Search results for: Boolean circuit

Authors: U. M. Swamy

Abstract:

A compact Hausdorff and totally disconnected topological space are known as Boolean space in view of the stone duality between Boolean algebras and such topological spaces. A sheaf over X is a triple (S, p, X) where S and X are topological spaces and p is a local homeomorphism of S onto X (that is, for each element s in S, there exist open sets U and G containing s and p(s) in S and X respectively such that the restriction of p to U is a homeomorphism of U onto G). Here we mainly concern on sheaves over Boolean spaces. From a given sheaf over a Boolean space, we obtain an algebraic structure in such a way that there is a one-to-one correspondence between these algebraic structures and sheaves over Boolean spaces.

Keywords: Boolean algebra, Boolean space, sheaf, stone duality

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Authors: Zhangquan Zhou, Guilin Qi

Abstract:

Materialization is an important reasoning service for applications built on the Web Ontology Language (OWL). To make materialization efficient in practice, current research focuses on deciding tractability of an ontology language and designing parallel reasoning algorithms. However, some well-known large-scale ontologies, such as YAGO, have been shown to have good performance for parallel reasoning, but they are expressed in ontology languages that are not parallelly tractable, i.e., the reasoning is inherently sequential in the worst case. This motivates us to study the problem of parallel tractability of ontology materialization from a theoretical perspective. That is we aim to identify the ontologies for which materialization is parallelly tractable, i.e., in the NC complexity. Since the NC complexity is defined based on Boolean circuit that is widely used to investigate parallel computing problems, we first transform the problem of materialization to evaluation of Boolean circuits, and then study the problem of parallel tractability based on circuits. In this work, we focus on datalog rewritable ontology languages. We use Boolean circuits to identify two classes of datalog rewritable ontologies (called parallelly tractable classes) such that materialization over them is parallelly tractable. We further investigate the parallel tractability of materialization of a datalog rewritable OWL fragment DHL (Description Horn Logic). Based on the above results, we analyze real-world datasets and show that many ontologies expressed in DHL belong to the parallelly tractable classes.

Keywords: ontology materialization, parallel reasoning, datalog, Boolean circuit

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Authors: Saurabh Rawat, Anushree Sah

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K Maps are generally and ideally, thought to be simplest form for obtaining solution of Boolean equations. Cubical Representation of Boolean equations is an alternate pick to incur a solution, otherwise to be meted out with Truth Tables, Boolean Laws, and different traits of Karnaugh Maps. Largest possible k- cubes that exist for a given function are equivalent to its prime implicants. A technique of minimization of Logic functions is tried to be achieved through cubical methods. The main purpose is to make aware and utilise the advantages of cubical techniques in minimization of Logic functions. All this is done with an aim to achieve minimal cost solution.r

Keywords: K-maps, don’t care conditions, Boolean equations, cubes

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Authors: Marcin Michalak

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Biclustering is the way of two-dimensional data analysis. For several years it became possible to express such issue in terms of Boolean reasoning, for processing continuous, discrete and binary data. The mathematical backgrounds of such approach — proved ability of induction of exact and inclusion–maximal biclusters fulfilling assumed criteria — are strong advantages of the method. Unfortunately, the core of the method has quite high computational complexity. In the paper the basics of Boolean reasoning approach for biclustering are presented. In such context the problems of computation parallelization are risen.

Keywords: Boolean reasoning, biclustering, parallelization, prime implicant

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Authors: Sekou Kangoye, Alexis Todoskoff, Mihaela Barreau

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Modified Condition/Decision Coverage (MC/DC) is a structural coverage criterion that aims to prove that all conditions involved in a Boolean expression can influence the result of that expression. In the context of automotive, MC/DC is highly recommended and even required for most security and safety applications testing. However, due to complex Boolean expressions that often embedded in those applications, generating a set of MC/DC compliant test cases for any of these expressions is a nontrivial task and can be time consuming for testers. In this paper we present an approach to automatically generate MC/DC test cases for any Boolean expression. We introduce novel techniques, essentially based on binary trees to quickly and optimally generate MC/DC test cases for the expressions. Thus, the approach can be used to reduce the manual testing effort of testers.

Keywords: binary trees, MC/DC, test case generation, nontrivial task

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Authors: Finley Lawson

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The triune nature of God is one of the most complex doctrines of Christianity, and its complexity is further compounded when one considers the incarnation. However, many of the difficulties and paradoxes associated with our idea of the divine arise from our adherence to reductionist ontology. In order to move our theological discourse forward, in respect to divine and human nature, a holistic interpretation of our profession of faith is necessary. The challenge of a holistic interpretation is that it questions our ability to make any statement about the genuine, ontological individuation of persons (both divine and human), and in doing so raises the issue of whether we are, ontologically, bound to descend in to a form of pan(en)theism. In order to address the ‘inevitable’ slide in to pan(en)theism. The impact of two forms of holistic interpretation, Boolean and Non-Boolean, on our concept of personhood will be examined. Whilst a Boolean interpretation allows for a greater understanding of the relational nature of the Trinity, it is the Non-Boolean interpretation which has greater ontological significance. A Non-Boolean ontology, grounded in our scientific understanding of the nature of the world, shows our quest for individuation rests not in ontological fact but in epistemic need, and that it is our limited epistemology that drives our need to divide that which is ontologically indivisible. This discussion takes place within a ‘methodological’, rather than ‘doctrinal’ approach to science and religion - examining assumptions and methods that have shaped our language and beliefs about key doctrines, rather than seeking to reconcile particular Christian doctrines with particular scientific theories. Concluding that Non-Boolean holism is the more significant for our doctrine is, in itself, not enough. A world without division appears much removed from the distinct place of man and divine as espoused in our creedal affirmation, to this end, several possible interpretations for understanding Non-Boolean human – divine relations are tentatively put forward for consideration.

Keywords: holism, individuation, ontology, Trinitarian relations

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Authors: Riddhi Jangid, Gajendra Pratap Singh

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Petri nets, a formalized modeling language that was introduced back around 50-60 years, have been widely used for modeling discrete event dynamic systems and simulating their behavior. Reachability analysis of Petri nets gives many insights into a modeled system. This idea leads us to study the reachability technique and use it in the reachability problem in the state space of reachable markings. With the same concept, Crisp Boolean Petri nets were defined in which the marking vectors that are boolean are distinct in the reachability analysis of the nets. We generalize the concept and define ‘Crisp’ Petri nets that generate the marking vectors exactly once in their reachability-based analysis, not necessarily Boolean.

Keywords: marking vector, n-vector, Petri nets, reachability

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Authors: Abdelkader Hadjoudja, Hajar Bouazza

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The PLD/CPLD devices are widely used for logic synthesis since several decades. Based on sum of product terms (PTs) architecture, the PLD/CPLD offer a high degree of flexibility to support various application requirements. They are suitable for large combinational logic, finite state machines as well as intensive I/O designs. CPLDs offer very predictable timing characteristics and are therefore ideal for critical control applications. This paper describes how the logic synthesis techniques, such as 1) XOR detection, 2) logic doubling, 3) complement of a Boolean function are combined, applied and used to optimize the CPLDs devices architecture that is based on PAL-like macrocells. Our goal is to use these techniques for minimizing the number of macrocells required to implement a circuit and minimize the delay of mapped circuit.

Keywords: CPLD, doubling, optimization, XOR

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Authors: Riddhi Jangid, Gajendra Pratap Singh

Abstract:

Petri nets, a mathematical tool, is used for modeling in different areas of computer sciences, biological networks, chemical systems and many other disciplines. A Petri net model of a given system is created by the graphical representation that describes the properties and behavior of the system. While looking for the behavior of any system, 1-safe Petri nets are of particular interest to many in the application part. Boolean Petri nets correspond to those class in 1- safe Petri nets that generate all the binary n-vectors in their reachability analysis. We study the class by changing different parameters like the token counts in the places and how the structure of the tree changes in the reachability analysis. We discuss here an extended class of Boolean Petri nets that generates n-ary trees in their reachability-based analysis.

Keywords: marking vector, n-vector, petri nets, reachability

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Authors: Fikre Belay Tekulu

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The Adigrat town lies in the Tigray region of Ethiopia. This region is mountainous and experiences a semiarid type of climate. Most of the rainfall occurs in four months of the year, which are June to September. During this season, flood is a common natural disaster, especially in urban areas. In this paper, an attempt is made to identify flood-prone areas in Adigrat town using Boolean logic with GIS and remote sensing techniques. Three parameters were incorporated as land use type, elevation, and slope. Boolean logic was used as land use equal to buildup land, elevation less than 2430 m, and slope less than 5 degrees. As a result, 0.575 km² was identified severely affected by floods during the rainy season.

Keywords: flood, GIS, hydrology, Adigrat

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Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

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This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

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Authors: Ali Khwaldeh, Nimer Adwan

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In this paper, a method for constructing a controlled balanced Boolean function satisfying the criterion of a Strictly Avalanche Criteria (SAC) effect is proposed. The proposed method is based on the use of three orthogonal nonlinear components which is unlike the high-order SAC functions. So, the generator synthesized by the proposed method has separate sets of control and information inputs. The proposed method proves its simplicity and the implementation ability. The proposed method allows synthesizing a SAC function generator with fixed control and information inputs. This ensures greater efficiency of the built-in oscillator compared to high-order SAC functions that can be used as a generator. Accordingly, the method is completely formalized and implemented as a software product.

Keywords: boolean function, controlled balanced boolean function, strictly avalanche criteria, orthogonal nonlinear

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Authors: Hoda Abugharsa

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In this paper we propose to design a sorter circuit using insertion sorting algorithm. The circuit will be designed using Algorithmic State Machines (ASM) method. That means converting the insertion sorting flowchart into an ASM chart. Then the ASM chart will be used to design the sorter circuit and the control unit.

Keywords: insert sorting algorithm, ASM chart, sorter circuit, state machine, control unit

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Authors: Hamdi Belgacem, Fradi Aymen

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In this paper we present a low power, low cost differential logic unit (LU). The proposed LU receives dual-rail inputs and generates dual-rail outputs. The proposed circuit can be used in Arithmetic and Logic Units (ALU) of processor. It can be also dedicated for self-checking applications based on dual duplication code. Four logic functions as well as their inverses are implemented within a single Logic Unit. The hardware overhead for the implementation of the proposed LU is lower than the hardware overhead required for standard LU implemented with standard CMOS logic style. This new implementation is attractive as fewer transistors are required to implement important logic functions. The proposed differential logic unit can perform 8 Boolean logical operations by using only 16 transistors. Spice simulations using a 32 nm technology was utilized to evaluate the performance of the proposed circuit and to prove its acceptable electrical behaviour.

Keywords: differential logic unit, double pass transistor logic, low power CMOS design, low cost CMOS design

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Authors: Samai'la Abdullahi

Abstract:

A graph is a pair of two set and so that a graph is a pictorial representation of a system using two basic element nodes and edges. A node is represented by a circle (either hallo shade) and edge is represented by a line segment connecting two nodes together. In this paper, we present a circuit network in the concept of graph theory application and also circuit models of graph are represented in logical connection method were we formulate matrix method of adjacency and incidence of matrix and application of truth table.

Keywords: euler circuit and path, graph representation of circuit networks, representation of graph models, representation of circuit network using logical truth table

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Authors: Pedro Luis Ferrer Penalver, Edmundo da Silva Braga

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In this paper, the performance of a simple surge protection for a direct current circuit was simulated. The protection circuit was developed from modified electric macro models of a gas discharge tube and a transient voltage suppressor diode. Moreover, a combination wave generator circuit was used as source of energy surges. The simulations showed that the circuit presented ensures immunity corresponding with test level IV of the IEC 61000-4-5:2014 international standard. The developed circuit can be modified to meet the requirements of any other equipment to be protected. Similarly, the parameters of the combination wave generator can be changed to provide different surge amplitudes.

Keywords: combination wave generator, IEC 61000-4-5, Pspice simulation, surge protection

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Authors: Shengqi Yu, Jinwei Zhao

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This paper presents a kind of analog circuit based temperature control system, which is mainly composed by threshold control signal circuit, synchronization signal circuit and trigger pulse circuit. Firstly, the temperature feedback signal function is realized by temperature sensor TS503F3950E. Secondly, the main control circuit forms the cycle controlled pulse signal to control the thyristor switching model. Finally two reverse paralleled thyristors regulate the output power by their switching state. In the consequence, this is a modernized and energy-saving domestic electric heating system.

Keywords: time base circuit, automatic control, zero-crossing trigger, temperature control

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Authors: Yuichi Kida, Takuro Kida

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In a new smart society supported by the recent development of 5G and 6G Communication systems, the im- portance of wireless power transmission is increasing. These systems contain discrete sampling systems in the middle of the transmission path and equivalent circuit representation of lossless or lossy power transmission through these systems is an important issue in circuit theory. In this paper, for the given weight function, we show that a lossless power transmission system with the given weight is expressed by an equivalent circuit representation of the Kida’s optimal signal prediction system followed by a reactance multi-port circuit behind it. Further, it is shown that, when the system is lossy, the system has an equivalent circuit in the form of connecting a multi-port positive-real circuit behind the Kida’s optimal signal prediction system. Also, for the convenience of the reader, in this paper, the equivalent circuit expression of the reactance multi-port circuit and the positive- real multi-port circuit by Cauer and Ohno, whose information is currently being lost even in the world of the Internet.

Keywords: signal prediction, pseudo inverse matrix, artificial intelligence, power transmission

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Authors: Davit Mirzoyan, Ararat Khachatryan

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A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: detection, monitoring, process corner, process variation

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Authors: Moustapha H. Ibrahim, Dahir Abdourahman

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This document presents a short-circuit fault detection process in a photovoltaic (PV) system. The proposed method is developed in MATLAB/Simulink. It determines whatever the size of the installation number of the short circuit module. The proposed algorithm indicates the presence or absence of an abnormality on the power of the PV system through measures of hourly global irradiation, power output, and ambient temperature. In case a fault is detected, it displays the number of modules in a short circuit. This fault detection method has been successfully tested on two different PV installations.

Keywords: PV system, short-circuit, fault detection, modelling, MATLAB-Simulink

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Authors: Presto Tri Sambodo, Suharjana, Galih Yoga Santiko

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Having an ideal body shape healthy body are the desire of everyone, both young and old. The purpose of this study was to determine: (1) the effect of block circuit training on aerobic fitness and body fat percentage, (2) the effect of non-block circuit training on aerobic fitness and body fat percentage, and (3) differences in the effect of exercise on block and non-circuit training block against aerobic fitness and body fat percentage. This research is an experimental research with the prestest posttest design Two groups design. The population in this study were 57 members of fat loss at GOR UNY Fitness Center. The retrieval technique uses purposive random sampling with a sample of 20 people. The instruments with rockport test (1.6 KM) and body fat percentage with a scale of bioelectrical impedance analysis omron (BIA). So it can be concluded the circuit training between block and non-block has a significant effect on aerobic fitness and body fat percentage. And for differences in the effect of circuit training between blocks and non-blocks, it is more influential on aerobic fitness than the percentage of body fat.

Keywords: circuit training, aerobic fitness, body fat percentage, healthy body

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Authors: Mohsen Bagheri, Ahmad Afifi

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This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on instrumentation amplifier and it is useful for reducing offset in Wheatstone bridge. The obtained gain is 645 with 1 μv/°c equivalent drift and 1.58 mw power consumption. A Schmitt trigger and multiplexer circuit control output node. A high speed counter is designed in this work. The proposed circuit is designed and simulated in 0.18 μm CMOS technology with 1.8 v power supply.

Keywords: piezoresistive accelerometer, zero offset, Schmitt trigger, bidirectional reversible counter

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Authors: M. Y. Ismail, M. Inam

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This paper presents equivalent circuit modeling of active planar reflectors which can be used for the detailed analysis and characterization of reflector performance in terms of lumped components. Equivalent circuit representation has been proposed for PIN diodes and liquid crystal based active planar reflectors designed within X-band frequency range. A very close agreement has been demonstrated between equivalent circuit results, 3D EM simulated results as well as measured scattering parameter results. In the case of measured results, a maximum discrepancy of 1.05dB was observed in the reflection loss performance, which can be attributed to the losses occurred during measurement process.

Keywords: Equivalent circuit modelling, planar reflectors, reflectarray antenna, PIN diode, liquid crystal

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Authors: Ararat Khachatryan, Davit Mirzoyan

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In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: aging effect, HCI, NBTI, nanoscale

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Authors: Hussein Al-bayaty

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This paper presents a novel idea to show the ability to benefit of the harmonic currents which are produced on the load side of the power grid. The proposed circuit contributes in reduction of the total harmonic distortion (THD) percentage through adding a high pass filter to draw harmonic currents with 150 Hz and multiple frequencies a and convert them to DC current and then reconvert it to AC current with 50 Hz frequency in order to feed different loads. The circuit has been designed, investigated and simulated in the MATLAB, Simulink program; the results will be assessed and compared the two cases: firstly, the system without adding the new circuit. Secondly, with adding the high pas filter circuit to the power system.

Keywords: harmonics elimination, passive filters, Total Harmonic Distortion (THD), filter circuit

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Authors: Pejman Hosseinioun, Abolghasem Ghasempour, Elham Gholami, Hamed Sarbazi

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Considering the development in global semiconductor technology, it is anticipated that gadgets such as diodes and resonant transistor tunnels (RTD/RTT), Single electron transistors (SET) and quantum cellular automata (QCA) will substitute CMOS (Complementary Metallic Oxide Semiconductor) gadgets in many applications. Unfortunately, these new technologies cannot disembark the common Boolean logic efficiently and are only appropriate for liminal logic. Therefor there is no doubt that with the development of these new gadgets it is necessary to find new MacDraw technologies which are compatible with them. Resonant transistor tunnels (RTD/RTT) and circuit MacDraw with enhanced computing abilities are candida for accumulating Nano criterion in the future. Quantum cellular automata (QCA) are also advent Nano technological gadgets for electrical circuits. Advantages of these gadgets such as higher speed, smaller dimensions, and lower consumption loss are of great consideration. QCA are basic gadgets in manufacturing gates, fuses and memories. Regarding the complex Nano criterion physical entity, circuit designers can focus on logical and constructional design to decrease complication in MacDraw. Moreover Single electron technology (SET) is another noteworthy gadget considered in Nano technology. This article is a survey in future of Nano technology in digital MacDraw.

Keywords: nano technology, resonant transistor tunnels, quantum cellular automata, semiconductor

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Authors: Patel Himeshkumar Ashokbhai, Suchit Sharma, Arvind Kumar Garg

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The purpose of this paper is to study the effect of change in feed rate on grinding circuit and cyclone efficiency in case of lead-zinc ore. The following experiments and analysis were conducted on beneficiation circuit of Sindesar Khurd (SK) mines under Hindustan Zinc Ltd. subsidiary of Vedanta Group of Companies, a leading producer of lead-Zinc, silver and cadmium (as by products) in India. Feed rate is an important variable in beneficiation circuit operation. Optimizing feed rate is indispensable for any grinding circuit and directly effects cyclone efficiency. The size analysis of ore in grinding circuit along with cyclone efficiency on varying feed rates establishes their interdependence. Feed rate determines retention time ore gets within grinding circuit. Retention time in turn determines degree of liberation of mineral. Inadequate liberation causes decreased circuit efficiency. In this paper we have studied the effect of varying feed rate on (1) D80 particle size of different sections of different streams of grinding circuit (2) Re-circulating load (3) Cyclone efficiency. As a conclusion, this study gives some clues to operate grinding circuits and hydro-cyclones in more efficient way regarding beneficiation of Lead-zinc ore.

Keywords: cyclone efficiency, feed rate, grinding circuit, re-circulating load

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Authors: Douglas Yeboah, Monishka Narayan, Jai Singh

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One of the key parameters in determining the power conversion efficiency (PCE) of organic solar cells (OSCs) is the open-circuit voltage, however, it is still not well understood. In order to examine the performance of OSCs, it is necessary to understand the losses associated with the open-circuit voltage and how best it can be improved. Here, an analytical expression for the open-circuit voltage of bulk heterojunction (BHJ) OSCs is derived from the charge carrier densities without considering the drift-diffusion current. The open-circuit voltage thus obtained is dependent on the donor-acceptor band gap, the energy difference between the highest occupied molecular orbital (HOMO) and the hole quasi-Fermi level of the donor material, temperature, the carrier density (electrons), the generation rate of free charge carriers and the bimolecular recombination coefficient. It is found that open-circuit voltage increases when the carrier density increases and when the temperature decreases. The calculated results are discussed in view of experimental results and agree with them reasonably well. Overall, this work proposes an alternative pathway for improving the open-circuit voltage in BHJ OSCs.

Keywords: charge carrier density, open-circuit voltage, organic solar cells, temperature

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Authors: Duanlei Yuan, Guangchao Yan, Zhanqing Chen, Xian Cheng

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This paper mainly focuses on the problem that high voltage circuit breaker’s closing and opening operation at random phase brings harmful electromagnetic transient effects on the power system. To repress the negative transient effects, a 35 kV SF6 phase-control circuit breaker equipped with electromagnetic force driving actuator is designed in this paper. Based on the constructed mathematical and structural models, the static magnetic field distribution and dynamic properties of the under loading actuator are simulated. The prototype of 35 kV SF6 phase-control circuit breaker is developed based on theories analysis and simulation. Tests are carried on to verify the operating reliability of the prototype. The developed circuit breaker can control its operating speed intelligently and switches with phase selection. Results of the tests and simulation prove that the phase-control circuit breaker is feasible for industrial applications.

Keywords: phase-control, circuit breaker, electromagnetic force driving actuator, tests and simulation

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Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

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In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

Procedia PDF Downloads 364