Search results for: trans conductance amplifier
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 186

Search results for: trans conductance amplifier

96 Reliability and Cost Focused Optimization Approach for a Communication Satellite Payload Redundancy Allocation Problem

Authors: Mehmet Nefes, Selman Demirel, Hasan H. Ertok, Cenk Sen

Abstract:

A typical reliability engineering problem regarding communication satellites has been considered to determine redundancy allocation scheme of power amplifiers within payload transponder module, whose dominant function is to amplify power levels of the received signals from the Earth, through maximizing reliability against mass, power, and other technical limitations. Adding each redundant power amplifier component increases not only reliability but also hardware, testing, and launch cost of a satellite. This study investigates a multi-objective approach used in order to solve Redundancy Allocation Problem (RAP) for a communication satellite payload transponder, focusing on design cost due to redundancy and reliability factors. The main purpose is to find the optimum power amplifier redundancy configuration satisfying reliability and capacity thresholds simultaneously instead of analyzing respectively or independently. A mathematical model and calculation approach are instituted including objective function definitions, and then, the problem is solved analytically with different input parameters in MATLAB environment. Example results showed that payload capacity and failure rate of power amplifiers have remarkable effects on the solution and also processing time.

Keywords: Communication satellite payload, multi-objective optimization, redundancy allocation problem, reliability, transponder.

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95 Closed form Delay Model for on-Chip VLSIRLCG Interconnects for Ramp Input for Different Damping Conditions

Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.

Keywords: Delay Modelling; On-Chip Interconnect; RLCGInterconnect; Ramp Input; Damping; VLSI

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94 Design and Implementation of a 10-bit SAR ADC

Authors: Hasmayadi Abdul Majid, Rohana Musa

Abstract:

This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC.

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93 Groundwater Potential Zone Identification in Unconsolidated Aquifer Using Geophysical Techniques around Tarbela Ghazi, District Haripur, Pakistan

Authors: Syed Muzyan Shahzad, Liu Jianxin, Asim Shahzad, Muhammad Sharjeel Raza, Sun Ya, Fanidi Meryem

Abstract:

Electrical resistivity investigation was conducted in vicinity of Tarbela Ghazi, in order to study the subsurface layer with a view of determining the depth to the aquifer and thickness of groundwater potential zones. Vertical Electrical Sounding (VES) using Schlumberger array was carried out at 16 VES stations. Well logging data at four tube wells have been used to mark the super saturated zones with great discharge rate. The present paper shows a geoelectrical identification of the lithology and an estimate of the relationship between the resistivity and Dar Zarrouk parameters (transverse unit resistance and longitudinal unit conductance). The VES results revealed both homogeneous and heterogeneous nature of the subsurface strata. Aquifer is unconfined to confine in nature, and at few locations though perched aquifer has been identified, groundwater potential zones are developed in unconsolidated deposits layers and more than seven geo-electric layers are observed at some VES locations. Saturated zones thickness ranges from 5 m to 150 m, whereas at few area aquifer is beyond 150 m thick. The average anisotropy, transvers resistance and longitudinal conductance values are 0.86 %, 35750.9821 Ω.m2, 0.729 Siemens, respectively. The transverse unit resistance values fluctuate all over the aquifer system, whereas below at particular depth high values are observed, that significantly associated with the high transmissivity zones. The groundwater quality in all analyzed samples is below permissible limit according to World Health Standard (WHO).

Keywords: Geoelectric layers, Dar Zarrouk parameters, Aquifer, Electro-stratigraphic.

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92 The Management in Large Emergency Situations – A Best Practise Case Study based on GIS for Management of Evacuation

Authors: Ion Baş, Claudiu Zoicaş, Angela Ioniţâ

Abstract:

In most of the cases, natural disasters lead to the necessity of evacuating people. The quality of evacuation management is dramatically improved by the use of information provided by decision support systems, which become indispensable in case of large scale evacuation operations. This paper presents a best practice case study. In November 2007, officers from the Emergency Situations Inspectorate “Crisana" of Bihor County from Romania participated to a cross-border evacuation exercise, when 700 people have been evacuated from Netherlands to Belgium. One of the main objectives of the exercise was the test of four different decision support systems. Afterwards, based on that experience, software system called TEVAC (Trans Border Evacuation) has been developed “in house" by the experts of this institution. This original software system was successfully tested in September 2008, during the deployment of the international exercise EU-HUROMEX 2008, the scenario involving real evacuation of 200 persons from Hungary to Romania. Based on the lessons learned and results, starting from April 2009, the TEVAC software is used by all Emergency Situations Inspectorates all over Romania.

Keywords: Emergency evacuation, Searching Features, TEVAC(Trans Border Evacuation) software system, User Interface Design.

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91 Digital Automatic Gain Control Integrated on WLAN Platform

Authors: Emilija Miletic, Milos Krstic, Maxim Piz, Michael Methfessel

Abstract:

In this work we present a solution for DAGC (Digital Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4 GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used enables gain control over Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The control over those signals is performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the average power of the baseband signal close to the desired set point. DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and actual gain setting, adjusting a gain factor of the accumulation, and applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.

Keywords: WLAN, AGC, RSSI, baseband processor

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90 WiMAX RoF Design for Cost Effective Access Points

Authors: Haruka Mikamori, Koyu Chinen

Abstract:

An optimized design of E/O and O/E for access points of WiMAX RoF was carried out by evaluating RCE. The use of the DFB-LD, a low input-impedance driving, a low distortion PIN-PD, and a high gain EPHEMT amplifier is promising the cost-effective design. For the uplink RoF design, the use of EDFA and EP-HEMT amplifiers is necessity.

Keywords: WiMAX, RoF, RCE, RAU, Access Point

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89 Performance Enhancement of DWDM Systems Using HTE Configuration HTE Configuration for 1479-1555nm Wavelength Range

Authors: Inderpreet Kaur, Neena Gupta

Abstract:

In this paper, the gain spectrum of EDFA has been broadened by implementing HTE configuration for S and C band. On using this configuration an amplification bandwidth of 76nm ranging from 1479nm to 1555nm with a peak gain of 26dB has been obtained.

Keywords: C band, DWDM system, EDFA, Gain, HTE, Hybrid Fiber Amplifier, S band.

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88 Highly-Efficient Photoreaction Using Microfluidic Device

Authors: Shigenori Togashi, Yukako Asano

Abstract:

We developed an effective microfluidic device for photoreactions with low reflectance and good heat conductance. The performance of this microfluidic device was tested by carrying out a photoreactive synthesis of benzopinacol and acetone from benzophenone and 2-propanol. The yield reached 36% with an irradiation time of 469.2 s and was improved by more than 30% when compared to the values obtained by the batch method. Therefore, the microfluidic device was found to be effective for improving the yields of photoreactions.

Keywords: Microfluidic device, Photoreaction, Benzophenone, Black Aluminum Oxide, Detection, Yield Improvement.

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87 Design and Implementation of a 10-bit SAR ADC with A Programmable Reference

Authors: Hasmayadi Abdul Majid, Yuzman Yusoff, Noor Shelida Salleh

Abstract:

This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. The ADC consumed less than 7.5 mW power with a 3 V supply.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Resistive DAC, Programmable Reference.

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86 The COVID-19 Pandemic: Lessons Learned in Promoting Student Internationalisation

Authors: David Cobham

Abstract:

In higher education, a great degree of importance is placed on the internationalisation of the student experience. This is seen as a valuable contributor to elements such as building confidence, broadening knowledge, creating networks, and connections and enhancing employability for current students who will become the next generation of managers in technology and business. The COVID-19 pandemic has affected all areas of people’s lives. The limitations of travel coupled with the fears and concerns generated by the health risks have dramatically reduced the opportunity for students to engage with this agenda. Institutions of higher education have been required to rethink fundamental aspects of their business model from recruitment and enrolment, through learning approaches, assessment methods and the pathway to employment. This paper presents a case study which focuses on student mobility and how the physical experience of being in another country either to study, to work, to volunteer or to gain cultural and social enhancement has of necessity been replaced by alternative approaches. It considers trans-national education as an alternative to physical study overseas, virtual mobility and internships as an alternative to international work experience and adopting collaborative on-line projects as an alternative to in-person encounters. The paper concludes that although these elements have been adopted to address the current situation, the lessons learnt and the feedback gained suggests that they have contributed successfully in new and sometimes unexpected ways, and that they will persist beyond the present to become part of the "new normal" for the future. That being the case, senior leaders of institutions of higher education will be required to revisit their international plans and to rewrite their international strategies to take account of and build upon these changes.

Keywords: Trans-national education, internationalisation, higher education management, virtual mobility.

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85 Digital Predistorter with Pipelined Architecture Using CORDIC Processors

Authors: Kyunghoon Kim, Sungjoon Shim, Jun Tae Kim, Jong Tae Kim

Abstract:

In a wireless communication system, a predistorter(PD) is often employed to alleviate nonlinear distortions due to operating a power amplifier near saturation, thereby improving the system performance and reducing the interference to adjacent channels. This paper presents a new adaptive polynomial digital predistorter(DPD). The proposed DPD uses Coordinate Rotation Digital Computing(CORDIC) processors and PD process by pipelined architecture. It is simpler and faster than conventional adaptive polynomial DPD. The performance of the proposed DPD is proved by MATLAB simulation.

Keywords: DPD, CORDIC.

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84 Temperature Sensor IC Design for Intracranial Monitoring Device

Authors: Wai Pan Chan, Minkyu Je

Abstract:

A precision CMOS chopping amplifier is adopted in this work to improve a CMOS temperature sensor high sensitive enough for intracranial temperature monitoring. An amplified temperature sensitivity of 18.8 ± 3*0.2 mV/oC is attained over the temperature range from 20 oC to 80 oC from a given 10 samples of the same wafer. The analog frontend design outputs the temperature dependent and the temperature independent signals which can be directly interfaced to a 10 bit ADC to accomplish an accurate temperature instrumentation system.

Keywords: Chopping, analog frontend, CMOS temperature sensor, traumatic brain injury (TBI), intracranial temperature monitoring.

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83 Coherent PON for NG-PON2: 40Gbps Downstream Transmission with 40dB Power Margin using Commercial DFB Lasers and no Optical Amplification

Authors: Roberto Gaudino, Antonino Nespola, Dario Zeolla, Stefano Straullu, Vittorio Curri, Gabriella Bosco, Roberto Cigliutti, Stefano Capriata, Paolo Solina.

Abstract:

We demonstrate a 40Gbps downstream PON transmission based on PM-QPSK modulation using commercial DFB lasers without optical amplifier in the ODN, obtaining 40dB power budget. We discuss this solution within NG-PON2 architectures.

Keywords: DFB lasers, Optical Coherent Receiver, Passive Optical Networks.

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82 Design and Simulation Interface Circuit for Piezoresistive Accelerometers with Offset Cancellation Ability

Authors: Mohsen Bagheri, Ahmad Afifi

Abstract:

This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on Instrumentation amplifier and it is useful for reducing offset In Wheatstone Bridge. The obtained gain is 645 with 1μv/°c Equivalent drift and 1.58mw power consumption. A Schmitt trigger and multiplexer circuit control output node. a high speed counter is designed in this work .the proposed circuit is designed and simulated In 0.18μm CMOS technology with 1.8v power supply.

Keywords: Piezoresistive accelerometer, zero offset, Schmitt trigger, bidirectional reversible counter

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81 Experimental Verification of the Relationship between Physiological Indexes and the Presence or Absence of an Operation during E-learning

Authors: Masaki Omata, Shumma Hosokawa

Abstract:

An experiment to verify the relationships between physiological indexes of an e-learner and the presence or absence of an operation during e-learning is described. Electroencephalogram (EEG), hemoencephalography (HEG), skin conductance (SC), and blood volume pulse (BVP) values were measured while participants performed experimental learning tasks. The results show that there are significant differences between the SC values when reading with clicking on learning materials and the SC values when reading without clicking, and between the HEG ratio when reading (with and without clicking) and the HEG ratio when resting for four of five participants. We conclude that the SC signals can be used to estimate whether or not a learner is performing an active task and that the HEG ratios can be used to estimate whether a learner is learning.

Keywords: E-learning, physiological index, physiological signal, state of learning.

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80 Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity

Authors: P. Prasad Rao, K. Lal Kishore

Abstract:

Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18

Keywords: 1.5 bits/stage, Conversion Frequency, Redundancy Switched Capacitor Sample and Hold Circuit

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79 Design a Low Voltage- Low Offset Class AB Op-Amp

Authors: B.Gholami, S.Gholami, A.Forouzantabar, Sh.Bazyari

Abstract:

A new design approach for three-stage operational amplifiers (op-amps) is proposed. It allows to actually implement a symmetrical push-pull class-AB amplifier output stage for wellestablished three-stage amplifiers using a feedforward transconductance stage. Compared with the conventional design practice, the proposed approach leads to a significant improvement of the symmetry between the positive and the negative op-amp step response, resulting in similar values of the positive/negative settling time. The new approach proves to be very useful in order to fully exploit the potentiality allowed by the op-amp in terms of speed performances. Design examples in a commercial 0.35-μm CMOS prove the effectiveness of theproposed strategy.

Keywords: Low-voltage op amp, design , optimum design

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78 High-Speed High-Gain CMOS OTA for SC Applications

Authors: M.Yousefi, A.Vatanjou, F.Nazeri

Abstract:

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained is 1.15GHz. These results confirm that adding extra paths for signal can improve DC gain and UGB of folded-cascode significantly.

Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW)

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77 Realization of Electronically Controllable Current-mode Square-rooting Circuit Based on MO-CFTA

Authors: P. Silapan, C. Chanapromma, T. Worachak

Abstract:

This article proposes a current-mode square-rooting circuit using current follower transconductance amplifier (CTFA). The amplitude of the output current can be electronically controlled via input bias current with wide input dynamic range. The proposed circuit consists of only single CFTA. Without any matching conditions and external passive elements, the circuit is then appropriate for an IC architecture. The magnitude of the output signal is temperature-insensitive. The PSpice simulation results are depicted, and the given results agree well with the theoretical anticipation. The power consumption is approximately 1.96mW at ±1.5V supply voltages.

Keywords: CFTA, Current-mode, Square-rooting Circuit

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76 A Digitally Programmable Voltage-mode Multifunction Biquad Filter with Single-Output

Authors: C. Ketviriyakit, W. Kongnun, C. Chanapromma, P. Silapan

Abstract:

This article proposes a voltage-mode multifunction filter using differential voltage current controllable current conveyor transconductance amplifier (DV-CCCCTA). The features of the circuit are that: the quality factor and pole frequency can be tuned independently via the values of capacitors: the circuit description is very simple, consisting of merely 1 DV-CCCCTA, and 2 capacitors. Without any component matching conditions, the proposed circuit is very appropriate to further develop into an integrated circuit. Additionally, each function response can be selected by suitably selecting input signals with digital method. The PSpice simulation results are depicted. The given results agree well with the theoretical anticipation.

Keywords: DV-CCCCTA, Voltage-mode, Multifunction filter

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75 PSRR Enhanced LDO Regulator Using Noise Sensing Circuit

Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

Abstract:

In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor.

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74 Design Optimization for Efficient Erbium-Doped Fiber Amplifiers

Authors: Parekhan M. Aljaff, Banaz O. Rasheed

Abstract:

The exact gain shape profile of erbium doped fiber amplifiers (EDFA`s) are depends on fiber length and Er3 ion densities. This paper optimized several of erbium doped fiber parameters to obtain high performance characteristic at pump wavelengths of λp= 980 nm and λs= 1550 nm for three different pump powers. The maximum gain obtained for pump powers (10, 30 and 50mw) is nearly (19, 30 and 33 dB) at optimizations. The required numerical aperture NA to obtain maximum gain becomes less when pump power increased. The amplifier gain is increase when Er+3doped near the center of the fiber core. The simulation has been done by using optisystem 5.0 software (CAD for Photonics, a license product of a Canadian based company) at 2.5 Gbps.

Keywords: EDFA, Erbium Doped Fiber, optimization OpticalAmplifiers.

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73 Realization of Electronically Tunable Current- Mode Multiphase Sinusoidal Oscillators Using CFTAs

Authors: Prungsak Uttaphut

Abstract:

An implementation of current-mode multiphase sinusoidal oscillators is presented. Using CFTA-based lossy integrators, odd and odd/even phase systems can be realized with following advantages. The condition of oscillation and frequency of oscillation can be orthogonally tuned. The high output impedances facilitate easy driving an external load without additional current buffers. The proposed MSOs provide odd or even phase signals that are equally spaced in phase and equal amplitude. The circuit requires one CFTA, one resistor and one grounded capacitor per phase without additional current amplifier. The results of PSPICE simulations using CMOS CFTA are included to verify theory.

Keywords: multiphase sinusoidal oscillator, current-mode, CFTA, lossy integrator

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72 An Investigation into the Isolation and Bandwidth Characteristics of X-Band Chireix PA Combiners

Authors: D. P. Clayton, E. A. Ball

Abstract:

This paper describes an investigation into the isolation characteristics and bandwidth performance of radio frequency (RF) combiners that are used as part of Chireix power amplifier (PA) architectures, designed for use in the X-Band range of frequencies. Combiner designs investigated are the typical Chireix and Wilkinson configurations which also include simulation of the Wilkinson using manufacturer’s data for the isolation resistor. Another simulation was the less common approach of using a Branchline coupler to form the combiner, as well as simulation results from adding an additional stage. This paper presents the findings of this investigation and compares the bandwidth performance and isolation characteristics to determine suitability.

Keywords: Bandwidth, Chireix, couplers, outphasing, power amplifiers, Wilkinson, X-Band.

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71 A 0.9 V, High-Speed, Low-Power Tunable Gain Current Mirror

Authors: Hassan Faraji Baghtash

Abstract:

A high-speed current mirror with low-power method of adjusting current gain is presented. The current mirror provides continuous gain adjustment; yet, its gain can simply be programmed digitally, as well. The structure features the ever interesting merits of linear-in-dB gain control scheme and low power/voltage operation. The performance of proposed structure is verified through the simulation in TSMC 0.18 µm CMOS Technology. The proposed tunable gain current mirror structure draws only 18 µW from 0.9 V power supply and can operate at high frequencies up to 550 MHz in the worst case condition of maximum gain setting.

Keywords: Current mirror, current mode, low power, low voltage, tunable circuit, variable current amplifier.

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70 An Approach to Flatten the Gain of Fiber Raman Amplifiers with Multi-Pumping

Authors: Surinder Singh, Adish Bindal

Abstract:

The effects of the pumping wavelength and their power on the gain flattening of a fiber Raman amplifier (FRA) are investigated. The multi-wavelength pumping scheme is utilized to achieve gain flatness in FRA. It is proposed that gain flatness becomes better with increase in number of pumping wavelengths applied. We have achieved flat gain with 0.27 dB fluctuation in a spectral range of 1475-1600 nm for a Raman fiber length of 10 km by using six pumps with wavelengths with in the 1385-1495 nm interval. The effect of multi-wavelength pumping scheme on gain saturation in FRA is also studied. It is proposed that gain saturation condition gets improved by using this scheme and this scheme is more useful for higher spans of Raman fiber length.

Keywords: FRA, gain, pumping, WDM.

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69 Design of a Carbon Silicon Electrode for Iontophoresis Treatment towards Alopecia

Authors: Q. Wei, D. G. Hwang, Z. Mohy-Udin, D. H. Shin, J. H. Park, M. Y. Kang, J. H. Cho

Abstract:

This study presents design of a carbon silicon electrode for iontophorsis treatment towards alopecia. The alopecia is a medical description means loss of hair from the body. For solving this problem, the drug need to be delivered into the scalp, therefore, the iontophoresis was chosen to use in this treatment. However, almost common electrodes of iontophoresis device are made with metal material, the electrodes could give patients hurt when they using it, and it is hard to avoid the hair for attaching the hair. For this reason, an electrode is made with silicon material to decrease the hurt from the electrodes, and the carbon material is mixed in it for increasing conductance. The several cones with stainless material on the electrode make the electrode is able to void hair to attach the affected part. According to the results of a vivo-experiment, the carbon silicon electrode showed a good performance and in treatment comfortably.

Keywords: Carbon silicon, drug delivery system, iontophoresis

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68 Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology

Authors: H. Daoud Dammak, S. Bensalem, S. Zouari, M. Loulou

Abstract:

This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35μm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz in strong inversion mode. In moderate inversion mode, it has a 92dB DC gain and provides a gain bandwidth product of around 69MHz. The OTA circuit has a DC gain of 75.5dB and unity-gain frequency limited to 19.14MHZ in weak inversion region.

Keywords: CMOS IC design, Folded Cascode OTA, gm/ID methodology, optimization.

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67 Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Authors: Muhaned Zaidi, Ian Grout, Abu Khari bin A’ain

Abstract:

In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process.

Keywords: Op-amp, rail-to-rail output, Miller compensation, negative Miller capacitance.

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