Digital Predistorter with Pipelined Architecture Using CORDIC Processors
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 33093
Digital Predistorter with Pipelined Architecture Using CORDIC Processors

Authors: Kyunghoon Kim, Sungjoon Shim, Jun Tae Kim, Jong Tae Kim

Abstract:

In a wireless communication system, a predistorter(PD) is often employed to alleviate nonlinear distortions due to operating a power amplifier near saturation, thereby improving the system performance and reducing the interference to adjacent channels. This paper presents a new adaptive polynomial digital predistorter(DPD). The proposed DPD uses Coordinate Rotation Digital Computing(CORDIC) processors and PD process by pipelined architecture. It is simpler and faster than conventional adaptive polynomial DPD. The performance of the proposed DPD is proved by MATLAB simulation.

Keywords: DPD, CORDIC.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1329074

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1787

References:


[1] J. K. Cavers, "Amplifier Linearization Using a Digital Predistorter with Fast Adaptation and Low Memory Requirements," IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 39. NO. 4 pp. 374-382, NOVEMBER 1990.
[2] J. Namiki, "An automatically controlled predistorter for multilevel quadrature amplitude modulation," IEEE Trans Commun., vol. COM-3 1, pp 707-712, May 1983.
[3] D. Hilbom, S. Stapleton, and J. Cavers, "An adaptive direct conversion transmitter," in Proc. IEEE Vehicular Technol. Conf, Boulder, CO, May 1992.
[4] Y. Nagata, "Linear amplification technique for digital mobile communications,"in Proc. IEEE Vehicular Technol. Conf, May 1989, pp 159-164.
[5] J. K. Cavers "Amplifier linearization using a digital predistorter with fast adaptation and low memory requirements," IEEE Trans. Vehicular Technol., vol. 39, pp 374-382, Nov. 1990.
[6] K. J. Muhonenm, K. Kavehrad, "Look-Up Table Techniques for Adaptive Digital Predistortion: A Development and Comparison," IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 49, NO. 5, pp. 1995-2002, SEPTEMBER 2000
[7] M. Ghaderi, S. Kumar, D. E. Dodds, "Fast adaptive polynomial I and Q predistorter with globaloptimization," Communications, IEE Proceedings, VOL. 143, No. 2, pp. 78-86, April 1996.
[8] E. Westesson, L. Sundström, "Low-Power Complex Polynomial Predistorter Circuit in CMOS for RF Power Amplifier Linearization," Solid-State conference, 2001. ESSCIRC 201. Proceddings of the 27th European, pp. 486-489, September 2001.
[9] B. Parhami, "Computer Arithmetic : Algorithms and Hardware Designs," pp. 361-377, Oxford University Press, Inc. 2000.