Search results for: static power reduction.
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 4761

Search results for: static power reduction.

4671 Loss Reduction and Reliability Improvement of Industrial Distribution System through Network Reconfiguration

Authors: Ei Ei Phyu, Kyaw Myo Lin, Thin Thin Moe

Abstract:

The paper presents an approach to improve the reliability and reduce line losses of practical distribution system applying network reconfiguration. The change of the topology redirects the power flow within the distribution network to obtain better performance of the system. Practical distribution network (Pyigyitagon Industrial Zone (I)) is used as the case study network. The detailed calculations of the reliability indices are done by using analytical method and power flow calculation is performed by Newton-Rephason solver. The comparison of various network reconfiguration techniques are described with respect to power loss and reliability index levels. Finally, the optimal reconfigured network is selected among difference cases based on the two factors: the most reliable network and the least loss minimization.

Keywords: Distribution system reliability, loss reduction, network reconfiguration, reliability enhancement, reliability indices.

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4670 Simulation of Static Frequency Converter for Synchronous Machine Operation and Investigation of Shaft Voltage

Authors: Arun Kumar Datta, M. A. Ansari, N. R. Mondal, B. V. Raghavaiah, Manisha Dubey, Shailendra Jain

Abstract:

This study is carried out to understand the effects of Static frequency converter (SFC) on large machine. SFC has a feature of four quadrant operations. By virtue of this it can be implemented to run a synchronous machine either as a motor or alternator. This dual mode operation helps a single machine to start & run as a motor and then it can be converted as an alternator whenever required. One such dual purpose machine is taken here for study. This machine is installed at a laboratory carrying out short circuit test on high power electrical equipment. SFC connected with this machine is broadly described in this paper. The same SFC has been modeled with the MATLAB/Simulink software. The data applied on this virtual model are the actual parameters from SFC and synchronous machine. After running the model, simulated machine voltage and current waveforms are validated with the real measurements. Processing of these waveforms is done through Fast Fourier Transformation (FFT) which reveals that the waveforms are not sinusoidal rather they contain number of harmonics. These harmonics are the major cause of generating shaft voltage. It is known that bearings of electrical machine are vulnerable to current flow through it due to shaft voltage. A general discussion on causes of shaft voltage in perspective with this machine is presented in this paper.

Keywords: Alternators, AC-DC power conversion, capacitive coupling, electric discharge machining, frequency converter, Fourier transforms, inductive coupling, simulation, Shaft voltage, synchronous machines, static excitation, thyristor.

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4669 Electrical Characteristics of SCR - based ESD Device for I/O and Power Rail Clamp in 0.35um Process

Authors: Yong Seo Koo, Dong Su Kim, Byung Seok Lee, Won Suk Park, Bo Bea Song

Abstract:

This paper presents a SCR-based ESD protection devices for I/O clamp and power rail clamp, respectably. These devices have a low trigger voltage and high holding voltage characteristics than conventional SCR device. These devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) processes. These devices were validated using a TLP system. From the experimental results, the device for I/O ESD clamp has a trigger voltage of 5.8V. Also, the device for power rail ESD clamp has a holding voltage of 7.7V.

Keywords: ESD (Electro-Static Discharge), ESD protection device, SCR (Silicon Controlled Rectifier), Latch-up

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4668 Representation of Power System for Electromagnetic Transient Calculation

Authors: P. Sowa

Abstract:

The new idea of analyze of power system failure with use of artificial neural network is proposed. An analysis of the possibility of simulating phenomena accompanying system faults and restitution is described. It was indicated that the universal model for the simulation of phenomena in whole analyzed range does not exist. The main classic method of search of optimal structure and parameter identification are described shortly. The example with results of calculation is shown.

Keywords: Dynamic equivalents, Network reduction, Neural networks, Power system analysis.

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4667 A Comparative Study on Seismic Provisions Made in UBC-1997 and Saudi Building Code for RC Buildings

Authors: S. Nazar, M. A. Ismaeil

Abstract:

This paper presents a comparative study of static analysis procedure for seismic performance based on UBC-1997 and SBC-301-2007(Saudi Arabia). These building codes define different ductility classes and corresponding response reduction factors based on material, configuration and detailing of reinforcements. Codes differ significantly in specifying the procedures to estimate base shear, drift and effective stiffness of structural members. One of the major improvements made in new SBC (based on IBC-2003) is ground motion parameters used for seismic design. In old SBC (based on UBC) maps have been based on seismic zones. However new SBC provide contour maps giving spectral response quantities. In this approach, a case study of RC frame building located in two different cities and with different ductility classes has been performed. Moreover, equivalent static method based on SBC-301 and UBC-1997 is used to explore the variation in results based on two codes, particularly design base shear, lateral loads and story drifts.

Keywords: Ductility Classes, Equivalent Static method, RC Frames, SBC-301-2007, Story drifts, UBC-1997.

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4666 A Single-Phase Register File with Complementary Pass-Transistor Adiabatic Logic

Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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4665 Control of Pressure Gradient in the Contraction of a Wind Tunnel

Authors: Dehghan Manshadi M., Mirzaei M., Soltani M. R., Ghorbanian K.

Abstract:

Subsonic wind tunnel experiments were conducted to study the effect of tripped boundary layer on the pressure distribution in the contraction region of the tunnel. Measurements were performed by installing trip strip at two different positions in the concave portion of the contraction. The results show that installation of the trip strips, have significant effects on both turbulence and pressure distribution. The reduction in the free stream turbulence and reduction of the wall static pressure distribution deferred signified with the location of the trip strip.

Keywords: Contraction, pressure distribution, trip strip, turbulence intensity.

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4664 New Strategy Agents to Improve Power System Transient Stability

Authors: Mansour A. Mohamed, George G. Karady, Ali M. Yousef

Abstract:

This paper proposes transient angle stability agents to enhance power system stability. The proposed transient angle stability agents divided into two strategy agents. The first strategy agent is a prediction agent that will predict power system instability. According to the prediction agent-s output, the second strategy agent, which is a control agent, is automatically calculating the amount of active power reduction that can stabilize the system and initiating a control action. The control action considered is turbine fast valving. The proposed strategies are applied to a realistic power system, the IEEE 50- generator system. Results show that the proposed technique can be used on-line for power system instability prediction and control.

Keywords: Multi-agents, Fast Valving, Power System Transient Stability, Prediction methods,

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4663 Generalized Noise Analysis of Log Domain Static Translinear Circuits

Authors: E. Farshidi

Abstract:

This paper presents a new general technique for analysis of noise in static log-domain translinear circuits. It is demonstrated that employing this technique, leads to a general, simple and routine method of the noise analysis. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.

Keywords: Noise analysis, log-domain, static, dynamic, translinear loop, companding.

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4662 Improved Modulo 2n +1 Adder Design

Authors: Somayeh Timarchi, Keivan Navi

Abstract:

Efficient modulo 2n+1 adders are important for several applications including residue number system, digital signal processors and cryptography algorithms. In this paper we present a novel modulo 2n+1 addition algorithm for a recently represented number system. The proposed approach is introduced for the reduction of the power dissipated. In a conventional modulo 2n+1 adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit circuits, the diminished-1 and carry save diminished-1 number systems can be effectively used in applications. In the paper, we also derive two new architectures for designing modulo 2n+1 adder, based on n-bit ripple-carry adder. The first architecture is a faster design whereas the second one uses less hardware. In the proposed method, the special treatment required for zero operands in Diminished-1 number system is removed. In the fastest modulo 2n+1 adders in normal binary system, there are 3-operand adders. This problem is also resolved in this paper. The proposed architectures are compared with some efficient adders based on ripple-carry adder and highspeed adder. It is shown that the hardware overhead and power consumption will be reduced. As well as power reduction, in some cases, power-delay product will be also reduced.

Keywords: Modulo 2n+1 arithmetic, residue number system, low power, ripple-carry adders.

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4661 Static Analysis and Pseudostatic Slope Stability

Authors: Meftah Ali

Abstract:

This article aims to analyze the static stability and pseudostatic slope by using different methods such as: Bishop method, Junbu, Ordinary, Morgenstern-price and GLE. The two dimensional modeling of slope stability under various loading as: the earthquake effect, the water level and road mobile charges. The results show that the slope is stable in the static case without water, but in other cases, the slope lost its stability and give unstable. The calculation of safety factor is to evaluate the stability of the slope using the limit equilibrium method despite the difference between the results obtained by these methods that do not rely on the same assumptions. In the end, the results of this study illuminate well the influence of the action of water, moving loads and the earthquake on the stability of the slope.

Keywords: Slope stability, pseudo static, safety factor, limit equilibrium.

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4660 A Multiobjective Damping Function for Coordinated Control of Power System Stabilizer and Power Oscillation Damping

Authors: Jose D. Herrera, Mario A. Rios

Abstract:

This paper deals with the coordinated tuning of the Power System Stabilizer (PSS) controller and Power Oscillation Damping (POD) Controller of Flexible AC Transmission System (FACTS) in a multi-machine power systems. The coordinated tuning is based on the critical eigenvalues of the power system and a model reduction technique where the Hankel Singular Value method is applied. Through the linearized system model and the parameter-constrained nonlinear optimization algorithm, it can compute the parameters of both controllers. Moreover, the parameters are optimized simultaneously obtaining the gains of both controllers. Then, the nonlinear simulation to observe the time response of the controller is performed.

Keywords: Balanced realization, controllability Grammian, electromechanical oscillations, FACTS, Hankel singular values, observability Grammian, POD, PSS.

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4659 Low Complexity Peak-to-Average Power Ratio Reduction in Orthogonal Frequency Division Multiplexing System by Simultaneously Applying Partial Transmit Sequence and Clipping Algorithms

Authors: V. Sudha, D. Sriram Kumar

Abstract:

Orthogonal Frequency Division Multiplexing (OFDM) has been used in many advanced wireless communication systems due to its high spectral efficiency and robustness to frequency selective fading channels. However, the major concern with OFDM system is the high peak-to-average power ratio (PAPR) of the transmitted signal. Some of the popular techniques used for PAPR reduction in OFDM system are conventional partial transmit sequences (CPTS) and clipping. In this paper, a parallel combination/hybrid scheme of PAPR reduction using clipping and CPTS algorithms is proposed. The proposed method intelligently applies both the algorithms in order to reduce both PAPR as well as computational complexity. The proposed scheme slightly degrades bit error rate (BER) performance due to clipping operation and it can be reduced by selecting an appropriate value of the clipping ratio (CR). The simulation results show that the proposed algorithm achieves significant PAPR reduction with much reduced computational complexity.

Keywords: CCDF, OFDM, PAPR, PTS.

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4658 Off-State Leakage Power Reduction by Automatic Monitoring and Control System

Authors: S. Abdollahi Pour, M. Saneei

Abstract:

This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 10 μW for 32nm technology and about 12 μW for 65nm technology at the same power supply voltage as the core power supply. Moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop.

Keywords: leakage current, leakage power monitor, body biasing, low power

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4657 PAPR Reduction of FBMC Using Sliding Window Tone Reservation Active Constellation Extension Technique

Authors: V. Sandeep Kumar, S. Anuradha

Abstract:

The high Peak to Average Power Ratio (PAR) in Filter Bank Multicarrier with Offset Quadrature Amplitude Modulation (FBMC-OQAM) can significantly reduce power efficiency and performance. In this paper, we address the problem of PAPR reduction for FBMC-OQAM systems using Tone Reservation (TR) technique. Due to the overlapping structure of FBMCOQAM signals, directly applying TR schemes of OFDM systems to FBMC-OQAM systems is not effective. We improve the tone reservation (TR) technique by employing sliding window with Active Constellation Extension for the PAPR reduction of FBMC-OQAM signals, called sliding window tone reservation Active Constellation Extension (SW-TRACE) technique. The proposed SW-TRACE technique uses the peak reduction tones (PRTs) of several consecutive data blocks to cancel the peaks of the FBMC-OQAM signal inside a window, with dynamically extending outer constellation points in active(data-carrying) channels, within margin-preserving constraints, in order to minimize the peak magnitude. Analysis and simulation results compared to the existing Tone Reservation (TR) technique for FBMC/OQAM system. The proposed method SW-TRACE has better PAPR performance and lower computational complexity.

Keywords: FBMC-OQAM, peak-to-average power ratio, sliding window, tone reservation Active Constellation Extension.

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4656 A Thermodynamic Solution for the Static and Dynamic Characteristics of a Two-Lobe Journal Bearing

Authors: B. Chetti, W. A. Crosby

Abstract:

The work described in this paper is an investigation of the static and dynamic characteristics of two-lobe journal bearings taking into consideration the thermal effects. A thermo-hydrodynamic solution of a finite two-lobe journal bearing is performed by solving the generalized form Reynolds equation with the energy equation, taking into consideration viscosity variation across the film thickness. The static and dynamic characteristics were numerically obtained. The results are evaluated for different values of viscosity-temperature coefficient and Peclet number. The results show that considering the thermal effects in the solution of the two-lobe journal bearing has a marked on the study of its stability.

Keywords: Two-lobe bearing, thermal effect, static and dynamic characteristics.

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4655 Fuzzy C-Means Clustering Algorithm for Voltage Stability in Large Power Systems

Authors: Mohamad R. Khaldi, Christine S. Khoury, Guy M. Naim

Abstract:

The steady-state operation of maintaining voltage stability is done by switching various controllers scattered all over the power network. When a contingency occurs, whether forced or unforced, the dispatcher is to alleviate the problem in a minimum time, cost, and effort. Persistent problem may lead to blackout. The dispatcher is to have the appropriate switching of controllers in terms of type, location, and size to remove the contingency and maintain voltage stability. Wrong switching may worsen the problem and that may lead to blackout. This work proposed and used a Fuzzy CMeans Clustering (FCMC) to assist the dispatcher in the decision making. The FCMC is used in the static voltage stability to map instantaneously a contingency to a set of controllers where the types, locations, and amount of switching are induced.

Keywords: Fuzzy logic, Power system control, Reactive power control, Voltage control

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4654 A Blind SLM Scheme for Reduction of PAPR in OFDM Systems

Authors: K. Kasiri, M. J. Dehghani

Abstract:

In this paper we propose a blind algorithm for peakto- average power ratio (PAPR) reduction in OFDM systems, based on selected mapping (SLM) algorithm as a distortionless method. The main drawback of the conventional SLM technique is the need for transmission of several side information bits, for each data block, which results in loss in data rate transmission. In the proposed method some special number of carriers in the OFDM frame is reserved to be rotated with one of the possible phases according to the number of phase sequence blocks in SLM algorithm. Reserving some limited number of carriers wont effect the reduction in PAPR of OFDM signal. Simulation results show using ML criteria at the receiver will lead to the same system-performance as the conventional SLM algorithm, while there is no need to send any side information to the receiver.

Keywords: Orthogonal Frequency Division Multiplexing(OFDM), Peak-to-Average Power Ratio (PAPR), Selected Mapping(SLM), Blind SLM (BSLM).

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4653 A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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4652 Multi-Objective Fuzzy Model in Optimal Sitingand Sizing of DG for Loss Reduction

Authors: H. Shayeghi, B. Mohamadi

Abstract:

This paper presents a possibilistic (fuzzy) model in optimal siting and sizing of Distributed Generation (DG) for loss reduction and improve voltage profile in power distribution system. Multi-objective problem is developed in two phases. In the first one, the set of non-dominated planning solutions is obtained (with respect to the objective functions of fuzzy economic cost, and exposure) using genetic algorithm. In the second phase, one solution of the set of non-dominated solutions is selected as optimal solution, using a suitable max-min approach. This method can be determined operation-mode (PV or PQ) of DG. Because of considering load uncertainty in this paper, it can be obtained realistic results. The whole process of this method has been implemented in the MATLAB7 environment with technical and economic consideration for loss reduction and voltage profile improvement. Through numerical example the validity of the proposed method is verified.

Keywords: Fuzzy Power Flow, DG siting and sizing, LoadUncertainty, Multi-objective Possibilistic Model.

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4651 Microkinetic Modelling of NO Reduction on Pt Catalysts

Authors: Vishnu S. Prasad, Preeti Aghalayam

Abstract:

The major harmful automobile exhausts are nitric oxide (NO) and unburned hydrocarbon (HC). Reduction of NO using unburned fuel HC as a reductant is the technique used in hydrocarbon-selective catalytic reduction (HC-SCR). In this work, we study the microkinetic modelling of NO reduction using propene as a reductant on Pt catalysts. The selectivity of NO reduction to N2O is detected in some ranges of operating conditions, whereas the effect of inlet O2% causes a number of changes in the feasible regimes of operation.

Keywords: Microkinetic modelling, NOx, Pt on alumina catalysts, selective catalytic reduction.

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4650 Methodology for Obtaining Static Alignment Model

Authors: Lely A. Luengas, Pedro R. Vizcaya, Giovanni Sánchez

Abstract:

In this paper, a methodology is presented to obtain the Static Alignment Model for any transtibial amputee person. The proposed methodology starts from experimental data collected on the Hospital Militar Central, Bogotá, Colombia. The effects of transtibial prosthesis malalignment on amputees were measured in terms of joint angles, center of pressure (COP) and weight distribution. Some statistical tools are used to obtain the model parameters. Mathematical predictive models of prosthetic alignment were created. The proposed models are validated in amputees and finding promising results for the prosthesis Static Alignment. Static alignment process is unique to each subject; nevertheless the proposed methodology can be used in each transtibial amputee.

Keywords: Information theory, prediction model, prosthetic alignment, transtibial prosthesis.

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4649 An Evaluation of Sag Detection Techniques for Fast Solid-State Electronic Transferring to Alternate Electrical Energy Sources

Authors: M. N. Moschakis, I. G. Andritsos, V. V. Dafopoulos, J. M. Prousalidis, E. S. Karapidakis

Abstract:

This paper deals with the evaluation of different detection strategies used in power electronic devices as a critical element for an effective mitigation of voltage disturbances. The effectiveness of those detection schemes in the mitigation of disturbances such as voltage sags by a Solid-State Transfer Switch is evaluated through simulations. All critical parameters affecting their performance is analytically described and presented. Moreover, the effect of fast detection of sags on the overall performance of STS is analyzed and investigated.

Keywords: Faults (short-circuits), industrial engineering, power electronics, power quality, static transfer switch, voltage sags (or dips).

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4648 Study of Shaft Voltage on Short Circuit Alternator with Static Frequency Converter

Authors: Arun Kumar Datta, Manisha Dubey, Shailendra Jain

Abstract:

Electric machines are driven nowadays by static system popularly known as soft starter. This paper describes a thyristor based static frequency converter (SFC) to run a large synchronous machine installed at a short circuit test laboratory. Normally a synchronous machine requires prime mover or some other driving mechanism to run. This machine doesn’t need a prime mover as it operates in dual mode. In the beginning SFC starts this machine as a motor to achieve the full speed. Thereafter whenever required it can be converted to generator mode. This paper begins with the various starting methodology of synchronous machine. Detailed of SFC with different operational modes have been analyzed. Shaft voltage is a very common phenomenon for the machines with static drives. Various causes of shaft voltages in perspective with this machine are the main attraction of this paper.

Keywords: Capacitive coupling, electric discharge machining, inductive coupling, Shaft voltage, static frequency converter.

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4647 Computation of Global Voltage Stability Margin in a Practical Power Network Incorporating FACTS in the OPF Frame Work

Authors: P. Nagendra, S. Halder nee Dey, S. Paul, T. Datta

Abstract:

This paper presents a methodology to assess the voltage stability status combined with optimal power flow technique using an instantaneous two-bus equivalent model of power system incorporating static var compensator (SVC) and thyristor controlled series compensator (TCSC) controllers. There by, a generalized global voltage stability indicator being developed has been applied to a robust practical Indian Eastern Grid 203-bus system. Simulation results have proved that the proposed methodology is promising to assess voltage stability of any power system at any operating point in global scenario. Voltage stability augmentation with the application of SVC at the weakest bus and TCSC at critical line connected to the weakest bus is compared with the system having no compensation. In the proposed network equivalent model the generators have been modeled more accurately considering economic criteria.

Keywords: Equivalent two-bus model, global voltage security indicator, optimal power flow, SVC, TCSC.

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4646 Coordinated Design of PSS and STATCOM for Power System Stability Improvement Using Bacteria Foraging Algorithm

Authors: Kyaw Myo Lin, Wunna Swe, Pyone Lai Swe

Abstract:

This paper presents the coordinated controller design of static synchronous compensator (STATCOM) and power system stabilizers (PSSs) for power system stability improvement. Coordinated design problem of STATCOM-based controller with multiple PSSs is formulated as an optimization problem and optimal controller parameters are obtained using bacteria foraging optimization algorithm. By minimizing the proposed objective function, in which the speed deviations between generators are involved; stability performance of the system is improved. The nonlinear simulation results show that coordinated design of STATCOM-based controller and PSSs improve greatly the system damping oscillations and consequently stability improvement.

Keywords: Bacteria Foraging, Coordinated Design, Power System Stability, PSSs, STATCOM.

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4645 Aliveness Detection of Fingerprints using Multiple Static Features

Authors: Heeseung Choi, Raechoong Kang, Kyungtaek Choi, Jaihie Kim

Abstract:

Fake finger submission attack is a major problem in fingerprint recognition systems. In this paper, we introduce an aliveness detection method based on multiple static features, which derived from a single fingerprint image. The static features are comprised of individual pore spacing, residual noise and several first order statistics. Specifically, correlation filter is adopted to address individual pore spacing. The multiple static features are useful to reflect the physiological and statistical characteristics of live and fake fingerprint. The classification can be made by calculating the liveness scores from each feature and fusing the scores through a classifier. In our dataset, we compare nine classifiers and the best classification rate at 85% is attained by using a Reduced Multivariate Polynomial classifier. Our approach is faster and more convenient for aliveness check for field applications.

Keywords: Aliveness detection, Fingerprint recognition, individual pore spacing, multiple static features, residual noise.

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4644 Incorporation of SVS CBVLC Supplementary Controller for Damping SSR in Power System

Authors: Narendra Kumar, Sanjiv Kumar

Abstract:

Static VAR System (SVS) is a kind of FACTS device which is used in power system primarily for the purpose of voltage and reactive power control. In this paper presents a systematic approach for designing SVS supplementary controller, which is used to improve the damping of power system oscillation. The combined bus voltage and line current (CBVLC) supplementary controller has been developed and incorporated in the SVS control system located at the middle of the series compensated long transmission line. Damping of torsional stresses due to subsynchronous resonance resulting from series capacitive compensation using CBVLC is investigated in this paper. Simulation results are carried out with MATLAB/Simulink on the IEEE first benchmark model (FBM). The simulation results show that the oscillations are satisfactorily damped out by the SVS supplementary controller. Time domain simulation is performed on power system and the results demonstrate the effectiveness of the proposed controller.

Keywords: Bus voltage and line current (BVLC), series compensation, sub synchronous resonance (SSR), supplementary controller, eigenvalue investigation.

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4643 Electricity Power Planning: the Role of Wind Energy

Authors: Paula Ferreira, Madalena Araújo, M.E.J. O’Kelly

Abstract:

Combining energy efficiency with renewable energy sources constitutes a key strategy for a sustainable future. The wind power sector stands out as a fundamental element for the achievement of the European renewable objectives and Portugal is no exception to the increase of the wind energy for the electricity generation. This work proposes an optimization model for the long range electricity power planning in a system similar to the Portuguese one, where the expected impacts of the increasing installed wind power on the operating performance of thermal power plants are taken into account. The main results indicate that the increasing penetration of wind power in the electricity system will have significant effects on the combined cycle gas power plants operation and on the theoretically expected cost reduction and environmental gains. This research demonstrated the need to address the impact that energy sources with variable output may have, not only on the short-term operational planning, but especially on the medium to long range planning activities, in order to meet the strategic objectives for the energy sector.

Keywords: Wind power, electricity planning model, cost, emissions.

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4642 Design and Analysis of Low-Power, High Speed and Area Efficient 2-Bit Digital Magnitude Comparator in 90nm CMOS Technology Using Gate Diffusion Input

Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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