Search results for: Chip Micro-Hardness

Authors: Boram Kim, Shigeyasu Uno, Kazuo Nakazato

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Continuous-time delta-sigma analog digital converter (ADC) for radio frequency identification (RFID) complementary metal oxide semiconductor (CMOS) biosensor has been reported. This delta-sigma ADC is suitable for digital conversion of biosensor signal because of small process variation, and variable input range. As the input range of continuous-time switched current delta-sigma ADC (Dynamic range : 50 dB) can be limited by using current reference, amplification of biosensor signal is unnecessary. The input range is switched to wide input range mode or narrow input range mode by command of current reference. When the narrow input range mode, the input range becomes ± 0.8 V. The measured power consumption is 5 mW and chip area is 0.31 mm^2 using 1.2 um standard CMOS process. Additionally, automatic input range detecting system is proposed because of RFID biosensor applications.

Keywords: continuous time, delta sigma, A/D converter, RFID, biosensor, CMOS

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Authors: Robert Cep, Lenka Ocenasova, Jana Novakova, Karel Kouril, Jan Valicek, Branimir Barisic

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This paper deals with the problem of thermal and mechanical shocks, which rising during operation, mostly at interrupted cut. Here will be solved their impact on the cutting edge tool life, the impact of coating technology on resistance to shocks and experimental determination of tool life in heating flame. Resistance of removable cutting edges against thermal and mechanical shock is an important indicator of quality as well as its abrasion resistance. Breach of the edge or its crumble may occur due to cyclic loading. We can observe it not only during the interrupted cutting (milling, turning areas abandoned hole or slot), but also in continuous cutting. This is due to the volatility of cutting force on cutting. Frequency of the volatility in this case depends on the type of rising chips (chip size element). For difficult-to-machine materials such as austenitic steel particularly happened at higher cutting speeds for the localization of plastic deformation in the shear plane and for the inception of separate elements substantially continuous chips. This leads to variations of cutting forces substantially greater than for other types of steel.

Keywords: Cutting Tool Life, Heating, Mechanical Shocks, Thermal Shocks

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Authors: Preetam Kumar

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The number of users supported in a DS-CDMA cellular system is typically less than spreading factor (N), and the system is said to be underloaded. Overloading is a technique to accommodate more number of users than the spreading factor N. In O/O overloading scheme, the first set is assigned to the N synchronous users and the second set is assigned to the additional synchronous users. An iterative multistage soft decision interference cancellation (SDIC) receiver is used to remove high level of interference between the two sets. Performance is evaluated in terms of the maximum number acceptable users so that the system performance is degraded slightly compared to the single user performance at a specified BER. In this paper, the capacity of CDMA based O/O overloading scheme is evaluated with SDIC receiver. It is observed that O/O scheme using orthogonal Gold codes provides 25% channel overloading (N=64) for synchronous DS-CDMA system on an AWGN channel in the uplink at a BER of 1e-5.For a Rayleigh faded channel, the critical capacity is 40% at a BER of 5e-5 assuming synchronous users. But in practical systems, perfect chip timing is very difficult to maintain in the uplink.. We have shown that the overloading performance reduces to 11% for a timing synchronization error of 0.02Tc for a BER of 1e-5.

Keywords: DS-CDMA, Interference Cancellation, MultiuserDetection, Orthogonal codes, Overloading.

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Authors: R. Ziaie Moayed, M. Hamidzadeh

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The use of waste rubber chips not only can be of great importance in terms of the environment, but also can be used to increase the shear strength of soils. The purpose of this study was to evaluate the variation of the internal friction angle of liquefiable sandy soil using waste rubber chips. For this purpose, the geotechnical properties of unmodified and modified soil samples by waste lining rubber chips have been evaluated and analyzed by performing the triaxial consolidated drained test. In order to prepare the laboratory specimens, the sandy soil in part of Rudsar shores in Gilan province, north of Iran with high liquefaction potential has been replaced by two percent of waste rubber chips. Samples have been compressed until reaching the two levels of density of 15.5 and 16.7 kN/m³. Also, in order to find the optimal length of chips in sandy soil, the rectangular rubber chips with the widths of 0.5 and 1 cm and the lengths of 0.5, 1, and 2 cm were used. The results showed that the addition of rubber chips to liquefiable sandy soil greatly increases the shear resistance of these soils. Also, it can be seen that decreasing the width and increasing the length-to-width ratio of rubber chips has a direct impact on the shear strength of the modified soil samples with rubber chips.

Keywords: Improvement, shear strength, internal friction angle, sandy soil, rubber chip.

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Authors: Suresh Alapati, Sreehari Rao Patri, K. S. R. Krishna Prasad

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Anultra-low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gainenhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 )A. An undershot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 )s for the output voltage undershooting case. The load regulation is of 2.77 )V/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: Capacitor-less LDO, frequency compensation, Transient response, latch, self-biased differential amplifier.

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Authors: M. Aqeel Iqbal

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Fully customized hardware based technology provides high performance and low power consumption by specializing the tasks in hardware but lacks design flexibility since any kind of changes require re-design and re-fabrication. Software based solutions operate with software instructions due to which a great flexibility is achieved from the easy development and maintenance of the software code. But this execution of instructions introduces a high overhead in performance and area consumption. In past few decades the reconfigurable computing domain has been introduced which overcomes the traditional trades-off between flexibility and performance and is able to achieve high performance while maintaining a good flexibility. The dramatic gains in terms of chip performance and design flexibility achieved through the reconfigurable computing systems are greatly dependent on the design of their computational units being integrated with reconfigurable logic resources. The computational unit of any reconfigurable system plays vital role in defining its strength. In this research paper an RFU based computational unit design has been presented using the tightly coupled, multi-threaded reconfigurable cores. The proposed design has been simulated for VLIW based architectures and a high gain in performance has been observed as compared to the conventional computing systems.

Keywords: Configuration Stream, Configuration overhead, Configuration Controller, Reconfigurable devices.

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

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While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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Authors: P. R. Prabhu, S. M. Kulkarni, S. S. Sharma, K. Jagannath, Achutha Kini U.

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In the present study, response surface methodology has been used to optimize turn-assisted deep cold rolling process of AISI 4140 steel. A regression model is developed to predict surface hardness and surface roughness using response surface methodology and central composite design. In the development of predictive model, deep cold rolling force, ball diameter, initial roughness of the workpiece, and number of tool passes are considered as model variables. The rolling force and the ball diameter are the significant factors on the surface hardness and ball diameter and numbers of tool passes are found to be significant for surface roughness. The predicted surface hardness and surface roughness values and the subsequent verification experiments under the optimal operating conditions confirmed the validity of the predicted model. The absolute average error between the experimental and predicted values at the optimal combination of parameter settings for surface hardness and surface roughness is calculated as 0.16% and 1.58% respectively. Using the optimal processing parameters, the surface hardness is improved from 225 to 306 HV, which resulted in an increase in the near surface hardness by about 36% and the surface roughness is improved from 4.84µm to 0.252 µm, which resulted in decrease in the surface roughness by about 95%. The depth of compression is found to be more than 300µm from the microstructure analysis and this is in correlation with the results obtained from the microhardness measurements. Taylor hobson talysurf tester, micro vickers hardness tester, optical microscopy and X-ray diffractometer are used to characterize the modified surface layer. 

Keywords: Surface hardness, response surface methodology, microstructure, central composite design, deep cold rolling, surface roughness.

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Authors: Sadi Vural, Hiromi Tomii, Hironori Yamauchi

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With the advent of digital cinema and digital broadcasting, copyright protection of video data has been one of the most important issues. We present a novel method of watermarking for video image data based on the hardware and digital wavelet transform techniques and name it as “traceable watermarking" because the watermarked data is constructed before the transmission process and traced after it has been received by an authorized user. In our method, we embed the watermark to the lowest part of each image frame in decoded video by using a hardware LSI. Digital Cinema is an important application for traceable watermarking since digital cinema system makes use of watermarking technology during content encoding, encryption, transmission, decoding and all the intermediate process to be done in digital cinema systems. The watermark is embedded into the randomly selected movie frames using hash functions. Embedded watermark information can be extracted from the decoded video data. For that, there is no need to access original movie data. Our experimental results show that proposed traceable watermarking method for digital cinema system is much better than the convenient watermarking techniques in terms of robustness, image quality, speed, simplicity and robust structure.

Keywords: Decoder, Digital content, JPEG2000 Frame, System-On-Chip, traceable watermark, Hash Function, CRC-32.

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Authors: K.Kadirgama, M.M.Noor, K.A. Abou-El-Hossein, H.H.Habeeb, M.M. Rahman, B.Mohamad, R.A. Bakar

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Cutting fluids, usually in the form of a liquid, are applied to the chip formation zone in order to improve the cutting conditions. Cutting fluid can be expensive and represents a biological and environmental hazard that requires proper recycling and disposal, thus adding to the cost of the machining operation. For these reasons dry cutting or dry machining has become an increasingly important approach; in dry machining no coolant or lubricant is used. This paper discussed the effect of the dry cutting on cutting force and tool life when machining aerospace materials (Haynes 242) with using two different coated carbide cutting tools (TiAlN and TiN/MT-TiCN/TiN). Response surface method (RSM) was used to minimize the number of experiments. ParTiAlN Swarm Optimisation (PSO) models were developed to optimize the machining parameters (cutting speed, federate and axial depth) and obtain the optimum cutting force and tool life. It observed that carbide cutting tool coated with TiAlN performed better in dry cutting compared with TiN/MT-TiCN/TiN. On other hand, TiAlN performed more superior with using of 100 % water soluble coolant. Due to the high temperature produced by aerospace materials, the cutting tool still required lubricant to sustain the heat transfer from the workpiece.

Keywords: Dry cutting, partial swarm optimisation, response surface method, tool life

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Authors: Hsin-Hung Chang, Jin-Lung Guan, Ming-Ta Yang

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This paper presents a compact thermoelectric power generator system based on temperature difference across the element. The system can transfer the burning heat energy to electric energy directly. The proposed system has a thermoelectric generator and a power control box. In the generator, there are 4 thermoelectric modules (TEMs), each of which uses 2 thermoelectric chips (TEs) and 2 cold sinks, 1 thermal absorber, and 1 thermal conduction flat board. In the power control box, there are 1 storing energy device, 1 converter, and 1 inverter. The total net generating power is about 11W. This system uses commercial portable gas stoves or burns timber or the coal as the heat source, which is easily obtained. It adopts solid-state thermoelectric chips as heat inverter parts. The system has the advantages of being light-weight, quite, and mobile, requiring no maintenance, and havng easily-supplied heat source. The system can be used a as long as burning is allowed. This system works well for highly-mobilized outdoors situations by providing a power for illumination, entertainment equipment or the wireless equipment at refuge. Under heavy storms such as typhoon, when the solar panels become ineffective and the wind-powered machines malfunction, the thermoelectric power generator can continue providing the vital power.

Keywords: Thermoelectric chip, seekback effect, thermo electric power generator.

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Authors: Tim Dunne, Weicheng Li, Chris Cheng, Qi Peng

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Deeper petroleum reservoirs are more challenging to exploit due to the high hardness and abrasive characteristics of the formations. A cutting structure that consists of particulate diamond impregnated in a supporting matrix is found to be effective. Diamond impregnated bits are favored in these applications due to the higher thermal stability of the matrix material. The diamond particles scour or abrade away concentric grooves while the rock formation adjacent to the grooves is fractured and removed. The matrix material supporting the diamond will wear away, leaving the superficial dull diamonds to fall out. The matrix material wear will expose other embedded intact sharp diamonds to continue the operation. Minimizing the erosion effect on the matrix is an important design consideration, as the life of the bit can be extended by preventing early diamond pull-out. A careful balancing of the key parameters, such as diamond concentration, tungsten carbide and metal binder must be considered during development. Described herein is the design of experiment for developing and lab testing 8 unique samples. ASTM B611 wear testing was performed to benchmark the material performance against baseline products, with further scanning electron microscopy and microhardness evaluations. The recipe S5 with diamond 25/35 mesh size, narrow size distribution, high concentration blended with fine tungsten carbide and Co-Cu-Fe-P metal binder has the best performance, which shows 19% improvement in the ASTM B611 wear test compared with the reference material. In the field trial, the rate of penetration (ROP) is measured as 15 m/h, compared to 9.5, 7.8, and 6.8 m/h of other commercial impregnated bits in the same formation. A second round of optimizing recipe S5 for a higher wear resistance is further reported.

Keywords: Diamond containing material, grit hot press insert, impregnated diamond, insert, rate of penetration, ultrahard formation.

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Authors: A. Baith Mohamed, Ayman Abdel-Hamid, Kareem Youssri Mohamed

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Current proposals for E-passport or ID-Card is similar to a regular passport with the addition of tiny contactless integrated circuit (computer chip) inserted in the back cover, which will act as a secure storage device of the same data visually displayed on the photo page of the passport. In addition, it will include a digital photograph that will enable biometric comparison, through the use of facial recognition technology at international borders. Moreover, the e-passport will have a new interface, incorporating additional antifraud and security features. However, its problems are reliability, security and privacy. Privacy is a serious issue since there is no encryption between the readers and the E-passport. However, security issues such as authentication, data protection and control techniques cannot be embedded in one process. In this paper, design and prototype implementation of an improved E-passport reader is presented. The passport holder is authenticated online by using GSM network. The GSM network is the main interface between identification center and the e-passport reader. The communication data is protected between server and e-passport reader by using AES to encrypt data for protection will transferring through GSM network. Performance measurements indicate a 19% improvement in encryption cycles versus previously reported results.

Keywords: RFID "Radio Frequency Identification", EPC"Electronic Product Code", ICAO "International Civil Aviation Organization", IFF "Identify Friend or Foe"

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Authors: Shahrinaz Ismail, Roslina Abdul Latif

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Social media has led to paradigm shifts in ways people work and do business, interact and socialize, learn and obtain knowledge. So much so that social media has established itself as an important spatial extension of this nation-s historicity and challenges. Regardless of the enabling reputation and recommendation features through social networks embedded in the social media system, the overflow of broadcasted and publicized media contents turns the table around from engendering trust to doubting the trust system. When the trust is at doubt, the effects include deactivation of accounts and creation of multiple profiles, which lead to the overflow of 'ghost' contents (i.e. “the abundance of abandoned ships"). In most literature, the study of trust can be related to culture; hence the difference between Western-s “openness" and Eastern-s “blue-chip" concepts in networking and relationships. From a survey on issues and challenges among Malaysian social media users, 'authenticity' emerges as one of the main factors that causes and is caused by other factors. The other issue that has surfaced is credibility either in terms of message/content and source. Another is the quality of the knowledge that is shared. This paper explores the terrains of this critical space which in recent years has been dominated increasingly by, arguably, social networks embedded in the social media system, the overflow of broadcasted and publicized media content.

Keywords: Authenticity, credibility, knowledge quality and social media.

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Authors: Jae Chul Cha, Sandeep K. Gupta

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The demand for higher performance graphics continues to grow because of the incessant desire towards realism. And, rapid advances in fabrication technology have enabled us to build several processor cores on a single die. Hence, it is important to develop single chip parallel architectures for such data-intensive applications. In this paper, we propose an efficient PIM architectures tailored for computer graphics which requires a large number of memory accesses. We then address the two important tasks necessary for maximally exploiting the parallelism provided by the architecture, namely, partitioning and placement of graphic data, which affect respectively load balances and communication costs. Under the constraints of uniform partitioning, we develop approaches for optimal partitioning and placement, which significantly reduce search space. We also present heuristics for identifying near-optimal placement, since the search space for placement is impractically large despite our optimization. We then demonstrate the effectiveness of our partitioning and placement approaches via analysis of example scenes; simulation results show considerable search space reductions, and our heuristics for placement performs close to optimal – the average ratio of communication overheads between our heuristics and the optimal was 1.05. Our uniform partitioning showed average load-balance ratio of 1.47 for geometry processing and 1.44 for rasterization, which is reasonable.

Keywords: Data Partitioning and Placement, Graphics, PIM, Search Space Reduction.

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Authors: Hamed Rezazadeh, Majid Ebrahimzadeh, Mohammad Reza Zeidi Yam

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Anodizing is an electrochemical process that converts the metal surface into a decorative, durable, corrosion-resistant, anodic oxide finish. Aluminum is ideally suited to anodizing, although other nonferrous metals, such as magnesium and titanium, also can be anodized. The anodic oxide structure originates from the aluminum substrate and is composed entirely of aluminum oxide. This aluminum oxide is not applied to the surface like paint or plating, but is fully integrated with the underlying aluminum substrate, so cannot chip or peel. It has a highly ordered, porous structure that allows for secondary processes such as coloring and sealing. In this experimental paper, we focus on a reliable method for fabricating nanoporous alumina with high regularity. Starting from study of nanostructure materials synthesize methods. After that, porous alumina fabricate in the laboratory by anodization of aluminum oxide. Hard anodization processes are employed to fabricate the nanoporous alumina using 0.3M oxalic acid and 90, 120 and 140 anodized voltages. The nanoporous templates were characterized by SEM and FFT. The nanoporous templates using 140 voltages have high ordered. The pore formation, influence of the experimental conditions on the pore formation, the structural characteristics of the pore and the oxide chemical reactions involved in the pore growth are discuss.

Keywords: Alumina, Nanoporous Template, Anodization

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Authors: M. N. Islam, B. Boswell, Y. R. Ginting

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The influence of canned cycles and cutting parameters on hole quality in cryogenic drilling has been investigated experimentally and analytically. A three-level, three-parameter experiment was conducted by using the design-of-experiment methodology. The three levels of independent input parameters were the following: for canned cycles—a chip-breaking canned cycle (G73), a spot drilling canned cycle (G81), and a deep hole canned cycle (G83); for feed rates—0.2, 0.3, and 0.4 mm/rev; and for cutting speeds—60, 75, and 100 m/min. The selected work and tool materials were aluminum 6061-6T and high-speed steel (HSS), respectively. For cryogenic cooling, liquid nitrogen (LN2) was used and was applied externally. The measured output parameters were the three widely used quality characteristics of drilled holes—diameter error, circularity, and surface roughness. Pareto ANOVA was applied for analyzing the results. The findings revealed that the canned cycle has a significant effect on diameter error (contribution ratio 44.09%) and small effects on circularity and surface finish (contribution ratio 7.25% and 6.60%, respectively). The best results for the dimensional accuracy and surface roughness were achieved by G81. G73 produced the best circularity results; however, for dimensional accuracy, it was the worst level.

Keywords: Circularity, diameter error, drilling canned cycle, Pareto ANOVA, surface roughness.

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Authors: A. Muthuramalingam, S. Himavathi, E. Srinivasan

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.Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions using FPGA. Implementation method with resource/speed tradeoff is proposed to handle signed decimal numbers. The VHDL coding developed is tested using Xilinx XC V50hq240 Chip. To improve the speed of operation a lookup table method is used. The problems involved in using a lookup table (LUT) for a nonlinear function is discussed. The percentage saving in resource and the improvement in speed with an LUT for a neuron is reported. An attempt is also made to derive a generalized formula for a multi-input neuron that facilitates to estimate approximately the total resource requirement and speed achievable for a given multilayer neural network. This facilitates the designer to choose the FPGA capacity for a given application. Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented

Keywords: FPGA implementation, multi-input neuron, neural network, nn based space vector modulator.

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Authors: Hanaa T. El-Madany, Faten H. Fahmy, Ninet M. A. El-Rahman, Hassen T. Dorrah

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Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.

Keywords: Spacecraft, neural network, FPGA, VHDL.

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Authors: D. Geringswald, B. Hintze

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The miniaturization of circuits is advancing. During chip manufacturing, structures are filled for example by metal organic chemical vapor deposition (MOCVD). Since this process reaches its limits in case of very high aspect ratios, the use of alternatives such as the atomic layer deposition (ALD) is possible, requiring the extension of existing coating systems. However, it is an unsolved question to what extent MOCVD can achieve results similar as an ALD process. In this context, this work addresses the characterization of a metal organic vapor deposition of titanium nitride. Based on the current state of the art, the film properties coating thickness, sheet resistance, resistivity, stress and chemical composition are considered. The used setting parameters are temperature, plasma gas ratio, plasma power, plasma treatment time, deposition time, deposition pressure, number of cycles and TDMAT flow. The derived process instructions for unstructured wafers and inside a structure with high aspect ratio include lowering the process temperature and increasing the number of cycles, the deposition and the plasma treatment time as well as the plasma gas ratio of hydrogen to nitrogen (H₂:N₂). In contrast to the current process configuration, the deposited titanium nitride (TiN) layer is more uniform inside the entire test structure. Consequently, this paper provides approaches to employ the MOCVD for structures with increasing aspect ratios.

Keywords: ALD, high aspect ratio, PE-MOCVD, TiN.

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Authors: Ameni Mokni , Hatem Mhiri , Georges Le Palec , Philippe Bournot

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In mechanical and environmental engineering, mixed convection is a frequently encountered thermal fluid phenomenon which exists in atmospheric environment, urban canopy flows, ocean currents, gas turbines, heat exchangers, and computer chip cooling systems etc... . This paper deals with a numerical investigation of mixed convection in a vertical heated channel. This flow results from the mixing of the up-going fluid along walls of the channel with the one issued from a flat nozzle located in its entry section. The fluiddynamic and heat-transfer characteristics of vented vertical channels are investigated for constant heat-flux boundary conditions, a Rayleigh number equal to 2.57 1010, for two jet Reynolds number Re=3 103 and 2104 and the aspect ratio in the 8-20 range. The system of governing equations is solved with a finite volumes method and an implicit scheme. The obtained results show that the turbulence and the jet-wall interaction activate the heat transfer, as does the drive of ambient air by the jet. For low Reynolds number Re=3 103, the increase of the aspect Ratio enhances the heat transfer of about 3%, however; for Re=2 104, the heat transfer enhancement is of about 12%. The numerical velocity, pressure and temperature fields are post-processed to compute the quantities of engineering interest such as the induced mass flow rate, and average Nusselt number, in terms of Rayleigh, Reynolds numbers and dimensionless geometric parameters are presented.

Keywords: Aspect Ratio, Channel, Jet, Mixed convection

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Authors: B. Arzhanov, A. Correia, P. Delgado, J. Meireles

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Due to the higher power loss levels in electronic components, the thermal design of PCBs (Printed Circuit Boards) of an assembled device becomes one of the most important quality factors in electronics. Nonetheless, some of leading causes of the microelectronic component failures are due to higher temperatures, the leakages or thermal-mechanical stress, which is a concern, is the reliability of microelectronic packages. This article presents an experimental approach to measure the junction temperature of exposed pad packages. The implemented solution is in a prototype phase, using a temperature-sensitive parameter (TSP) to measure temperature directly on the die, validating the numeric results provided by the Mechanical APDL (Ansys Parametric Design Language) under same conditions. The physical device-under-test is composed by a Thermal Test Chip (TTC-1002) and assembly in a QFN cavity, soldered to a test-board according to JEDEC Standards. Monitoring the voltage drop across a forward-biased diode, is an indirectly method but accurate to obtain the junction temperature of QFN component with an applied power range between 0,3W to 1.5W. The temperature distributions on the PCB test-board and QFN cavity surface were monitored by an infra-red thermal camera (Goby-384) controlled and images processed by the Xeneth software. The article provides a set-up to monitorize in real-time the junction temperature of ICs, namely devices with the exposed pad package (i.e. QFN). Presenting the PCB layout parameters that the designer should use to improve thermal performance, and evaluate the impact of voids in solder interface in the device junction temperature.

Keywords: Quad Flat No-Lead packages, exposed pads, junction temperature, thermal management, measurements.

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Authors: F. A. Gdhaidh, K. Hussain, H. S. Qi

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A numerical study of natural convection heat transfer in water filled cavity has been examined in 3-Dfor single phase liquid cooling system by using an array of parallel plate fins mounted to one wall of a cavity. The heat generated by a heat source represents a computer CPU with dimensions of 37.5∗37.5mm mounted on substrate. A cold plate is used as a heat sink installed on the opposite vertical end of the enclosure. The air flow inside the computer case is created by an exhaust fan. A turbulent air flow is assumed and k-ε model is applied. The fins are installed on the substrate to enhance the heat transfer. The applied power energy range used is between 15 - 40W. In order to determine the thermal behaviour of the cooling system, the effect of the heat input and the number of the parallel plate fins are investigated. The results illustrate that as the fin number increases the maximum heat source temperature decreases. However, when the fin number increases to critical value the temperature start to increase due to the fins are too closely spaced and that cause the obstruction of water flow. The introduction of parallel plate fins reduces the maximum heat source temperature by 10% compared to the case without fins. The cooling system maintains the maximum chip temperature at 64.68°C when the heat input was at 40W that is much lower than the recommended computer chips limit temperature of no more than 85°C and hence the performance of the CPU is enhanced.

Keywords: Chips limit temperature, closed enclosure, natural convection, parallel plate, single phase liquid.

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Authors: A. Almaneea, N. Kapur, J. L. Summers, H. M. Thompson

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Meeting the growth in demand for digital services such as social media, telecommunications, and business and cloud services requires large scale data centres, which has led to an increase in their end use energy demand. Generally, over 30% of data centre power is consumed by the necessary cooling overhead. Thus energy can be reduced by improving the cooling efficiency. Air and liquid can both be used as cooling media for the data centre. Traditional data centre cooling systems use air, however liquid is recognised as a promising method that can handle the more densely packed data centres. Liquid cooling can be classified into three methods; rack heat exchanger, on-chip heat exchanger and full immersion of the microelectronics. This study quantifies the improvements of heat transfer specifically for the case of immersed microelectronics by varying the CPU and heat sink location. Immersion of the server is achieved by filling the gap between the microelectronics and a water jacket with a dielectric liquid which convects the heat from the CPU to the water jacket on the opposite side. Heat transfer is governed by two physical mechanisms, which is natural convection for the fixed enclosure filled with dielectric liquid and forced convection for the water that is pumped through the water jacket. The model in this study is validated with published numerical and experimental work and shows good agreement with previous work. The results show that the heat transfer performance and Nusselt number (Nu) is improved by 89% by placing the CPU and heat sink on the bottom of the microelectronics enclosure.

Keywords: CPU location, data centre cooling, heat sink in enclosures, Immersed microelectronics, turbulent natural convection in enclosures.

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Authors: Satish Kumar, Arun Kumar Gupta, Pankaj Chandna

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In the modern manufacturing systems, the use of thermal cutting techniques using oxyfuel, plasma and laser have become indispensable for the shape forming of high quality complex components; however, the conventional chip removal production techniques still have its widespread space in the manufacturing industry. Both these types of machining operations require the positioning of end effector tool at the edge where the cutting process commences. This repositioning of the cutting tool in every machining operation is repeated several times and is termed as non-productive time or airtime motion. Minimization of this non-productive machining time plays an important role in mass production with high speed machining. As, the tool moves from one region to the other by rapid movement and visits a meticulous region once in the whole operation, hence the non-productive time can be minimized by synchronizing the tool movements. In this work, this problem is being formulated as a general travelling salesman problem (TSP) and a genetic algorithm approach has been applied to solve the same. For improving the efficiency of the algorithm, the GA has been hybridized with a noble special heuristic and simulating annealing (SA). In the present work a novel heuristic in the combination of GA has been developed for synchronization of toolpath movements during repositioning of the tool. A comparative analysis of new Meta heuristic techniques with simple genetic algorithm has been performed. The proposed metaheuristic approach shows better performance than simple genetic algorithm for minimization of nonproductive toolpath length. Also, the results obtained with the help of hybrid simulated annealing genetic algorithm (HSAGA) are also found better than the results using simple genetic algorithm only.

Keywords: Non-productive time, Airtime, 2.5 D milling, Laser cutting, Metaheuristic, Genetic Algorithm, Simulated Annealing.

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Authors: Ruth Lorivi, Jianzheng Li, John J. Ambuchi, Kaiwen Deng

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Nitrogen removal from wastewater is accomplished by nitrification and denitrification processes. Successful denitrification requires carbon, therefore, if placed after biochemical oxygen demand (BOD) and nitrification process, a carbon source has to be re-introduced into the water. To avoid adding a carbon source, denitrification is usually placed before BOD and nitrification processes. This process however involves recycling the nitrified effluent. In this study wood chips were used as internal carbon source which enabled placement of denitrification after BOD and nitrification process without effluent recycling. To investigate the efficiency of a wood packed aerobic-anaerobic baffled reactor on carbon and nutrients removal from domestic wastewater, a three compartment baffled reactor was presented. Each of the three compartments was packed with 329 g wood chips 1x1cm acting as an internal carbon source for denitrification. The proposed mode of operation was aerobic-anoxic-anaerobic (OAA) with no effluent recycling. The operating temperature, hydraulic retention time (HRT), dissolved oxygen (DO) and pH were 24 ± 2 ℃, 24 h, less than 4 mg/L and 7 ± 1 respectively. The removal efficiencies of chemical oxygen demand (COD), ammonia nitrogen (NH₄⁺-N) and total nitrogen (TN) attained was 99, 87 and 83% respectively. TN removal rate was limited by nitrification as 97% of ammonia converted into nitrate and nitrite was denitrified. These results show that application of wood chips in wastewater treatment processes is an efficient internal carbon source. 

Keywords: Aerobic-anaerobic baffled reactor, denitrification, nitrification, wood chip.

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Authors: Gaurav D. Sonawane, Vikas G. Sargade

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The present investigation is a study of the effect of advanced Physical Vapor Deposition (PVD) coatings on cutting temperature residual stresses and surface roughness during Duplex Stainless Steel (DSS) 2205 turning. Austenite stabilizers like nickel, manganese, and molybdenum reduced the cost of DSS. Surface Integrity (SI) plays an important role in determining corrosion resistance and fatigue life. Resistance to various types of corrosion makes DSS suitable for applications with critical environments like Heat exchangers, Desalination plants, Seawater pipes and Marine components. However, lower thermal conductivity, poor chip control and non-uniform tool wear make DSS very difficult to machine. Cemented carbide tools (M grade) were used to turn DSS in a dry environment. AlTiN and AlTiCrN coatings were deposited using advanced PVD High Pulse Impulse Magnetron Sputtering (HiPIMS) technique. Experiments were conducted with cutting speed of 100 m/min, 140 m/min and 180 m/min. A constant feed and depth of cut of 0.18 mm/rev and 0.8 mm were used, respectively. AlTiCrN coated tools followed by AlTiN coated tools outperformed uncoated tools due to properties like lower thermal conductivity, higher adhesion strength and hardness. Residual stresses were found to be compressive for all the tools used for dry turning, increasing the fatigue life of the machined component. Higher cutting temperatures were observed for coated tools due to its lower thermal conductivity, which results in very less tool wear than uncoated tools. Surface roughness with uncoated tools was found to be three times higher than coated tools due to lower coefficient of friction of coating used.

Keywords: Cutting temperatures, DSS2205, dry turning, HiPIMS, surface integrity.

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Authors: Adewale O. Adegbenjo, Elsie Nsiah-Baafi, Mxolisi B. Shongwe, Mercy Ramakokovhu, Peter A. Olubambi

Abstract:

The sintering step in powder metallurgy (P/M) processes is very sensitive as it determines to a large extent the properties of the final component produced. Spark plasma sintering over the past decade has been extensively used in consolidating a wide range of materials including metallic alloy powders. This novel, non-conventional sintering method has proven to be advantageous offering full densification of materials, high heating rates, low sintering temperatures, and short sintering cycles over conventional sintering methods. Ti6Al4V has been adjudged the most widely used α+β alloy due to its impressive mechanical performance in service environments, especially in the aerospace and automobile industries being a light metal alloy with the capacity for fuel efficiency needed in these industries. The P/M route has been a promising method for the fabrication of parts made from Ti6Al4V alloy due to its cost and material loss reductions and the ability to produce near net and intricate shapes. However, the use of this alloy has been largely limited owing to its relatively poor hardness and wear properties. The effect of sintering temperature on the densification, hardness, and wear behaviors of spark plasma sintered Ti6Al4V powders was investigated in this present study. Sintering of the alloy powders was performed in the 650–850°C temperature range at a constant heating rate, applied pressure and holding time of 100°C/min, 50 MPa and 5 min, respectively. Density measurements were carried out according to Archimedes’ principle and microhardness tests were performed on sectioned as-polished surfaces at a load of 100gf and dwell time of 15 s. Dry sliding wear tests were performed at varied sliding loads of 5, 15, 25 and 35 N using the ball-on-disc tribometer configuration with WC as the counterface material. Microstructural characterization of the sintered samples and wear tracks were carried out using SEM and EDX techniques. The density and hardness characteristics of sintered samples increased with increasing sintering temperature. Near full densification (99.6% of the theoretical density) and Vickers’ micro-indentation hardness of 360 HV were attained at 850°C. The coefficient of friction (COF) and wear depth improved significantly with increased sintering temperature under all the loading conditions examined, except at 25 N indicating better mechanical properties at high sintering temperatures. Worn surface analyses showed the wear mechanism was a synergy of adhesive and abrasive wears, although the former was prevalent.

Keywords: Hardness, powder metallurgy, Spark plasma sintering, wear.

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Authors: B. Arzhanov, A. Correia, P. Delgado, J. Meireles

Abstract:

Quad Flat No-Lead (QFN) packages have become very popular for turners, converters and audio amplifiers, among others applications, needing efficient power dissipation in small footprints. Since semiconductor junction temperature (T_J) is a critical parameter in the product quality. And to ensure that die temperature does not exceed the maximum allowable T_J, a thermal analysis conducted in an earlier development phase is essential to avoid repeated re-designs process with huge losses in cost and time. A simulation tool capable to estimate die temperature of components with QFN package was developed. Allow establish a non-empirical way to define an acceptance criterion for amount of voids in solder interface between its exposed pad and Printed Circuit Board (PCB) to be applied during industrialization process, and evaluate the impact of PCB designs parameters. Targeting PCB layout designer as an end user for the application, a user-friendly interface (GUI) was implemented allowing user to introduce design parameters in a convenient and secure way and hiding all the complexity of finite element simulation process. This cost effective tool turns transparent a simulating process and provides useful outputs after acceptable time, which can be adopted by PCB designers, preventing potential risks during the design stage and make product economically efficient by not oversizing it. This article gathers relevant information related to the design and implementation of the developed tool, presenting a parametric study conducted with it. The simulation tool was experimentally validated using a Thermal-Test-Chip (TTC) in a QFN open-cavity, in order to measure junction temperature (T_J) directly on the die under controlled and knowing conditions. Providing a short overview about standard thermal solutions and impacts in exposed pad packages (i.e. QFN), accurately describe the methods and techniques that the system designer should use to achieve optimum thermal performance, and demonstrate the effect of system-level constraints on the thermal performance of the design.

Keywords: Quad Flat No-Lead packages, exposed pads, junction temperature, thermal management and measurements.

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