Monitorization of Junction Temperature Using a Thermal-Test-Device

Authors: B. Arzhanov, A. Correia, P. Delgado, J. Meireles

Abstract:

Due to the higher power loss levels in electronic components, the thermal design of PCBs (Printed Circuit Boards) of an assembled device becomes one of the most important quality factors in electronics. Nonetheless, some of leading causes of the microelectronic component failures are due to higher temperatures, the leakages or thermal-mechanical stress, which is a concern, is the reliability of microelectronic packages. This article presents an experimental approach to measure the junction temperature of exposed pad packages. The implemented solution is in a prototype phase, using a temperature-sensitive parameter (TSP) to measure temperature directly on the die, validating the numeric results provided by the Mechanical APDL (Ansys Parametric Design Language) under same conditions. The physical device-under-test is composed by a Thermal Test Chip (TTC-1002) and assembly in a QFN cavity, soldered to a test-board according to JEDEC Standards. Monitoring the voltage drop across a forward-biased diode, is an indirectly method but accurate to obtain the junction temperature of QFN component with an applied power range between 0,3W to 1.5W. The temperature distributions on the PCB test-board and QFN cavity surface were monitored by an infra-red thermal camera (Goby-384) controlled and images processed by the Xeneth software. The article provides a set-up to monitorize in real-time the junction temperature of ICs, namely devices with the exposed pad package (i.e. QFN). Presenting the PCB layout parameters that the designer should use to improve thermal performance, and evaluate the impact of voids in solder interface in the device junction temperature.

Keywords: Quad Flat No-Lead packages, exposed pads, junction temperature, thermal management, measurements.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1112067

References:

[1] Turkakar, G. and T. Okutucu-Ozyurt, Dimensional optimization of microchannel heat sinks with multiple heat sources. International Journal of Thermal Sciences, 2012. 62(0): p. 85-92.
[2] Allan, R. Warm up to the latest PCB cooling techniques (2011).
[3] Foli, K., et al., Optimization of micro heat exchanger: CFD, analytical approach and multi-objective evolutionary algorithms. International Journal of Heat and Mass Transfer, 2006. 49(5–6): p.1090-1099.
[4] Edwards, D. Enhance Thermal Performance Through Design and Optimization, 2013.
[5] ‪Husain A, K.K., Multiobjective Optimization of a Microchannel Heat Sink U sing Evolutionary Algorithm. J. Heat Transfer., 130(11), 2008:‬‬‬‬‬‬‬‬‬‬‬‬‬‬‬‬
[6] MA-COM Technology, Surface Mount Instructions for QFN/DFN Packages, Application Note-S2083 (2012).
[7] Sarvar, F., Whalley, D.C. and Conway, P.P., Thermal interface materials, a review of the state of the art, IEEE Electronic System integration Technology, Conference, Dresden, September 2006, vol. 2, pp. 1292-1302
[8] Siva Gurrum and Matt Romig, Using Thermal Calculation Tools for Analog Components, TI Report SLUA566, 2010.
[9] Analog Devices, Tutorial Thermal Design Basics (MT-093), 2009.
[10] Texas Instruments, Semiconductor and IC Package Thermal Metrics, Application Report-SPRA953B, 2012.
[11] RFMD, Calculating Junction Temperature from Thermal Resistance, Design application note AN027 (2002).
[12] Cirrus Logic. (2007). AN315 - Thermal Considerations for QFN Packaged Integrated Circuits.
[13] Thermal Engineering Associate, inc (TEA), TECH BRIEF (TB-07), Diode Junction Temperature & Thermal Resistance Measurements (2010).
[14] Jason chonko, Using Forward Voltage to Measure Semiconductor Junction Temperature, Keithley Instruments, 2006.
[15] Actel, Application Note AC322, Assembly and PCB Layout Guidelines for QFN packages, 2008.
[16] Maxim integrated, Thermal Considerations of QFN and Other Exposed-Paddle Packages, Application Note: HFAN-08.1 (2008).
[17] Mohammad Yunusa, K. Srihari, J.M. Pitarresi, Anthony Primavera, Effect of voids on the reliability of BGA/CSP solder joints, Microelectronics Reliability 43 (2003) 2077-2086.
[18] Texas Instruments, Design Guide (SPRABI3), Thermal Design Guide for KeyStone Devices, 2010.
[19] EIA/JEDEC Standard No. 51-3, Low Effective Thermal Conductivity Test-Board for Leaded Surface Mount Packages, 1995.
[20] Thermal Engineering Associate inc (TEA), Thermal Test Chips - TTC-1002 datasheet (2009).
[21] Heraeus, Bonding Wires for Semiconductor Technology (datasheet), 2013.
[22] JEDEC Standard No. 51-2A, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air), 1995.
[23] EIA/JEDEC Standard No. 51-1, Integrated Circuits Thermal Measurement Method-Electrical Test Method (Single Semiconductor Device), 1995.
[24] B. Arzhanov, A. Correia, P. Delgado, J. Meireles, Thermal evaluation of PCB design options and voids in solder interface by a simulation tool, HMIExcel Innovation, University of Minho and Bosch Car Multimedia (2015).
[25] Thermal Engineering Associate inc (TEA), An Introduction to Diode Thermal Measurements, TEA, Tech Brief (2009).