Search results for: Adiabatic logic

Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: Abdelrahman A. H. Abdelrahim, Gharib Subhi Mahmoud, Sherzod Turaev, Azeddine Messikh

Abstract:

Quantum gates are the basic building blocks in the quantum circuits model. These gates can be implemented using adiabatic or non adiabatic processes. Adiabatic models can be controlled using auxiliary qubits, whereas non adiabatic models can be simplified by using one single-shot implementation. In this paper, the controlled adiabatic evolutions is combined with the single-shot implementation to obtain quantum gates with controlled non adiabatic evolutions. This is an important improvement which can speed the implementation of quantum gates and reduce the errors due to the long run in the adiabatic model. The robustness of our scheme to different types of errors is also investigated.

Keywords: Adiabatic evolutions, non adiabatic evolutions, controlled adiabatic evolutions, quantum rotation gates, dephasing rates, master equation.

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Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: M. Mohsenzadeh, F. Shams, M. Teshnehlab

Abstract:

Current research on semantic web aims at making intelligent web pages meaningful for machines. In this way, ontology plays a primary role. We believe that logic can help ontology languages (such as OWL) to be more fluent and efficient. In this paper we try to combine logic with OWL to reduce some disadvantages of this language. Therefore we extend OWL by logic and also show how logic can satisfy our future expectations of an ontology language.

Keywords: Logical Programming, OWL, Language Extension.

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Authors: E. Elgendy, J. Schmidt

Abstract:

Drop-in of R-22 alternatives in refrigeration and air conditioning systems requires a redesign of system components to improve system performance and reliability with the alternative refrigerants. The present paper aims at design adiabatic capillary tubes for R-22 alternatives such as R-417A, R-422D and R-438A. A theoretical model has been developed and validated with the available experimental data from literature for R-22 over a wide range of both operating and geometrical parameters. Predicted lengths of adiabatic capillary tube are compared with the lengths of the capillary tube needed under similar experimental conditions and majority of predictions are found to be within 4.4% of the experimental data. Hence, the model has been applied for R-417A, R- 422D and R-438A and capillary tube selection charts and correlations have been computed. Finally a comparison between the selected refrigerants and R-22 has been introduced and the results showed that R-438A is the closest one to R-22.

Keywords: Adiabatic flow, Capillary tube, R-22 alternatives, Rating charts, Modelling.

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Authors: Padmanabhan Balasubramanian, Bashetty Raghavendra

Abstract:

In this paper, an analysis is presented, which demonstrates the effect pre-logic factoring could have on an automated combinational logic synthesis process succeeding it. The impact of pre-logic factoring for some arbitrary combinatorial circuits synthesized within a FPGA based logic design environment has been analyzed previously. This paper explores a similar effect, but with the non-regenerative logic synthesized using elements of a commercial standard cell library. On an overall basis, the results obtained pertaining to the analysis on a variety of MCNC/IWLS combinational logic benchmark circuits indicate that pre-logic factoring has the potential to facilitate simultaneous power, delay and area optimized synthesis solutions in many cases.

Keywords: Algebraic factoring, Combinational logic synthesis, Standard cells, Low power, Delay optimization, Area reduction.

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Authors: Hyun-Kyu Kang

Abstract:

The Korean Government has applied the preliminary feasibility study to new government R&D program plans as a part of an evaluation system for R&D programs. The preliminary feasibility study for the R&D program is composed of 3 major criteria such as technological, policy and economic analysis. The program logic model approach is used as a part of the technological analysis in the preliminary feasibility study. We has developed and improved the R&D program logic model. The logic model is a very useful tool for evaluating R&D program plans. Using a logic model, we can generally identify important factors of the R&D program plan, analyze its logic flow and find the disconnection or jump in the logic flow among components of the logic model.

Keywords: Preliminary feasibility study, R&D program logic model, technological analysis.

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Authors: K. Jaroensutasinee

Abstract:

The general global behavior of particle S a non-linear (Q - xy)2 potential cannot be revealed a Poincare surface of section method (PSS) because inost trajectories take practically infinitely long time to integrate numerically before they come back to the surface. In this study as an alternative to PSS, a multiple scale perturbation is applied to analyze global adiabatic, non-adiabatic and chaotic behavior of particles in this potential. It was found that the results can be summarized as a form of a Fermi-like map. Additionally, this method gives a variation of global stochasticity criteria with Q.

Keywords: Multiple Scak Perturbation The Poincare Surface or Section, Fermi Map

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Authors: Aye Aye Mon

Abstract:

The application of a simple microcontroller to deal with a three variable input and a single output fuzzy logic controller, with Proportional – Integral – Derivative (PID) response control built-in has been tested for an automatic voltage regulator. The fuzzifiers are based on fixed range of the variables of output voltage. The control output is used to control the wiper motor of the auto transformer to adjust the voltage, using fuzzy logic principles, so that the voltage is stabilized. In this report, the author will demonstrate how fuzzy logic might provide elegant and efficient solutions in the design of multivariable control based on experimental results rather than on mathematical models.

Keywords: Fuzzy logic system, PID Controller, control systems, controlled A V R

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Authors: Omid Mirmotahari, Yngvar Berg, Ahmad Habibizad Navin

Abstract:

Reversible logic is becoming more and more prominent as the technology sets higher demands on heat, power, scaling and stability. Reversible gates are able at any time to "undo" the current step or function. Multiple-valued logic has the advantage of transporting and evaluating higher bits each clock cycle than binary. Moreover, we demonstrate in this paper, combining these disciplines we can construct powerful multiple-valued reversible logic structures. In this paper a reversible block implemented by pseudo floatinggate can perform AD-function and a DA-function as its reverse application.

Keywords: Reversible logic, bi-directional, Pseudo floating-gate(PFG), multiple-valued logic (MVL).

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Authors: Naiqin Feng, Yuhui Qiu, Yingshan Zhang, Fang Wang

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A logic model for analyzing complex systems- stability is very useful to many areas of sciences. In the real world, we are enlightened from some natural phenomena such as “biosphere", “food chain", “ecological balance" etc. By research and practice, and taking advantage of the orthogonality and symmetry defined by the theory of multilateral matrices, we put forward a logic analysis model of stability of complex systems with three relations, and prove it by means of mathematics. This logic model is usually successful in analyzing stability of a complex system. The structure of the logic model is not only clear and simple, but also can be easily used to research and solve many stability problems of complex systems. As an application, some examples are given.

Keywords: Complex system, logic model, relation, stability.

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Authors: Mujde Turkkan, Nurkan Yagiz

Abstract:

In this study an active controller is presented for vibration suppression of a full-bus model. The bus is modeled having seven degrees of freedom. Using the achieved model via Lagrange Equations the system equations of motion are derived. The suspensions of the bus model include air springs with two auxiliary chambers are used. Fuzzy logic controller is used to improve the ride comfort. The numerical results, verifies that the presented fuzzy logic controller improves the ride comfort.

Keywords: Ride comfort, air spring, bus, fuzzy logic controller.

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Authors: Mohamed Amine Haraoubia, Abdelaziz Hamzaoui, Najib Essounbouli

Abstract:

The pursuit of the MPPT has led to the development of many kinds of controllers, one of which is the Fuzzy Logic controller, which has proven its worth. To further tune this controller this paper will discuss and analyze the use of Genetic Algorithms to tune the Fuzzy Logic Controller. It will provide an introduction to both systems, and test their compatibility and performance.

Keywords: Fuzzy logic controller (FLC), fuzzy logic (FL), genetic algorithm (GA), maximum power point (MPP), maximum power point tracking (MPPT).

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Authors: K. Maria Agnes, J. Joshua Bapu

Abstract:

This paper impart the design and testing of Nanotechnology based sequential circuits using multiplexer conservative QCA (MX-CQCA) logic gates, which is easily testable using only two vectors. This method has great prospective in the design of sequential circuits based on reversible conservative logic gates and also smashes the sequential circuits implemented in traditional gates in terms of testability. Reversible circuits are similar to usual logic circuits except that they are built from reversible gates. Designs of multiplexer conservative QCA logic based two vectors testable double edge triggered (DET) sequential circuits in VHDL language are also accessible here; it will also diminish intricacy in testing side. Also other types of sequential circuits such as D, SR, JK latches are designed using this MX-CQCA logic gate. The objective behind the proposed design methodologies is to amalgamate arithmetic and logic functional units optimizing key metrics such as garbage outputs, delay, area and power. The projected MX-CQCA gate outshines other reversible gates in terms of the intricacy, delay.

Keywords: Conservative logic, Double edge triggered (DET) flip flop, majority voters, MX-CQCA gate, reversible logic, Quantum dot Cellular automata.

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Authors: Yun Bai

Abstract:

As a security mechanism, authorization is to provide access control to the system resources according to the polices and rules specified by the security strategies. Either by update or in the initial specification, conflicts in authorization is an issue needs to be solved. In this paper, we propose a new approach to solve conflict by using prioritized logic programs and discuss the uniqueness of its answer set. Addressing conflict resolution from logic programming viewpoint and the uniqueness analysis of the answer set provide a novel, efficient approach for authorization conflict resolution.

Keywords: authorization, formal specification, conflict resolution, prioritized logic program.

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Authors: Paratibha Aggarwal, Yogesh Aggarwal

Abstract:

The paper presents the potential of fuzzy logic (FL-I) and neural network techniques (ANN-I) for predicting the compressive strength, for SCC mixtures. Six input parameters that is contents of cement, sand, coarse aggregate, fly ash, superplasticizer percentage and water-to-binder ratio and an output parameter i.e. 28- day compressive strength for ANN-I and FL-I are used for modeling. The fuzzy logic model showed better performance than neural network model.

Keywords: Self compacting concrete, compressive strength, prediction, neural network, Fuzzy logic.

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Authors: T. H. Fung

Abstract:

Coloured Petri net (CPN) has been widely adopted in various areas in Computer Science, including protocol specification, performance evaluation, distributed systems and coordination in multi-agent systems. It provides a graphical representation of a system and has a strong mathematical foundation for proving various properties. This paper proposes a novel representation of a coloured Petri net using an extension of logic programming called abductive logic programming (ALP), which is purely based on classical logic. Under such a representation, an implementation of a CPN could be directly obtained, in which every inference step could be treated as a kind of equivalence preserved transformation. We would describe how to implement a CPN under such a representation using common meta-programming techniques in Prolog. We call our framework CPN-LP and illustrate its applications in modeling an intelligent agent.

Keywords: Abduction, coloured petri net, intelligent agent, logic programming.

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Authors: Walter Hussak

Abstract:

We present an operator for a propositional linear temporal logic over infinite schedules of iterated transactions, which, when applied to a formula, asserts that any schedule satisfying the formula is serializable. The resulting logic is suitable for specifying and verifying consistency properties of concurrent transaction management systems, that can be defined in terms of serializability, as well as other general safety and liveness properties. A strict form of serializability is used requiring that, whenever the read and write steps of a transaction occurrence precede the read and write steps of another transaction occurrence in a schedule, the first transaction must precede the second transaction in an equivalent serial schedule. This work improves on previous work in providing a propositional temporal logic with a serializability operator that is of the same PSPACE complete computational complexity as standard propositional linear temporal logic without a serializability operator.

Keywords: Temporal logic, iterated transactions, serializability.

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Authors: Chang Liu, Zishu He

Abstract:

Adaptive echo cancellers with two-path algorithm are applied to avoid the false adaptation during the double-talk situation. In the two-path algorithm, several transfer logic solutions have been proposed to control the filter update. This paper presents an improved transfer logic solution. It improves the convergence speed of the two-path algorithm, and allows the reduction of the memory elements and computational complexity. Results of simulations show the improved performance of the proposed solution.

Keywords: Acoustic echo cancellation, Echo return lossenhancement (ERLE), Two-path algorithm, Transfer logic

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Authors: S. Grace Sahaya Sheba, R. Omegala Priakumari

Abstract:

Polyethylene glycol (PEG) is a condensation polymer of ethylene oxide and water. It is soluble in water and in many organic solvents. PEG is used to make emulsifying agents, detergents, soaps, plasticizers, ointments etc. Ethanol (C₂H₅OH) also known as ethyl alcohol is a well-known organic compound and has wide applications in chemical industry as it is used as a solvent for paint, varnish, in preserving biological specimens, used as a fuel mixed with petrol etc. Though their chemical and physical properties are already studied, still because of their uses in day to day life the authors thought it is better to study some more of their physical properties like ultrasonic velocity and hence adiabatic compressibility, free length, etc. A detailed study of such properties and some excess parameters like excess adiabatic compressibility, excess free volume and few more in the liquid mixtures of these two compounds with PEG as a solute and Ethanol as a solvent at various mole fractions may throw some light on deeper understanding of molecular interaction between the solute and the solvent supported by NMR, IR etc. Hence the present research work is on ultrasonics/allied studies on these two liquid mixtures. Ultrasonic velocity (U), density (ρ) and viscosity (η) at room temperature and at different mole fraction from 0 to 0.055 of ethanol in PEG have been experimentally carried out by the authors. Acoustical parameters such as adiabatic compressibility (β), free volume (V_f), acoustic impedance (Z), internal pressure (π_i), intermolecular free length (L_f) and relaxation time (τ) were calculated from the experimental data. We have calculated excess parameters like excess adiabatic compressibility (β^E), excess internal pressure (π_i^E) free length (L_f^E) and excess acoustic impedance (Z^E) etc for these two chosen liquid mixtures. The excess compressibility is positive and maximum around a mole fraction 0.007 and excess internal pressure is negative and maximum at the same mole fraction and longer free length. The results are analyzed and it may be concluded that the molecular interactions between the solute and the solvent is not strong and it may be weak. Appropriate graphs are drawn.

Keywords: Adiabatic Compressibility, Binary mixture, Induce dipole, Polarizability, Ultrasonic.

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Authors: Shane D. Inder, Mehrdad Khamooshi

Abstract:

Efficient energy storage is a crucial factor in facilitating the uptake of renewable energy resources. Among the many options available for energy storage systems required to balance imbalanced supply and demand cycles, compressed air energy storage (CAES) is a proven technology in grid-scale applications. This paper reviews the current state of micro scale CAES technology and describes a micro-scale advanced adiabatic CAES (A-CAES) system, where heat generated during compression is stored for use in the discharge phase. It will also describe a thermodynamic model, developed in EES (Engineering Equation Solver) to evaluate the performance and critical parameters of the discharge phase of the proposed system. Three configurations are explained including: single turbine without preheater, two turbines with preheaters, and three turbines with preheaters. It is shown that the micro-scale A-CAES is highly dependent upon key parameters including; regulator pressure, air pressure and volume, thermal energy storage temperature and flow rate and the number of turbines. It was found that a micro-scale AA-CAES, when optimized with an appropriate configuration, could deliver energy input to output efficiency of up to 70%.

Keywords: CAES, adiabatic compressed air energy storage, expansion phase, micro generation, thermodynamic.

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Authors: Suguru Yoshioka, Satoshi Tojo

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This paper introduces a temporal epistemic logic CBCTL that updates agent-s belief states through communications in them, based on computational tree logic (CTL). In practical environments, communication channels between agents may not be secure, and in bad cases agents might suffer blackouts. In this study, we provide inform* protocol based on ACL of FIPA, and declare the presence of secure channels between two agents, dependent on time. Thus, the belief state of each agent is updated along with the progress of time. We show a prover, that is a reasoning system for a given formula in a given a situation of an agent ; if it is directly provable or if it could be validated through the chains of communications, the system returns the proof.

Keywords: communication channel, computational tree logic, reasoning system, temporal epistemic logic.

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Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

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Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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Authors: Cecília Reis, J. A. Tenreiro Machado, J. Boaventura Cunha

Abstract:

This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. The experiments reveal superior results in terms of speed and convergence to achieve a solution.

Keywords: Circuit design, fractional-order systems, genetic algorithms, logic circuits

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Authors: Padmanabhan Balasubramanian, R. Chinnadurai

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This paper deals with a power-conscious ANDEXOR- Inverter type logic implementation for a complex class of Boolean functions, namely Achilles- heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications).

Keywords: Achilles' heel functions, AND-EXOR-Inverter logic, CMOS technology, low power design.

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Authors: Noura Boudiaf, Abdelhamid Djebbar

Abstract:

Colored Petri Nets (CPN) are very known kind of high level Petri nets. With sound and complete semantics, rewriting logic is one of very powerful logics in description and verification of non-deterministic concurrent systems. Recently, CPN semantics are defined in terms of rewriting logic, allowing us to built models by formal reasoning. In this paper, we propose an automatic translation of CPN to the rewriting logic language Maude. This tool allows graphical editing and simulating CPN. The tool allows the user drawing a CPN graphically and automatic translating the graphical representation of the drawn CPN to Maude specification. Then, Maude language is used to perform the simulation of the resulted Maude specification. It is the first rewriting logic based environment for this category of Petri Nets.

Keywords: Colored Petri Nets, Rewriting Logic, Maude, Graphical Edition, Automatic Translation, Simulation.

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Authors: Daniel Stamate

Abstract:

We introduce a logic-based framework for database updating under constraints. In our framework, the constraints are represented as an instantiated extended logic program. When performing an update, database consistency may be violated. We provide an approach of maintaining database consistency, and study the conditions under which the maintenance process is deterministic. We show that the complexity of the computations and decision problems presented in our framework is in each case polynomial time.

Keywords: Databases, knowledge bases, constraints, updates, minimal change, consistency.

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Authors: V. K. Banga, R. Kumar, Y. Singh

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In this paper, we present optimal control for movement and trajectory planning for four degrees-of-freedom robot using Fuzzy Logic (FL) and Genetic Algorithms (GAs). We have evaluated using Fuzzy Logic (FL) and Genetic Algorithms (GAs) for four degree-of-freedom (4 DOF) robotics arm, Uncertainties like; Movement, Friction and Settling Time in robotic arm movement have been compensated using Fuzzy logic and Genetic Algorithms. The development of a fuzzy genetic optimization algorithm is presented and discussed. The result are compared only GA and Fuzzy GA. This paper describes genetic algorithms, which is designed to optimize robot movement and trajectory. Though the model represents is a general model for redundant structures and could represent any n-link structures. The result is a complete trajectory planning with Fuzzy logic and Genetic algorithms demonstrating the flexibility of this technique of artificial intelligence.

Keywords: Inverse kinematics, Genetic algorithms (GAs), Fuzzy logic (FL), Trajectory planning.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

Abstract:

Evolvable hardware (EHW) is a developing field that applies evolutionary algorithm (EA) to automatically design circuits, antennas, robot controllers etc. A lot of research has been done in this area and several different EAs have been introduced to tackle numerous problems, as scalability, evolvability etc. However every time a specific EA is chosen for solving a particular task, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade the selection of the right parameters for the EA-s components for solving different “test-problems" has been investigated. In this paper the behaviour of mutation rate for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies the number of inputs of each logic gates, the functionality (for example from AND to NOR) and the connectivity between logic gates. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates for the evolved circuits. The experimental results found provide the behaviour of the mutation rate during evolution for the design and optimization of simple logic circuits. The experimental results propose the best mutation rate to be used for designing combinational logic circuits. The research presented is particular important for those who would like to implement a dynamic mutation rate inside the evolutionary algorithm for evolving digital circuits. The researches on the mutation rate during the last 40 years are also summarized.

Keywords: Design of logic circuit, evolutionary computation, evolvable hardware, mutation rate.

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