Search results for: High Level Architecture
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 8838

Search results for: High Level Architecture

8688 Operational risks Classification for Information Systems with Service-Oriented Architecture (Including Loss Calculation Example)

Authors: Irina Pyrlina

Abstract:

This article presents the results of a study conducted to identify operational risks for information systems (IS) with service-oriented architecture (SOA). Analysis of current approaches to risk and system error classifications revealed that the system error classes were never used for SOA risk estimation. Additionally system error classes are not normallyexperimentally supported with realenterprise error data. Through the study several categories of various existing error classifications systems are applied and three new error categories with sub-categories are identified. As a part of operational risks a new error classification scheme is proposed for SOA applications. It is based on errors of real information systems which are service providers for application with service-oriented architecture. The proposed classification approach has been used to classify SOA system errors for two different enterprises (oil and gas industry, metal and mining industry). In addition we have conducted a research to identify possible losses from operational risks.

Keywords: Enterprise architecture, Error classification, Oil&Gas and Metal&Mining industries, Operational risks, Serviceoriented architecture

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8687 Design of Low Power and High Speed Digital IIR Filter in 45nm with Optimized CSA for Digital Signal Processing Applications

Authors: G. Ramana Murthy, C. Senthilpari, P. Velrajkumar, Lim Tien Sze

Abstract:

In this paper, a design methodology to implement low-power and high-speed 2nd order recursive digital Infinite Impulse Response (IIR) filter has been proposed. Since IIR filters suffer from a large number of constant multiplications, the proposed method replaces the constant multiplications by using addition/subtraction and shift operations. The proposed new 6T adder cell is used as the Carry-Save Adder (CSA) to implement addition/subtraction operations in the design of recursive section IIR filter to reduce the propagation delay. Furthermore, high-level algorithms designed for the optimization of the number of CSA blocks are used to reduce the complexity of the IIR filter. The DSCH3 tool is used to generate the schematic of the proposed 6T CSA based shift-adds architecture design and it is analyzed by using Microwind CAD tool to synthesize low-complexity and high-speed IIR filters. The proposed design outperforms in terms of power, propagation delay, area and throughput when compared with MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental results that the proposed 6T based design method can find better IIR filter designs in terms of power and delay than those obtained by using efficient general multipliers.

Keywords: CSA Full Adder, Delay unit, IIR filter, Low-Power, PDP, Parametric Analysis, Propagation Delay, Throughput, VLSI.

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8686 QSI Dynamical Fetch Policy for SMT

Authors: Shu-Chiao Yang, Jong-Jiann Shieh

Abstract:

A Simultaneous Multithreading (SMT) Processor is capable of executing instructions from multiple threads in the same cycle. SMT in fact was introduced as a powerful architecture to superscalar to increase the throughput of the processor. Simultaneous Multithreading is a technique that permits multiple instructions from multiple independent applications or threads to compete limited resources each cycle. While the fetch unit has been identified as one of the major bottlenecks of SMT architecture, several fetch schemes were proposed by prior works to enhance the fetching efficiency and overall performance. In this paper, we propose a novel fetch policy called queue situation identifier (QSI) which counts some kind of long latency instructions of each thread each cycle then properly selects which threads to fetch next cycle. Simulation results show that in best case our fetch policy can achieve 30% on speedup and also can reduce the data cache level 1 miss rate.

Keywords: SMT, QSI, DL1 miss rate.

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8685 The Study on the Development of Ornamentation in the Architecture of Safavid Dynasty

Authors: N. Utaberta, H. Mamamni, M. Surat, A. I. Che-Ani, N.A.G. Abdullah

Abstract:

The architecture of Safavid Dynasty can be considered the epitome of Iranian architectural beauty. Safavid dynasty (1501- 1722 AC) along with Ottoman in Turkey and Mughal Empire in India were the three great Islamic nations of their time (1500 AC) often known as the last Islamic countries with international authority up to the 20th Century. This era approximately coincide with Renaissance in Europe. In this era, large European countries begin amassing power thanks to significant scientific, cultural and religious revolutions of that time and colonizing nations such as England, Spain and Portugal began to influence international trends with in an increasing while other non-industrial nations diminished. The main objective of this paper is to give a typological overview of the development of decoration and ornament in the architecture of Safafid Dynasty in Iran. It is expected that it can start a wider discussion to enrich this nation-s heritage and contribute to the development of Islamic ornament in general.

Keywords: Ornamentation, Architecture in Iran, Safavid Dynasty

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8684 A Technique for Execution of Written Values on Shared Variables

Authors: Parvinder S. Sandhu, Vijay K. Banga, Prateek Gupta, Amit Verma

Abstract:

The current paper conceptualizes the technique of release consistency indispensable with the concept of synchronization that is user-defined. Programming model concreted with object and class is illustrated and demonstrated. The essence of the paper is phases, events and parallel computing execution .The technique by which the values are visible on shared variables is implemented. The second part of the paper consist of user defined high level synchronization primitives implementation and system architecture with memory protocols. There is a proposition of techniques which are core in deciding the validating and invalidating a stall page .

Keywords: synchronization objects, barrier, phases and events, shared memory

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8683 The Creation of Sustainable Architecture by use of Transformable Intelligent Building Skins

Authors: Maziar Asefi

Abstract:

Built environments have a large impact on environmental sustainability and if it is not considered properly can negatively affect our planet. The application of transformable intelligent building systems that automatically respond to environmental conditions is one of the best ways that can intelligently assist us to create sustainable environment. The significance of this issue is evident as energy crisis and environmental changes has made the sustainability the main concerns in many societies. The aim of this research is to review and evaluate the importance and influence of transformable intelligent structure on the creation of sustainable architecture. Intelligent systems in current buildings provide convenience through automatically responding to changes in environmental conditions, reducing energy dissipation and increase of the lifecycle of buildings. This paper by analyzing significant intelligent building systems will evaluate the potentials of transformable intelligent systems in the creation of sustainable architecture and environment.

Keywords: Transformable, Sustainable architecture, Intelligent building system, Environment condition

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8682 Towards an Enhanced Quality of IPTV Media Server Architecture over Software Defined Networking

Authors: Esmeralda Hysenbelliu

Abstract:

The aim of this paper is to present the QoE (Quality of Experience) IPTV SDN-based media streaming server enhanced architecture for configuring, controlling, management and provisioning the improved delivery of IPTV service application with low cost, low bandwidth, and high security. Furthermore, it is given a virtual QoE IPTV SDN-based topology to provide an improved IPTV service based on QoE Control and Management of multimedia services functionalities. Inside OpenFlow SDN Controller there are enabled in high flexibility and efficiency Service Load-Balancing Systems; based on the Loading-Balance module and based on GeoIP Service. This two Load-balancing system improve IPTV end-users Quality of Experience (QoE) with optimal management of resources greatly. Through the key functionalities of OpenFlow SDN controller, this approach produced several important features, opportunities for overcoming the critical QoE metrics for IPTV Service like achieving incredible Fast Zapping time (Channel Switching time) < 0.1 seconds. This approach enabled Easy and Powerful Transcoding system via FFMPEG encoder. It has the ability to customize streaming dimensions bitrates, latency management and maximum transfer rates ensuring delivering of IPTV streaming services (Audio and Video) in high flexibility, low bandwidth and required performance. This QoE IPTV SDN-based media streaming architecture unlike other architectures provides the possibility of Channel Exchanging between several IPTV service providers all over the word. This new functionality brings many benefits as increasing the number of TV channels received by end –users with low cost, decreasing stream failure time (Channel Failure time < 0.1 seconds) and improving the quality of streaming services.

Keywords: Improved QoE, OpenFlow SDN controller, IPTV service application, softwarization.

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8681 Service-Oriented Architecture for Object- Centric Information Fusion

Authors: Jeffrey A. Dunne, Kevin Ligozio

Abstract:

In many applications there is a broad variety of information relevant to a focal “object" of interest, and the fusion of such heterogeneous data types is desirable for classification and categorization. While these various data types can sometimes be treated as orthogonal (such as the hull number, superstructure color, and speed of an oil tanker), there are instances where the inference and the correlation between quantities can provide improved fusion capabilities (such as the height, weight, and gender of a person). A service-oriented architecture has been designed and prototyped to support the fusion of information for such “object-centric" situations. It is modular, scalable, and flexible, and designed to support new data sources, fusion algorithms, and computational resources without affecting existing services. The architecture is designed to simplify the incorporation of legacy systems, support exact and probabilistic entity disambiguation, recognize and utilize multiple types of uncertainties, and minimize network bandwidth requirements.

Keywords: Data fusion, distributed computing, service-oriented architecture, SOA

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8680 A Middleware Transparent Framework for Applying MDA to SOA

Authors: Ali Taee Zade, Siamak Rasulzadeh, Reza Torkashvan

Abstract:

Although Model Driven Architecture has taken successful steps toward model-based software development, this approach still faces complex situations and ambiguous questions while applying to real world software systems. One of these questions - which has taken the most interest and focus - is how model transforms between different abstraction levels, MDA proposes. In this paper, we propose an approach based on Story Driven Modeling and Aspect Oriented Programming to ease these transformations. Service Oriented Architecture is taken as the target model to test the proposed mechanism in a functional system. Service Oriented Architecture and Model Driven Architecture [1] are both considered as the frontiers of their own domain in the software world. Following components - which was the greatest step after object oriented - SOA is introduced, focusing on more integrated and automated software solutions. On the other hand - and from the designers' point of view - MDA is just initiating another evolution. MDA is considered as the next big step after UML in designing domain.

Keywords: SOA, MDA, SDM, Model Transformation, Middleware Transparency, Aspects and Jini.

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8679 Comparison of Artificial Neural Network Architectures in the Task of Tourism Time Series Forecast

Authors: João Paulo Teixeira, Paula Odete Fernandes

Abstract:

The authors have been developing several models based on artificial neural networks, linear regression models, Box- Jenkins methodology and ARIMA models to predict the time series of tourism. The time series consist in the “Monthly Number of Guest Nights in the Hotels" of one region. Several comparisons between the different type models have been experimented as well as the features used at the entrance of the models. The Artificial Neural Network (ANN) models have always had their performance at the top of the best models. Usually the feed-forward architecture was used due to their huge application and results. In this paper the author made a comparison between different architectures of the ANNs using simply the same input. Therefore, the traditional feed-forward architecture, the cascade forwards, a recurrent Elman architecture and a radial based architecture were discussed and compared based on the task of predicting the mentioned time series.

Keywords: Artificial Neural Network Architectures, time series forecast, tourism.

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8678 A Look at the History of Calligraphy in Decoration of Mosques in Iran: 630-1630 AD

Authors: Cengiz Tavşan, Niloufar Akbarzadeh

Abstract:

Architecture in Iran has a continuous history from at least 5000 BC to the present, and numerous Iranian pre-Islamic elements have contributed significantly to the formation of Islamic art. At first, decoration was limited to small objects and containers and then progressed in the art of plaster and brickwork. They later applied in architecture as well. The art of gypsum and brickwork, which was prevalent in the form of motifs (animals and plants) in pre-Islam, was used in the aftermath of Islam with the art of calligraphy in decorations. The splendor and beauty of Iranian architecture, especially during the Islamic era, are related to decoration and design. After the invasion of Iran by the Arabs and the introduction of Islam to Iran, the arrival of the Iranian classical architecture significantly changed, and we saw the Arabic calligraphy decoration of the mosques in Iran. The principles of aesthetics in the art of calligraphy in Iran are based precisely on the principles of the beauty of ancient Iranian and Islamic art. On the other hand, after Islam, calligraphy was one of the most important sources of Islamic art in Islam and one of the important features of Islamic culture. First, the calligraphy had no cultural meaning and was only for decoration and beautification, it had the same meaning only in the inscriptions; however, over time, it became meaningful. This article provides a summary of the history of calligraphy in the mosques (from the entrance to Islam until the Safavid period), which cannot ignore the role of the calligraphy in their decorative ideas; and also, the important role that decorative elements play in creating a public space in terms of social and aesthetic performance. This study was conducted using library studies and field studies. The purpose of this study is to show the characteristics of architecture and art of decorations in Iran, especially in the mosque's architecture, which reaches the pinnacle of progress. We will see that religious beliefs and artistic practices are merging and trying to bring a single concept.

Keywords: Islamic art, Islamic architecture, decorations in Iranian mosques, calligraphy.

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8677 A Biometric Template Security Approach to Fingerprints Based on Polynomial Transformations

Authors: Ramon Santana

Abstract:

The use of biometric identifiers in the field of information security, access control to resources, authentication in ATMs and banking among others, are of great concern because of the safety of biometric data. In the general architecture of a biometric system have been detected eight vulnerabilities, six of them allow obtaining minutiae template in plain text. The main consequence of obtaining minutia templates is the loss of biometric identifier for life. To mitigate these vulnerabilities several models to protect minutiae templates have been proposed. Several vulnerabilities in the cryptographic security of these models allow to obtain biometric data in plain text. In order to increase the cryptographic security and ease of reversibility, a minutiae templates protection model is proposed. The model aims to make the cryptographic protection and facilitate the reversibility of data using two levels of security. The first level of security is the data transformation level. In this level generates invariant data to rotation and translation, further transformation is irreversible. The second level of security is the evaluation level, where the encryption key is generated and data is evaluated using a defined evaluation function. The model is aimed at mitigating known vulnerabilities of the proposed models, basing its security on the impossibility of the polynomial reconstruction.

Keywords: Fingerprint, template protection, bio-cryptography, minutiae protection.

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8676 On-line Lao Handwritten Recognition with Proportional Invariant Feature

Authors: Khampheth Bounnady, Boontee Kruatrachue, Somkiat Wangsiripitak

Abstract:

This paper proposed high level feature for online Lao handwritten recognition. This feature must be high level enough so that the feature is not change when characters are written by different persons at different speed and different proportion (shorter or longer stroke, head, tail, loop, curve). In this high level feature, a character is divided in to sequence of curve segments where a segment start where curve reverse rotation (counter clockwise and clockwise). In each segment, following features are gathered cumulative change in direction of curve (- for clockwise), cumulative curve length, cumulative length of left to right, right to left, top to bottom and bottom to top ( cumulative change in X and Y axis of segment). This feature is simple yet robust for high accuracy recognition. The feature can be gather from parsing the original time sampling sequence X, Y point of the pen location without re-sampling. We also experiment on other segmentation point such as the maximum curvature point which was widely used by other researcher. Experiments results show that the recognition rates are at 94.62% in comparing to using maximum curvature point 75.07%. This is due to a lot of variations of turning points in handwritten.

Keywords: Handwritten feature, chain code, Lao handwritten recognition.

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8675 The Construction of Interactive Computer Multimedia Instruction on “Basic Japanese Vocabulary“

Authors: Kongrit Jittangthammagul, Sakesun Yampinij, Thapanee Endoo, Nattapong Kramwong

Abstract:

The study entitled “The Construction of Interactive Computer Multimedia Instruction on Basic Japanese Vocabulary" was aimed: 1) To construct the interactive computer multimedia instruction on Basic Japanese Vocabulary, 2) To find out multimedia-s quality, 3) To examine the student-s satisfaction and 4) To study the learning achievement in Basic Japanese vocabulary. The sampling group used in this study was composed of 40 1st year student in Educational Communications and Technology Department, Faculty of Industrial Education and Technology, King Mongkut-s University of Technology Thonburi, in the academic year 2553 B.E. (2010). According to research results, we found that 1). The quality assessment by 3 mass media experts was at 4.72 on average or at high level. 2) In terms of contents, the evaluation by 3 experts was at 4.81 on average or at high level. 3) In terms of achievement, there was a statistical significance between before and after the treatment at the .05 level. 4) The satisfaction of students towards the interactive computer multimedia Instruction on “Basic Japanese Vocabulary" was 4.35 on average, or at high level.

Keywords: Interactive Computer Multimedia on Basic Japanese Vocabulary, Learning Achievement, Quality

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8674 High Level Synthesis of Canny Edge Detection Algorithm on Zynq Platform

Authors: Hanaa M. Abdelgawad, Mona Safar, Ayman M. Wahba

Abstract:

Real time image and video processing is a demand in many computer vision applications, e.g. video surveillance, traffic management and medical imaging. The processing of those video applications requires high computational power. Thus, the optimal solution is the collaboration of CPU and hardware accelerators. In this paper, a Canny edge detection hardware accelerator is proposed. Edge detection is one of the basic building blocks of video and image processing applications. It is a common block in the pre-processing phase of image and video processing pipeline. Our presented approach targets offloading the Canny edge detection algorithm from processing system (PS) to programmable logic (PL) taking the advantage of High Level Synthesis (HLS) tool flow to accelerate the implementation on Zynq platform. The resulting implementation enables up to a 100x performance improvement through hardware acceleration. The CPU utilization drops down and the frame rate jumps to 60 fps of 1080p full HD input video stream.

Keywords: High Level Synthesis, Canny edge detection, Hardware accelerators, and Computer Vision.

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8673 A Cognitive Architectural Approach to the Institutional Roles of Agent Societies

Authors: Antônio Carlos da Rocha Costa

Abstract:

This paper concerns a formal model to help the simulation of agent societies where institutional roles and institutional links can be specified operationally. That is, this paper concerns institutional roles that can be specified in terms of a minimal behavioral capability that an agent should have in order to enact that role and, thus, to perform the set of institutional functions that role is responsible for. Correspondingly, the paper concerns institutional links that can be specified in terms of a minimal interactional capability that two agents should have in order to, while enacting the two institutional roles that are linked by that institutional link, perform for each other the institutional functions supported by that institutional link. The paper proposes a cognitive architecture approach to institutional roles and institutional links, that is, an approach in which a institutional role is seen as an abstract cognitive architecture that should be implemented by any concrete agent (or set of concrete agents) that enacts the institutional role, and in which institutional links are seen as interactions between the two abstract cognitive agents that model the two linked institutional roles. We introduce a cognitive architecture for such purpose, called the Institutional BCC (IBCC) model, which lifts Yoav Shoham-s BCC (Beliefs-Capabilities-Commitments) agent architecture to social contexts. We show how the resulting model can be taken as a means for a cognitive architecture account of institutional roles and institutional links of agent societies. Finally, we present an example of a generic scheme for certain fragments of the social organization of agent societies, where institutional roles and institutional links are given in terms of the model.

Keywords: Simulation of agent societies, institutional roles, cognitive architecture of institutional roles.

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8672 An Axiomatic Model for Development of the Allocated Architecture in Systems Engineering Process

Authors: A. Sharahi, R. Tehrani, A. Mollajan

Abstract:

The final step to complete the “Analytical Systems Engineering Process” is the “Allocated Architecture” in which all Functional Requirements (FRs) of an engineering system must be allocated into their corresponding Physical Components (PCs). At this step, any design for developing the system’s allocated architecture in which no clear pattern of assigning the exclusive “responsibility” of each PC for fulfilling the allocated FR(s) can be found is considered a poor design that may cause difficulties in determining the specific PC(s) which has (have) failed to satisfy a given FR successfully. The present study utilizes the Axiomatic Design method principles to mathematically address this problem and establishes an “Axiomatic Model” as a solution for reaching good alternatives for developing the allocated architecture. This study proposes a “loss Function”, as a quantitative criterion to monetarily compare non-ideal designs for developing the allocated architecture and choose the one which imposes relatively lower cost to the system’s stakeholders. For the case-study, we use the existing design of U. S. electricity marketing subsystem, based on data provided by the U.S. Energy Information Administration (EIA). The result for 2012 shows the symptoms of a poor design and ineffectiveness due to coupling among the FRs of this subsystem.

Keywords: Allocated Architecture, Analytical Systems Engineering Process, Functional Requirements (FRs), Physical Components (PCs), Responsibility of a Physical Component, System’s Stakeholders.

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8671 Product Feature Modelling for Integrating Product Design and Assembly Process Planning

Authors: Baha Hasan, Jan Wikander

Abstract:

This paper describes a part of the integrating work between assembly design and assembly process planning domains (APP). The work is based, in its first stage, on modelling assembly features to support APP. A multi-layer architecture, based on feature-based modelling, is proposed to establish a dynamic and adaptable link between product design using CAD tools and APP. The proposed approach is based on deriving “specific function” features from the “generic” assembly and form features extracted from the CAD tools. A hierarchal structure from “generic” to “specific” and from “high level geometrical entities” to “low level geometrical entities” is proposed in order to integrate geometrical and assembly data extracted from geometrical and assembly modelers to the required processes and resources in APP. The feature concept, feature-based modelling, and feature recognition techniques are reviewed.

Keywords: Assembly feature, assembly process planning, feature, feature-based modelling, form feature, ontology.

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8670 Investigating the Contemporary Architecture Education Challenges in India

Authors: Vriddhi Prasad

Abstract:

The paper briefly outlines the nature of contemporary Architecture Education in India and its present challenges with theoretically feasible solutions. It explores in detail the arduous position of architecture education owing to, privatization of higher education institutes in India, every changing demand of the technology driven industry and discipline, along with regional and cultural resources that should be explored academically for the enrichment of graduates. With the government's education policy of supporting privatization, a comprehensive role for the regulating body of Architecture Education becomes imperative. The paper provides key insights through empirical research into the nature of these roles and the areas which need attention in light of the problems. With the aid of critically acclaimed education model like Design Build, contextual retrofits for Indian institutes can be stressed for inclusion in the curriculum. The pairing of a private institute and public industry/research body and vice versa can lead to pro-economic and pro-social research environment. These reforms if stressed by an autonomous nationwide regulating body rather than the state will lead to uniformity and flexibility of curriculum which promotes the creation of fresh graduates who are adaptable to the changing needs.

Keywords: Architecture education, building information modeling, design build, pedagogy.

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8669 Big Brain: A Single Database System for a Federated Data Warehouse Architecture

Authors: X. Gumara Rigol, I. Martínez de Apellaniz Anzuola, A. Garcia Serrano, A. Franzi Cros, O. Vidal Calbet, A. Al Maruf

Abstract:

Traditional federated architectures for data warehousing work well when corporations have existing regional data warehouses and there is a need to aggregate data at a global level. Schibsted Media Group has been maturing from a decentralised organisation into a more globalised one and needed to build both some of the regional data warehouses for some brands at the same time as the global one. In this paper, we present the architectural alternatives studied and why a custom federated approach was the notable recommendation to go further with the implementation. Although the data warehouses are logically federated, the implementation uses a single database system which presented many advantages like: cost reduction and improved data access to global users allowing consumers of the data to have a common data model for detailed analysis across different geographies and a flexible layer for local specific needs in the same place.

Keywords: Data integration, data warehousing, federated architecture, online analytical processing.

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8668 Influence of Paralleled Capacitance Effect in Well-defined Multiple Value Logical Level System with Active Load

Authors: Chih Chin Yang, Yen Chun Lin, Hsiao Hsuan Cheng

Abstract:

Three similar negative differential resistance (NDR) profiles with both high peak to valley current density ratio (PVCDR) value and high peak current density (PCD) value in unity resonant tunneling electronic circuit (RTEC) element is developed in this paper. The PCD values and valley current density (VCD) values of the three NDR curves are all about 3.5 A and 0.8 A, respectively. All PV values of NDR curves are 0.40 V, 0.82 V, and 1.35 V, respectively. The VV values are 0.61 V, 1.07 V, and 1.69 V, respectively. All PVCDR values reach about 4.4 in three NDR curves. The PCD value of 3.5 A in triple PVCDR RTEC element is better than other resonant tunneling devices (RTD) elements. The high PVCDR value is concluded the lower VCD value about 0.8 A. The low VCD value is achieved by suitable selection of resistors in triple PVCDR RTEC element. The low PV value less than 1.35 V possesses low power dispersion in triple PVCDR RTEC element. The designed multiple value logical level (MVLL) system using triple PVCDR RTEC element provides equidistant logical level. The logical levels of MVLL system are about 0.2 V, 0.8 V, 1.5 V, and 2.2 V from low voltage to high voltage and then 2.2 V, 1.3 V, 0.8 V, and 0.2 V from high voltage back to low voltage in half cycle of sinusoid wave. The output level of four levels MVLL system is represented in 0.3 V, 1.1 V, 1.7 V, and 2.6 V, which satisfies the NMP condition of traditional two-bit system. The remarkable logical characteristic of improved MVLL system with paralleled capacitor are with four significant stable logical levels about 220 mV, 223 mV, 228 mV, and 230 mV. The stability and articulation of logical levels of improved MVLL system are outstanding. The average holding time of improved MVLL system is approximately 0.14 μs. The holding time of improved MVLL system is fourfold than of basic MVLL system. The function of additional capacitor in the improved MVLL system is successfully discovered.

Keywords: Capacitance, Logical level, Constant current source

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8667 Coloured Petri Nets Model for Web Architectures of Web and Database Servers

Authors: Nidhi Gaur, Padmaja Joshi, Vijay Jain, Rajeev Srivastava

Abstract:

Web application architecture is important to achieve the desired performance for the application. Performance analysis studies are conducted to evaluate existing or planned systems. Web applications are used by hundreds of thousands of users simultaneously, which sometimes increases the risk of server failure in real time operations. We use Coloured Petri Net (CPN), a very powerful tool for modelling dynamic behaviour of a web application system. CPNs extend the vocabulary of ordinary Petri nets and add features that make them suitable for modelling large systems. The major focus of this work is on server side of web applications. The presented work focuses on modelling restructuring aspects, with major focus on concurrency and architecture, using CPN. It also focuses on bringing out the appropriate architecture for web and database servers given the number of concurrent users.

Keywords: Coloured petri nets, concurrent users, performance modelling, web application architecture.

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8666 Suitability of Requirements Abstraction Model (RAM) Requirements for High-Level System Testing

Authors: Naeem Muhammad, Yves Vandewoude, Yolande Berbers, Robert Feldt

Abstract:

The Requirements Abstraction Model (RAM) helps in managing abstraction in requirements by organizing them at four levels (product, feature, function and component). The RAM is adaptable and can be tailored to meet the needs of the various organizations. Because software requirements are an important source of information for developing high-level tests, organizations willing to adopt the RAM model need to know the suitability of the RAM requirements for developing high-level tests. To investigate this suitability, test cases from twenty randomly selected requirements were developed, analyzed and graded. Requirements were selected from the requirements document of a Course Management System, a web based software system that supports teachers and students in performing course related tasks. This paper describes the results of the requirements document analysis. The results show that requirements at lower levels in the RAM are suitable for developing executable tests whereas it is hard to develop from requirements at higher levels.

Keywords: Market-driven requirements engineering, requirements abstraction model, requirements abstraction, system testing.

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8665 A Novel VLSI Architecture for Image Compression Model Using Low power Discrete Cosine Transform

Authors: Vijaya Prakash.A.M, K.S.Gurumurthy

Abstract:

In Image processing the Image compression can improve the performance of the digital systems by reducing the cost and time in image storage and transmission without significant reduction of the Image quality. This paper describes hardware architecture of low complexity Discrete Cosine Transform (DCT) architecture for image compression[6]. In this DCT architecture, common computations are identified and shared to remove redundant computations in DCT matrix operation. Vector processing is a method used for implementation of DCT. This reduction in computational complexity of 2D DCT reduces power consumption. The 2D DCT is performed on 8x8 matrix using two 1-Dimensional Discrete cosine transform blocks and a transposition memory [7]. Inverse discrete cosine transform (IDCT) is performed to obtain the image matrix and reconstruct the original image. The proposed image compression algorithm is comprehended using MATLAB code. The VLSI design of the architecture is implemented Using Verilog HDL. The proposed hardware architecture for image compression employing DCT was synthesized using RTL complier and it was mapped using 180nm standard cells. . The Simulation is done using Modelsim. The simulation results from MATLAB and Verilog HDL are compared. Detailed analysis for power and area was done using RTL compiler from CADENCE. Power consumption of DCT core is reduced to 1.027mW with minimum area[1].

Keywords: Discrete Cosine Transform (DCT), Inverse DiscreteCosine Transform (IDCT), Joint Photographic Expert Group (JPEG), Low Power Design, Very Large Scale Integration (VLSI) .

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8664 A Novel Digital Calibration Technique for Gain and Offset Mismatch in TIΣΔ ADCs

Authors: Ali Beydoun, Van-Tam Nguyen, Patrick Loumeau

Abstract:

Time interleaved sigma-delta (TIΣΔ) architecture is a potential candidate for high bandwidth analog to digital converters (ADC) which remains a bottleneck for software and cognitive radio receivers. However, the performance of the TIΣΔ architecture is limited by the unavoidable gain and offset mismatches resulting from the manufacturing process. This paper presents a novel digital calibration method to compensate the gain and offset mismatch effect. The proposed method takes advantage of the reconstruction digital signal processing on each channel and requires only few logic components for implementation. The run time calibration is estimated to 10 and 15 clock cycles for offset cancellation and gain mismatch calibration respectively.

Keywords: sigma-delta, calibration, gain and offset mismatches, analog-to-digital conversion, time-interleaving.

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8663 Design of Direct Power Controller for a High Power Neutral Point Clamped Converter Using Real Time Simulator

Authors: Amin Zabihinejad, Philippe Viarouge

Abstract:

In this paper, a direct power control (DPC) strategies have been investigated in order to control a high power AC/DC converter with time variable load. This converter is composed of a three level three phase neutral point clamped (NPC) converter as rectifier and an H-bridge four quadrant current control converter. In the high power application, controller not only must adjust the desire outputs but also decrease the level of distortions which are injected to the network from the converter. Regarding to this reason and nonlinearity of the power electronic converter, the conventional controllers cannot achieve appropriate responses. In this research, the precise mathematical analysis has been employed to design the appropriate controller in order to control the time variable load. A DPC controller has been proposed and simulated using Matlab/ Simulink. In order to verify the simulation result, a real time simulator- OPAL-RT- has been employed. In this paper, the dynamic response and stability of the high power NPC with variable load has been investigated and compared with conventional types using a real time simulator. The results proved that the DPC controller is more stable and has more precise outputs in comparison with conventional controller.

Keywords: Direct Power Control, Three Level Rectifier, Real Time Simulator, High Power Application.

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8662 Hardware Implementation of Local Binary Pattern Based Two-Bit Transform Motion Estimation

Authors: Seda Yavuz, Anıl Çelebi, Aysun Taşyapı Çelebi, Oğuzhan Urhan

Abstract:

Nowadays, demand for using real-time video transmission capable devices is ever-increasing. So, high resolution videos have made efficient video compression techniques an essential component for capturing and transmitting video data. Motion estimation has a critical role in encoding raw video. Hence, various motion estimation methods are introduced to efficiently compress the video. Low bit‑depth representation based motion estimation methods facilitate computation of matching criteria and thus, provide small hardware footprint. In this paper, a hardware implementation of a two-bit transformation based low-complexity motion estimation method using local binary pattern approach is proposed. Image frames are represented in two-bit depth instead of full-depth by making use of the local binary pattern as a binarization approach and the binarization part of the hardware architecture is explained in detail. Experimental results demonstrate the difference between the proposed hardware architecture and the architectures of well-known low-complexity motion estimation methods in terms of important aspects such as resource utilization, energy and power consumption.

Keywords: Binarization, hardware architecture, local binary pattern, motion estimation, two-bit transform.

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8661 WPRiMA Tool: Managing Risks in Web Projects

Authors: Thamer Al-Rousan, Shahida Sulaiman, Rosalina Abdul Salam

Abstract:

Risk management is an essential fraction of project management, which plays a significant role in project success. Many failures associated with Web projects are the consequences of poor awareness of the risks involved and lack of process models that can serve as a guideline for the development of Web based applications. To circumvent this problem, contemporary process models have been devised for the development of conventional software. This paper introduces the WPRiMA (Web Project Risk Management Assessment) as the tool, which is used to implement RIAP, the risk identification architecture pattern model, which focuses upon the data from the proprietor-s and vendor-s perspectives. The paper also illustrates how WPRiMA tool works and how it can be used to calculate the risk level for a given Web project, to generate recommendations in order to facilitate risk avoidance in a project, and to improve the prospects of early risk management.

Keywords: Architecture pattern model, risk factors, risk identification, web project, web project risk management assessment.

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8660 Working Motivation Factors Affecting Job Performance Effectiveness

Authors: Supattra Kanchanopast

Abstract:

The purpose of this paper was to study motivation factors affecting job performance effectiveness. This paper drew upon data collected from an Internal Audit Staffs of Internal Audit Line of Head Office of Krung Thai Public Company Limited. Statistics used included frequency, percentage, mean and standard deviation, t-test, and one-way ANOVA test. The finding revealed that the majority of the respondents were female of 46 years of age and over, married and live together, hold a bachelor degree, with an average monthly income over 70,001 Baht. The majority of respondents had over 15 years of work experience. They generally had high working motivation as well as high job performance effectiveness. The hypotheses testing disclosed that employees with different working status had different level of job performance effectiveness at a 0.01 level of significance. Working motivation factors had an effect on job performance in the same direction with high level. Individual working motivation included working completion, reorganization, working progression, working characteristic, opportunity, responsibility, management policy, supervision, relationship with their superior, relationship with co-worker, working position, working stability, safety, privacy, working conditions, and payment. All of these factors related to job performance effectiveness in the same direction with medium level.

Keywords: Internal Audit Staffs, Job Performance Effectiveness, Working Motivation.

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8659 Daylightophil Approach towards High-Performance Architecture for Hybrid-Optimization of Visual Comfort and Daylight Factor in BSk

Authors: Mohammadjavad Mahdavinejad, Hadi Yazdi

Abstract:

The greatest influence we have from the world is shaped through the visual form, thus light is an inseparable element in human life. The use of daylight in visual perception and environment readability is an important issue for users. With regard to the hazards of greenhouse gas emissions from fossil fuels, and in line with the attitudes on the reduction of energy consumption, the correct use of daylight results in lower levels of energy consumed by artificial lighting, heating and cooling systems. Windows are usually the starting points for analysis and simulations to achieve visual comfort and energy optimization; therefore, attention should be paid to the orientation of buildings to minimize electrical energy and maximize the use of daylight. In this paper, by using the Design Builder Software, the effect of the orientation of an 18m2(3m*6m) room with 3m height in city of Tehran has been investigated considering the design constraint limitations. In these simulations, the dimensions of the building have been changed with one degree and the window is located on the smaller face (3m*3m) of the building with 80% ratio. The results indicate that the orientation of building has a lot to do with energy efficiency to meet high-performance architecture and planning goals and objectives.

Keywords: Daylight, window, orientation, energy consumption, design builder.

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