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A Novel VLSI Architecture for Image Compression Model Using Low power Discrete Cosine Transform

Authors: Vijaya Prakash.A.M, K.S.Gurumurthy

Abstract:

In Image processing the Image compression can improve the performance of the digital systems by reducing the cost and time in image storage and transmission without significant reduction of the Image quality. This paper describes hardware architecture of low complexity Discrete Cosine Transform (DCT) architecture for image compression[6]. In this DCT architecture, common computations are identified and shared to remove redundant computations in DCT matrix operation. Vector processing is a method used for implementation of DCT. This reduction in computational complexity of 2D DCT reduces power consumption. The 2D DCT is performed on 8x8 matrix using two 1-Dimensional Discrete cosine transform blocks and a transposition memory [7]. Inverse discrete cosine transform (IDCT) is performed to obtain the image matrix and reconstruct the original image. The proposed image compression algorithm is comprehended using MATLAB code. The VLSI design of the architecture is implemented Using Verilog HDL. The proposed hardware architecture for image compression employing DCT was synthesized using RTL complier and it was mapped using 180nm standard cells. . The Simulation is done using Modelsim. The simulation results from MATLAB and Verilog HDL are compared. Detailed analysis for power and area was done using RTL compiler from CADENCE. Power consumption of DCT core is reduced to 1.027mW with minimum area[1].

Keywords: Low Power Design, Discrete Cosine Transform (DCT), Inverse DiscreteCosine Transform (IDCT), Joint Photographic Expert Group (JPEG), Very Large Scale Integration (VLSI)

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1062934

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References:


[1] Jongsun Park Kaushik Roy A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption Received: 2 April 2007 / Revised: 16 January 2008 / Accepted: 30 April 2008 / Published online: 3 June 2008.
[2] S. Ramachandran And S. Srinivasan Department of Electrical Engineering A Novel, Automatic Quality Control Scheme for Real
[3] Sungwook Yu and Earl E. Swartzlander Jr., Fellow, IEEE, DCT Implementation with Distributed Arithmetic, IEEE Transactions on Computers, VOL. 50, NO. 9, September 2001.
[4] B. Heyne and J. Goetz A low-power and high-quality implementation of the discrete cosine transformation,Adv. Radio Sci., 5, 305311, 2007.
[5] Y.P Lee, A cost effective architecture for 8x8 two-dimensional DCT/IDCT using direct method IEEE Transactions on circuit and system for video technology vol 7 N0 3 June 1997.
[6] C. Hemasundara Rao and M. Madavi Latha A Novel VLSI Architecture of Hybrid Image Compression Model based on Reversible Blockade Transform. .
[7] Sherif T.EID Shams University Cairo. A Low Power 1-D DCT/IDCT Core. 1999-Y2k.
[8] Ken Cabeen and Peter Gent Math 45 College of the Redwoods Image Compression and Discrete Cosine Transform.
[9] Andrew B.Watson,Image compression using the discrete cosine transform, Mathematical Journal, 4(1), 1994, p, 81-88.
[10] VijayaPrakash and K.S.Gurumurthy.A Novel VLSI Architecture for Digital Image Compression UsingDiscrete Cosine Transform and Quantization IJCSNS September 2010.
[11] Syed Ali Khayam, The Discrete Cosine Transform (DCT): Theory and Application. ECE 802 602: Information Theory and Coding, March 10th 2003.
[12] Xanthopoulos .T and Chandrakasan A P. A Low Powr DCT core using Adaptive Bitwidth and arithmetic Activity exploiting signals correlations and Quantization. IEEE journals of solid state circuits 35(5) 740-750 may 2000.