Search results for: Chip technology

Authors: K. Sivasubramanian, K. B. Jayanthi

Abstract:

Floorplanning plays a vital role in the physical design process of Very Large Scale Integrated (VLSI) chips. It is an essential design step to estimate the chip area prior to the optimized placement of digital blocks and their interconnections. Since VLSI floorplanning is an NP-hard problem, many optimization techniques were adopted in the literature. In this work, a music-inspired Harmony Search (HS) algorithm is used for the fixed die outline constrained floorplanning, with the aim of reducing the total chip area. HS draws inspiration from the musical improvisation process of searching for a perfect state of harmony. Initially, B*-tree is used to generate the primary floorplan for the given rectangular hard modules and then HS algorithm is applied to obtain an optimal solution for the efficient floorplan. The experimental results of the HS algorithm are obtained for the MCNC benchmark circuits.

Keywords: Floor planning, harmony search, non-slicing floorplan, very large scale integrated circuits.

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Authors: Zia Abbas, Giuseppe Scotti, Mauro Olivieri

Abstract:

Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-terminal intrinsic resistance via a bias current is possible. The presented approach is based on the CMOS implementation of second generation positive (CCCII+), negative (CCCII-) and dual Output Current Controlled Conveyor (DOCCCII) and its application as Universal filter. All the circuits have been designed and simulated using 65nm CMOS technology model parameters on Cadence Virtuoso / Spectre using 1V supply voltage. Various simulations have been carried out to verify the linearity between output and input ports, range of operation frequency, etc. The outcomes show good agreement between expected and experimental results.

Keywords: CCCII+, CCCII-, DOCCCII, Electronic tunability, Universal filter

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Authors: Eva Ungure, Sandra Muizniece-Brasava, Lija Dukalska, Vita Levkane

Abstract:

The objective of the research was to evaluate the quality of milk pomade sweet – sherbet packed in different packaging materials (Multibarrier 60, met.BOPET/PE, Aluthen), by several packaging technologies – active and modified atmosphere (MAP) (consisting of 100% CO2), and control – in air ambiance. Experiments were carried out at the Faculty of Food Technology of Latvia University of Agriculture. Samples were stored at the room temperature +21±1 °C. The physiochemical properties – weight losses, moisture, hardening, colour and changes in headspace atmosphere concentration (CO2 and O2) of packs were analysed before packaging and after 2, 4, 6, 8, 10 and 12 storage weeks.

Keywords: packaging, shelf life, sherbet with crunchy peanut chip's

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Authors: Seung-Mok Han, Woo-Jin Nam, Seongsoo Lee

Abstract:

This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from 4×4 to 16×16 blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a 16×16 block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.

Keywords: HEVC, Core transform, Low area, Shift-and-add, PE reuse

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Authors: M. Bakhouya, S. A. Bahra, T. El-Ghazawi

Abstract:

The Partitioned Global Address Space (PGAS) programming paradigm offers ease-of-use in expressing parallelism through a global shared address space while emphasizing performance by providing locality awareness through the partitioning of this address space. Therefore, the interest in PGAS programming languages is growing and many new languages have emerged and are becoming ubiquitously available on nearly all modern parallel architectures. Recently, new parallel machines with multiple cores are designed for targeting high performance applications. Most of the efforts have gone into benchmarking but there are a few examples of real high performance applications running on multicore machines. In this paper, we present and evaluate a parallelization technique for implementing a local DNA sequence alignment algorithm using a PGAS based language, UPC (Unified Parallel C) on a chip multithreading architecture, the UltraSPARC T1.

Keywords: Partitioned Global Address Space, Unified Parallel C, Multicore machines, Multi-threading Architecture, Sequence alignment.

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Authors: Guowei Hou, Lixin Yu, Wei Zhuang, Hui Qin, Xue Yang

Abstract:

Formal verification is proposed to ensure the correctness of the design and make functional verification more efficient. As cache plays a vital role in the design of System on Chip (SoC), and cache with Memory Management Unit (MMU) and cache memory unit makes the state space too large for simulation to verify, then a formal verification is presented for such system design. In the paper, a formal model checking verification flow is suggested and a new cache memory model which is called “exhaustive search model” is proposed. Instead of using large size ram to denote the whole cache memory, exhaustive search model employs just two cache blocks. For cache system contains data cache (Dcache) and instruction cache (Icache), Dcache memory model and Icache memory model are established separately using the same mechanism. At last, the novel model is employed to the verification of a cache which is module of a custom-built SoC system that has been applied in practical, and the result shows that the cache system is verified correctly using the exhaustive search model, and it makes the verification much more manageable and flexible.

Keywords: Cache system, formal verification, novel model, System on Chip (SoC).

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Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath

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This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

Keywords: CMOS, VLSI, Oscilloscope, Field Programmable Gate Array (FPGA), VHDL, Video Graphics Array (VGA)

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Authors: T.C.Manjunath, Ph.D., Ashok Kusagur, Shruthi Sanjay, Saritha Sindushree, C. Ardil

Abstract:

This paper deals with the design, development & implementation of a temperature sensor using zigbee. The main aim of the work undertaken in this paper is to sense the temperature and to display the result on the LCD using the zigbee technology. ZigBee operates in the industrial, scientific and medical (ISM) radio bands; 868 MHz in Europe, 915 MHz in the USA and 2.4 GHz in most jurisdictions worldwide. The technology is intended to be simpler and cheaper than other WPANs such as Bluetooth. The most capable ZigBee node type is said to require only about 10 % of the software of a typical Bluetooth or Wireless Internet node, while the simplest nodes are about 2 %. However, actual code sizes are much higher, more like 50 % of the Bluetooth code size. ZigBee chip vendors have announced 128-kilobyte devices. In this work undertaken in the design & development of the temperature sensor, it senses the temperature and after amplification is then fed to the micro controller, this is then connected to the zigbee module, which transmits the data and at the other end the zigbee reads the data and displays on to the LCD. The software developed is highly accurate and works at a very high speed. The method developed shows the effectiveness of the scheme employed.

Keywords: Zigbee, Microcontroller, PIC, Transmitter, Receiver, Synchronous, Blue tooth, Communication.

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Authors: Seongykyoon Jeong, Sungki Lee, Jaeyun Kim, Seunghun Oh, Kiho Kwak

Abstract:

The purpose of study is to demonstrate how the characteristics of technology and the process required for development of technology affect technology transfer from public organisations to industry on the technology level. In addition, using the advantage of the analytic level and the novel means of measuring technology convergence, we examine the characteristics of converging technologies as compared to non-converging technologies in technology transfer process. In sum, our study finds that a technology from the public sector is likely to be transferred when its readiness level is closer to generation of profit, when its stage of life cycle is early and when its economic values is high. Our findings also show that converging technologies are less likely to be transferred.

Keywords: Interdisciplinary, Technology transfer, Technology convergence.

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

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This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: Reconfigurable, fast Fourier transform, single-path delay feedback, 3GPP-LTE.

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Authors: Sorore Benabid

Abstract:

The Q-enhanced LC filters are the most used architecture in the Bandpass (BP) Continuous-Time (CT) Delta-Sigma (ΣΔ) modulators, due to their: high frequencies operation, high linearity than the active filters and a high quality factor obtained by Q-enhanced technique. This technique consists of the use of a negative resistance that compensate the ohmic losses in the on-chip inductor. However, this technique introduces a zero in the filter transfer function which will affect the modulator performances in term of Dynamic Range (DR), stability and in-band noise (Signal-to-Noise Ratio (SNR)). In this paper, we study the effect of this zero and we demonstrate that a calibration of the excess loop delay (ELD) is required to ensure the best performances of the modulator. System level simulations are done for a 2ndorder BP CT (ΣΔ) modulator at a center frequency of 300MHz. Simulation results indicate that the optimal ELD should be reduced by 13% to achieve the maximum SNR and DR compared to the ideal LC-based ΣΔ modulator.

Keywords: Continuous-time bandpass delta-sigma modulators, excess loop delay, on-chip inductor, Q-enhanced LC filter.

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Authors: Krzysztof Wawryn, Robert Suszyński, Bogdan Strzeszewski

Abstract:

This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.

Keywords: Pipelined converter, a/d converter, low power, lowvoltage, current mode.

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Authors: Hanane Ondella, Pierre Ladet, David Ferrand, Pat Sloan

Abstract:

In the micro and nano-technology industry, the «clean-rooms» dedicated to manufacturing chip, are equipped with the most sophisticated equipment-tools. There use a large number of resources in according to strict specifications for an optimum working and result. The distribution of «utilities» to the production is assured by teams who use a supervision tool. The studies show the interest to control the various parameters of production or/and distribution, in real time, through a reliable and effective supervision tool. This document looks at a large part of the functions that the supervisor must assure, with complementary functionalities to help the diagnosis and simulation that prove very useful in our case where the supervised installations are complexed and in constant evolution.

Keywords: Control-Command, evolution, non regression, performances, real time, simulation, supervision.

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Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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Authors: S. Karabulut, A. Güllü, A. Güldas, R. Gürbüz

Abstract:

This study investigates the effects of the lead angle and chip thickness variation on surface roughness during the machining of compacted graphite iron using ceramic cutting tools under dry cutting conditions. Analytical models were developed for predicting the surface roughness values of the specimens after the face milling process. Experimental data was collected and imported to the artificial neural network model. A multilayer perceptron model was used with the back propagation algorithm employing the input parameters of lead angle, cutting speed and feed rate in connection with chip thickness. Furthermore, analysis of variance was employed to determine the effects of the cutting parameters on surface roughness. Artificial neural network and regression analysis were used to predict surface roughness. The values thus predicted were compared with the collected experimental data, and the corresponding percentage error was computed. Analysis results revealed that the lead angle is the dominant factor affecting surface roughness. Experimental results indicated an improvement in the surface roughness value with decreasing lead angle value from 88° to 45°.

Keywords: CGI, milling, surface roughness, ANN, regression, modeling, analysis.

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Authors: Seongykyoon Jeong, Sungki Lee, Jaeyun Kim, Seunghun Oh, Kiho Kwak

Abstract:

The purpose of this article is to identify the practical strategies of R&D (research and development) entities for developing converging technology in organizational context. Based on the multi-assignation technological domains of patents derived from entire government-supported R&D projects for 13 years, we find that technology convergence is likely to occur when a university solely develops technology or when university develops technology as one of the collaborators. These results reflect the important role of universities in developing converging technology

Keywords: Interdisciplinary, Research and development strategy, Technology convergence

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Authors: P. P. S. Sifolo, M. J. Maimela M. P. Tladi

Abstract:

This article investigates technology used by Tshwane residents intended for tourism purposes. The aim is to contribute information for planning and management concerning technology within the tourism sector in the city of Tshwane, South Africa. This study identified the types of tourist related technologies used by the Tshwane residents, be it for business purposes or personal use. The study connected the exploitation of technology for tourism purposes through unpacking the tourism sector as it utilizes technology. Quantitative research methodology was used whereby self-completed questionnaires were chosen as research instruments. The research study carried out a search for knowledge on technology for tourism and the Tshwane residents; however the study revealed that technology has certainly imprinted tourism massively because of its effectiveness and efficiency. Technology has assisted tourism businesses stay abreast of competition with integrated communication technology (ICT) and because of that, SA is on the map as one of the economically performing countries in Africa. Moreover, technology and tourism make a meaningful impact on job creation and Gross Domestic Product (GDP).

Keywords: Information and Communication Technology, Technology for tourism, Tshwane residents.

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Authors: L.Tahmooresnejad, M.A.Shafia, R.Salami

Abstract:

Technology transfer is a common method for companies to acquire new technology and presents both challenges and substantial benefits. In some cases especially in developing countries, the mere possession of technology does not guarantee a competitive advantage if the appropriate infrastructure is not in place. In this paper, we identify the localization factors needed to provide a better understanding of the conditions necessary for localization in order to benefit from future technology developments. Our theoretical and empirical analyses allow us to identify several factors in the technology transfer process that affect localization and provide leverage in enhancing capabilities and absorptive capacity.The impact factors are categorized within different groups of government, firms, institutes and market, and are verified through the empirical survey of a technology transfer experience. Moreover, statistical analysis has allowed a deeper understanding of the importance of each factor and has enabled each group to prioritize their organizational policies to effectively localize their technology.

Keywords: Absorption Capacity, Adaptation, Technology Transfer, Technology Localization

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Authors: Bahram Talebjedi, Emily Earl, Mina Hoorfar

Abstract:

One of the issues that arises with microscale lab-on-a-chip technology is that the laminar flow within the microchannels limits the mixing of fluids. To combat this, micromixers have been introduced as a means to try and incorporate turbulence into the flow to better aid the mixing process. This study presents an electroosmotic micromixer that balances vortex generation and degeneration with the inlet flow velocity to greatly increase the mixing efficiency. A comprehensive parametric study was performed to evaluate the role of the relevant parameters on the mixing efficiency. It was observed that the suggested micromixer is perfectly suited for biological applications due to its low pressure drop (below 10 Pa) and low shear rate. The proposed micromixer with optimized working parameters is able to attain a mixing efficiency of 95% in a span of 0.5 seconds using a frequency of 10 Hz, a voltage of 0.7 V, and an inlet velocity of 0.366 mm/s.

Keywords: Microfluidics, active mixer, pulsed AC electroosmosis flow, micromixer.

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Authors: Daekook Kang, Wooseok Jang, Hyeonjeong Lee, Hyun Joung No

Abstract:

Technology changes have been acknowledged as a critical factor in determining competitiveness of organization. Under such environment, the right anticipation of technology change has been of huge importance in strategic planning. To monitor technology change, technology forecasting (TF) is frequently utilized. In academic perspective, TF has received great attention for a long time. However, few researches have been conducted to provide overview of the TF literature. Even though some studies deals with review of TF research, they generally focused on type and characteristics of various TF, so hardly provides information about patterns of TF research and which TF method is used in certain technology industry. Accordingly, this study profile developments in and patterns of scholarly research in TF over time. Also, this study investigates which technology industries have used certain TF method and identifies their relationships. This study will help in understanding TF research trend and their application area.

Keywords: Technology forecasting, technology industry, TF trend, technology trajectory.

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Authors: Virendra J. Majarikar, Harikrishnan N. Unni

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This paper sets to demonstrate a modeling of electrokinetic mixing employing electroosmotic stationary and time-dependent microchannel using alternate zeta patches on the lower surface of the micromixer in a lab on chip microfluidic device. Electroosmotic flow is amplified using different 2D and 3D model designs with alternate and geometric zeta potential values such as 25, 50, and 100 mV, respectively, to achieve high concentration mixing in the electrokinetically-driven microfluidic system. The enhancement of electrokinetic mixing is studied using Finite Element Modeling, and simulation workflow is accomplished with defined integral steps. It can be observed that the presence of alternate zeta patches can help inducing microvortex flows inside the channel, which in turn can improve mixing efficiency. Fluid flow and concentration fields are simulated by solving Navier-Stokes equation (implying Helmholtz-Smoluchowski slip velocity boundary condition) and Convection-Diffusion equation. The effect of the magnitude of zeta potential, the number of alternate zeta patches, etc. are analysed thoroughly. 2D simulation reveals that there is a cumulative increase in concentration mixing, whereas 3D simulation differs slightly with low zeta potential as that of the 2D model within the T-shaped micromixer for concentration 1 mol/m³ and 0 mol/m³, respectively. Moreover, 2D model results were compared with those of 3D to indicate the importance of the 3D model in a microfluidic design process.

Keywords: COMSOL, electrokinetic, electroosmotic, microfluidics, zeta potential.

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Authors: B. Kiyani, R. H. Amiri, S. H. Hosseini, A. Bourouni, A. Karimi

Abstract:

Nowadays, offshore's complicated facilities need their own communications requirements. Nevertheless, developing and real-world applications of new communications technology are faced with tremendous problems for new technology users, developers and implementers. Traditional systems engineering cannot be capable to develop a new technology effectively because it does not consider the dynamics of the process. This paper focuses on the design of a holistic model that represents the dynamics of new communication technology development within offshore industry. The model shows the behavior of technology development efforts. Furthermore, implementing this model, results in new and useful insights about the policy option analysis for developing a new communications technology in offshore industry.

Keywords: Technology development, Offshore industry, Systemdynamics, Voice Over IP.

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Authors: Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng

Abstract:

A digital baseband Application-Specific Integrated Circuit (ASIC) (yclic Redundancy Checkis developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm² in chip area (digital baseband: 0.060 mm², decimation filter: 0.056 mm²), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).

Keywords: Biomedical sensor, decimation filter, Radio Frequency Integrated Circuit (RFIC) baseband, temperature sensor.

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Authors: Jeeeun Kim, Sungjoo Lee

Abstract:

This research proposes a methodology for patent-citation-based technology input-output analysis by applying the patent information to input-output analysis developed for the dependencies among different industries. For this analysis, a technology relationship matrix and its components, as well as input and technology inducement coefficients, are constructed using patent information. Then, a technology inducement coefficient is calculated by normalizing the degree of citation from certain IPCs to the different IPCs (International patent classification) or to the same IPCs. Finally, we construct a Dependency Structure Matrix (DSM) based on the technology inducement coefficient to suggest a useful application for this methodology.

Keywords: Technology spillover effect, technology relationship, IO table, technology inducement coefficients, patent analysis, patent citation.

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Authors: E. V. Veraszto, J. T. F. Camargo, D. Silva, N. A. Miranda, F. O. Simon, S. F. Amaral, L. V. Freitas

Abstract:

The concept of technology as well as itself has evolved continuously over time, such that, nowadays, this concept is still marked by myths and realities. Even the concept of science is frequently misunderstood as technology. In this way, this paper presents different forms of interpretation of the concept of technology in the course of history, as well as the social and cultural aspects associated with it, through an analysis made by means of insights from sociological studies of science and technology and its multiple relations with society. Through the analysis of contents, the paper presents a classification of how technology is interpreted in the social sphere and search channel efforts to show how a broader understanding can contribute to better interpretations of how scientific and technological development influences the environment in which we operate. The text also presents a particular point of view for the interpretation of the concept from the analysis throughout the whole work.

Keywords: Technology, conceptions of technology, technological myths, definition of technology.

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Authors: José Carlos Rodríguez, Mario Gómez

Abstract:

The aim of this paper is to get insight on the nature of university-industry technology transfer (UITT) and technology transfer offices (TTOs) activity at universities in the case of emerging economies. In relation to the process of transferring knowledge/technology in the case of emerging economies, knowledge/technology transfer in these economies are more reactive than in developed economies due to differences in maturity of technologies. It is assumed in this paper that knowledge/technology transfer is a complex phenomenon, and thus the paper contributes to get insight on the nature of UITT and TTOs creation in the case of emerging economies by using a system dynamics model of knowledge/technology transfer in these countries. The paper recognizes the differences between industrialized countries and emerging economies on these phenomena.

Keywords: University-industry technology transfer, technology transfer offices, technology transfer models, emerging economies.

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Authors: Gizem Intepe, Tufan Koc

Abstract:

S-Curves are commonly used in technology forecasting. They show the paths of product performance in relation to time or investment in R&D. It is a useful tool to describe the inflection points and the limit of improvement of a technology. Companies use this information to base their innovation strategies. However inadequate use and some limitations of this technique lead to problems in decision making. In this paper first technology forecasting and its importance for company level strategies will be discussed. Secondly the S-Curve and its place among other forecasting techniques will be introduced. Thirdly its use in technology forecasting will be discussed based on its advantages, disadvantages and limitations. Finally an application of S-curve on 3D TV technology using patent data will also be presented and the results will be discussed.

Keywords: Patent analysis, Technological forecasting. S curves, 3D TV

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Authors: Sadi Vural, Hiromi Tomii, Hironori Yamauchi

Abstract:

As the development of digital technology is increasing, Digital cinema is getting more spread. However, content copy and attack against the digital cinema becomes a serious problem. To solve the above security problem, we propose “Additional Watermarking" for digital cinema delivery system. With this proposed “Additional watermarking" method, we protect content copyrights at encoder and user side information at decoder. It realizes the traceability of the watermark embedded at encoder. The watermark is embedded into the random-selected frames using Hash function. Using it, the embedding position is distributed by Hash Function so that third parties do not break off the watermarking algorithm. Finally, our experimental results show that proposed method is much better than the convenient watermarking techniques in terms of robustness, image quality and its simple but unbreakable algorithm.

Keywords: Decoder, Digital content, JPEG2000 Frame, System-On-Chip and additional watermark.

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Authors: Sadi Vural, Hiromi Tomii, Hironori Yamauchi

Abstract:

As far as the latest technological improvements are concerned, digital systems more become popular than the past. Despite this growing demand to the digital systems, content copy and attack against the digital cinema contents becomes a serious problem. To solve the above security problem, we propose “traceable watermarking using Hash functions for digital cinema system. Digital Cinema is a great application for traceable watermarking since it uses watermarking technology during content play as well as content transmission. The watermark is embedded into the randomly selected movie frames using CRC-32 techniques. CRC-32 is a Hash function. Using it, the embedding position is distributed by Hash Function so that any party cannot break off the watermarking or will not be able to change. Finally, our experimental results show that proposed DWT watermarking method using CRC-32 is much better than the convenient watermarking techniques in terms of robustness, image quality and its simple but unbreakable algorithm.

Keywords: Decoder, Digital content, JPEG2000 Frame, System-On-Chip, traceable watermark, Hash Function, CRC-32.

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Authors: G. Schuh, S. Aghassi

Abstract:

In order to bridge the gap between research and industry, promoting technology and knowledge transfer becomes increasingly important. Especially small- and medium-sized enterprises, having only little R&D resources themselves, depend on external technology development activities for remaining innovative. Academia research on the other hand needs potential industrial partners, who are capable and willing to commercialize their technologies as most public funding programs require some sort of technology transfer or dissemination activities. Modern web technologies offer more and more “social” functionalities and open up new ways of user interaction. In the past years several technology transfer platforms were developed, making use of modern web technologies in order to enable and support technology transfer. In this paper we report on the results of a state-of-the art analyses of existing technology transfer platforms, point out their advantages and deficits and give a perspective to the development of an improved technology transfer platform.

Keywords: Knowledge transfer, social software, technology management, technology transfer.

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