Search results for: power factor correction stage Regulation stage

Authors: B. Sathyanandhi, P. M. Balasubramaniam

Abstract:

This paper presents Buck-Boost converter topology to maintain the input power factor by using the power factor stage control and regulation stage control. Suppose, if we are using the RL load the power factor will be reduced due to the presence of total harmonic distortion in the current wave. To improve the power factor the current waveform should follow the fundamental component of the voltage waveform. These can be achieved by using the high -frequency power converter. Based on the resonant circuit the converter is able to perform the function of Buck, Boost, and buck-boost converter. Here ,we have used Buck-Boost converter, because, the buck-boost converter has more advantages than the boost converter. Here the switching action of the power converter can  take place by using the external zero comparator PFC stage control. The power converter consisting of the resonant  circuit which is used to control the output voltage gain of the converter. The power converter is operated at a very high switching frequency in the range of 400KHz in order to overcome the switching losses of the power converter. Due to  presence of high switching frequency, the power factor will improve. Therefore, the total harmonics distortion present in the current waveform has also reduced. These results has generated in the form of simulation by using MATLAB/SIMULINK software.  Similar to the Buck and Boost converters, the operation of the Buck-Boost has best understood, in terms of the inductor's "reluctance" for allowing rapid change in current, which also reduces the Total Harmonic Distortion (THD) in the input current waveform, which can improve the input Power factor, based on the type of load used.

Keywords: Buck-boost converter, High switching frequency, Power factor correction, power factor correction stage Regulation stage, Total harmonic distortion (THD).

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Authors: S. Saisundar, Shan Jiang, Kevin T. C. Chai, David Nuttman, Minkyu Je

Abstract:

Keywords: Analog to digital converter, cyclic, gain-boosting, pipelined.

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Authors: Renbin Dai, Rana Arslan Ali Khan

Abstract:

The design of Class A and Class AB 2-stage X band Power Amplifier is described in this report. This power amplifier is part of a transceiver used in radar for monitoring iron characteristics in a blast furnace. The circuit was designed using foundry WIN Semiconductors. The specification requires 15dB gain in the linear region, VSWR nearly 1 at input as well as at the output, an output power of 10 dBm and good stable performance in the band 10.9-12.2 GHz. The design was implemented by using inter-stage configuration, the Class A amplifier was chosen for driver stage i.e. the first amplifier focusing on the gain and the output amplifier conducted at Class AB with more emphasis on output power.

Keywords: Power amplifier, Class AB, Class A, MMIC, 2-stage, X band.

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Authors: Yakup Sahin, Naim Suleyman Ting, Ismail Aksoy

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A 1 kW power factor correction boost converter with an active snubber cell is presented in this paper. In the converter, the main switch turns on under zero voltage transition (ZVT) and turns off under zero current transition (ZCT) without any additional voltage or current stress. The auxiliary switch turns on and off under zero current switching (ZCS). Besides, the main diode turns on under ZVS and turns off under ZCS. The output current and voltage are controlled by the PFC converter in wide line and load range. The simulation results of converter are obtained for 1 kW and 100 kHz. One of the most important feature of the given converter is that it has direct power transfer as well as excellent soft switching techniques. Also, the converter has 0.99 power factor with the sinusoidal input current shape.

Keywords: Power factor correction, direct power transfer, zero-voltage transition, zero-current transition, soft switching.

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Authors: A. Inba Rexy, R. Seyezhai

Abstract:

Through the fast growing technologies, design of power factor correction (PFC) circuit is facing several challenges. In this paper, a two-phase interleaved boost converter with ripple steering technique is proposed. Among the various topologies, Interleaved Boost converter (IBC) is considered as superior due to enriched performance, lower ripple content, compact weight and size. A thorough investigation is presented here for the proposed topology. Simulation study for the IBC has been carried out using MATLAB/SIMULINK. Theoretical analysis and hardware prototype has been performed to validate the results.

Keywords: Interleaved Boost Converter (IBC), Power Factor Correction (PFC), Ripple Steering Technique, Ripple, and Simulation.

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Authors: M. Nirmala

Abstract:

Power quality in terms of power factor, THD and precisely regulated output voltage are the major key factors for efficient operation of power electronic converters. This paper presents an easy and effective active wave shaping control scheme for the pulsed input current drawn by the uncontrolled diode bridge rectifier thereby achieving power factor nearer to unity and also satisfying the THD specifications. It also regulates the output DC-bus voltage. CCM boost power factor correction with constant frequency operation features smaller inductor current ripple resulting in low RMS currents on inductor and switch thus leading to low electromagnetic interference. The objective of this work is to develop an active PFC control circuit using CCM boost converter implementing variable duty cycle control. The proposed scheme eliminates inductor current sensing requirements yet offering good performance and satisfactory results for maintaining the power quality. Simulation results have been presented which covers load changes also.

Keywords: CCM Boost converter, Power factor Correction, Total harmonic distortion, Variable Duty Cycle.

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Authors: P. Ram Mohan, M. Vijaya Kumar, O. V. Raghava Reddy

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This paper deals with the simulation of a Boost Power Factor Correction (PFC) Converter with Electro Magnetic Interference (EMI) Filter. The diode rectifier with output capacitor gives poor power factor. The Boost Converter of PFC Circuit is analyzed and then simulated with diode rectifier. The Boost PFC Converter with EMI Filter is simulated for resistive load. The power factor is improved using the proposed converter.

Keywords: Boost Converter, Power Factor Correction, Electro Magnetic Interference, Diode Rectifier

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Authors: Yakup Sahin, Naim Suleyman Ting, Ismail Aksoy

Abstract:

In this paper, a single phase soft switched Zero Voltage Transition and Zero Current Transition (ZVT-ZCT) Power Factor Correction (PFC) boost converter is proposed. In the proposed PFC converter, the main switch turns on with ZVT and turns off with ZCT without any additional voltage or current stresses. Auxiliary switch turns on and off with zero current switching (ZCS). Also, the main diode turns on with zero voltage switching (ZVS) and turns off with ZCS. The proposed converter has features like low cost, simple control and structure. The output current and voltage are controlled by the proposed PFC converter in wide line and load range. The theoretical analysis of converter is clarified and the operating steps are given in detail. The simulation results of converter are obtained for 500 W and 100 kHz. It is observed that the semiconductor devices operate with soft switching (SS) perfectly. So, the switching power losses are minimum. Also, the proposed converter has 0.99 power factor with sinusoidal current shape.

Keywords: Power factor correction, zero-voltage transition, zero-current transition, soft switching.

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Authors: P. Prasad Rao, K. Lal Kishore

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Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18

Keywords: 1.5 bits/stage, Conversion Frequency, Redundancy Switched Capacitor Sample and Hold Circuit

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Authors: Jetsada Arnin, Yodchanan Wongsawat

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One of the most important causes of accidents is driver fatigue. To reduce the accidental rate, the driver needs a quick nap when feeling sleepy. Hence, searching for the minimum time period of nap is a very challenging problem. The purpose of this paper is twofold, i.e. to investigate the possible fastest time period for nap and its relationship with stage 2 sleep, and to develop an automatic stage 2 sleep detection and alarm device. The experiment for this investigation is designed with 21 subjects. It yields the result that waking up the subjects after getting into stage 2 sleep for 3-5 minutes can efficiently reduce the sleepiness. Furthermore, the automatic stage 2 sleep detection and alarm device yields the real-time detection accuracy of approximately 85% which is comparable with the commercial sleep lab system.

Keywords: Stage 2 sleep, nap, sleep detection, real-time, EEG

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Authors: S.K.Ayyaswamy, S.Balachandran, K.Kannan

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Let G be a graph of order n. The second stage adjacency matrix of G is the symmetric n × n matrix for which the ijth entry is 1 if the vertices vi and vj are of distance two; otherwise 0. The sum of the absolute values of this second stage adjacency matrix is called the second stage energy of G. In this paper we investigate a few properties and determine some upper bounds for the largest eigenvalue.

Keywords: Second stage spectral radius, Irreducible matrix, Derived graph

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Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao

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A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.

Keywords: Bridgeless boost, boost converter, power factor correction, hold-up time.

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Authors: Sanjay L. Kurkute, Pradeep M. Patil, Kakasaheb C. Mohite

Abstract:

An optimal control strategy based on simple model, a single phase unity power factor boost converter is presented with an evaluation of first order differential equations. This paper presents an evaluation of single phase boost converter having power factor correction. The simple discrete model of boost converter is formed and optimal control is obtained, digital PI is adopted to adjust control error. The method of instantaneous current control is proposed in this paper for its good tracking performance of dynamic response. The simulation and experimental results verified our design.

Keywords: Single phase, boost converter, Power factor correction (PFC), Pulse Width Modulation (PWM).

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Authors: Shao-lun Zeng, Yu-long Ren

Abstract:

Benchmarking cleaner production performance is an effective way of pollution control and emission reduction in coal-fired power industry. A benchmarking method using two-stage super-efficiency data envelopment analysis for coal-fired power plants is proposed – firstly, to improve the cleaner production performance of DEA-inefficient or weakly DEA-efficient plants, then to select the benchmark from performance-improved power plants. An empirical study is carried out with the survey data of 24 coal-fired power plants. The result shows that in the first stage the performance of 16 plants is DEA-efficient and that of 8 plants is relatively inefficient. The target values for improving DEA-inefficient plants are acquired by projection analysis. The efficient performance of 24 power plants and the benchmarking plant is achieved in the second stage. The two-stage benchmarking method is practical to select the optimal benchmark in the cleaner production of coal-fired power industry and will continuously improve plants- cleaner production performance.

Keywords: benchmarking, cleaner production performance, coal-fired power plant, super-efficiency data envelopment analysis

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Authors: Takayuki Shiina

Abstract:

We consider power system expansion planning under uncertainty. In our approach, integer programming and stochastic programming provide a basic framework. We develop a multistage stochastic programming model in which some of the variables are restricted to integer values. By utilizing the special property of the problem, called block separable recourse, the problem is transformed into a two-stage stochastic program with recourse. The electric power capacity expansion problem is reformulated as the problem with first stage integer variables and continuous second stage variables. The L-shaped algorithm to solve the problem is proposed.

Keywords: electric power capacity expansion problem, integerprogramming, L-shaped method, stochastic programming

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Authors: Nesapriya. P., S. Rajalaxmi

Abstract:

This paper is based on the bridgeless single-phase Ac–Dc Power Factor Correction (PFC) converters with Fuzzy Logic Controller. High frequency isolated Cuk converters are used as a modular dc-dc converter in Discontinuous Conduction Mode (DCM) of operation of Power Factor Correction. The aim of this paper is to simplify the program complexity of the controller by reducing the number of fuzzy sets of the Membership Functions (MFs) and to improve the efficiency and to eliminate the power quality problems. The output of Fuzzy controller is compared with High frequency triangular wave to generate PWM gating signals of Cuk converter. The proposed topologies are designed to work in Discontinuous Conduction Mode (DCM) to achieve a unity power factor and low total harmonic distortion of the input current. The Fuzzy Logic Controller gives additional advantages such as accurate result, uncertainty and imprecision and automatic control circuitry. Performance comparisons between the proposed and conventional controllers and circuits are performed based on circuit simulations.

Keywords: Fuzzy Logic Controller (FLC), Bridgeless rectifier, Cuk converter, Pulse Width Modulation (PWM), Power Factor Correction, Total Harmonic Distortion (THD).

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Authors: Hossein Sahoolizadeh, Alishir Moradi Kordalivand, Zargham Heidari

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In first stage of each microwave receiver there is Low Noise Amplifier (LNA) circuit, and this stage has important rule in quality factor of the receiver. The design of a LNA in Radio Frequency (RF) circuit requires the trade-off many importance characteristics such as gain, Noise Figure (NF), stability, power consumption and complexity. This situation Forces desingners to make choices in the desing of RF circuits. In this paper the aim is to design and simulate a single stage LNA circuit with high gain and low noise using MESFET for frequency range of 5 GHz to 6 GHz. The desing simulation process is down using Advance Design System (ADS). A single stage LNA has successfully designed with 15.83 dB forward gain and 1.26 dB noise figure in frequency of 5.3 GHz. Also the designed LNA should be working stably In a frequency range of 5 GHz to 6 GHz.

Keywords: Advance Design System, Low Noise Amplifier, Radio Frequency, Noise Figure.

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Authors: Kazuyoshi MORI

Abstract:

The two-stage compensator designs of linear system are investigated in the framework of the factorization approach. First, we give “full feedback" two-stage compensator design. Based on this result, various types of the two-stage compensator designs with partial feedbacks are derived.

Keywords: Linear System, Factorization Approach, Two-Stage Compensator Design, Parametrization of Stabilizing Controllers.

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Authors: Arnaud Nougues

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This paper describes a two-stage methodology derived from IMC (Internal Model Control) for tuning a PID (Proportional-Integral-Derivative) controller for levels or other integrating processes in an industrial environment. Focus is ease of use and implementation speed which are critical for an industrial application. Tuning can be done with minimum effort and without the need of time-consuming open-loop step tests on the plant. The first stage of the method applies to levels only: the vessel residence time is calculated from equipment dimensions and used to derive a set of preliminary PI (Proportional-Integral) settings with IMC. The second stage, re-tuning in closed-loop, applies to levels as well as other integrating processes: a tuning correction mechanism has been developed based on a series of closed-loop simulations with model errors. The tuning correction is done from a simple closed-loop step test and application of a generic correlation between observed overshoot and integral time correction. A spin-off of the method is that an estimate of the vessel residence time (levels) or open-loop process gain (other integrating process) is obtained from the closed-loop data.

Keywords: closed-loop model identification, IMC-PID tuning method, integrating process control, on-line PID tuning adaptation

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Authors: Muhaned Zaidi, Ian Grout, Abu Khari bin A’ain

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In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process.

Keywords: Op-amp, rail-to-rail output, Miller compensation, negative Miller capacitance.

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Authors: S. Hu, J. Mortensen, Bernard F. Buxton

Abstract:

A real-time tracking system was built to track performers on an interactive stage. Using an ordinary, up to date, desktop workstation, the performers- silhouette was segmented from the background and parameterized by calculating the normalized central image moments. In the stage system, the silhouette moments were then sent to a parallel workstation, which used them to generate corresponding 3D virtual geometry and projected the generated graphic back onto the stage.

Keywords: Image moment, interactive stage, real-time, silhouette.

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Authors: Abouzar Moshfegh, Mehrzad Shams, Goodarz Ahmadi, Reza Ebrahimi

Abstract:

A 3D simulation study for an incompressible slip flow around a spherical aerosol particle was performed. The full Navier-Stokes equations were solved and the velocity jump at the gas-particle interface was treated numerically by imposition of the slip boundary condition. Analytical solution to the Stokesian slip flow past a spherical particle was used as a benchmark for code verification, and excellent agreement was achieved. The Simulation results showed that in addition to the Knudsen number, the Reynolds number affects the slip correction factor. Thus, the Cunningham-based slip corrections must be augmented by the inclusion of the effect of Reynolds number for application to Lagrangian tracking of fine particles. A new expression for the slip correction factor as a function of both Knudsen number and Reynolds number was developed.

Keywords: CFD, Cunningham correction, Slip correction factor, Spherical aerosol.

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Authors: Mat Syai'in, Adi Soeprijanto

Abstract:

An Optimal Power Flow based on Improved Particle Swarm Optimization (OPF-IPSO) with Generator Capability Curve Constraint is used by NN-OPF as a reference to get pattern of generator scheduling. There are three stages in Designing NN-OPF. The first stage is design of OPF-IPSO with generator capability curve constraint. The second stage is clustering load to specific range and calculating its index. The third stage is training NN-OPF using constructive back propagation method. In training process total load and load index used as input, and pattern of generator scheduling used as output. Data used in this paper is power system of Java-Bali. Software used in this simulation is MATLAB.

Keywords: Optimal Power Flow, Generator Capability Curve, Improved Particle Swarm Optimization, Neural Network

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Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: Pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA.

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Authors: Yogesh Pahariya, Rakesh Saxena, Biswaroop Sarkar

Abstract:

The selection of control strategy depends on the converters of the drive including power, speed, performance and the possible system costs. A number of attempts were therefore made in recent times to develop novel power electronic converter structures for SRM drives, based on the utilization. Many of the converters with variable speed drives have no input power factor correction circuits. This results in harmonic pollution of the utility supply, which should be avoided. The effect of power factor variation in terms of harmonic content is also analyzed in this study. The proposed topologies were simulated using MATLAB / Simulink software package and the results are obtained.

Keywords: Harmonic Pollution, Power Electronic Converter, Power Quality, Simulation.

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Authors: T. Tanitteerapan, E.Thanpo

Abstract:

This paper, a simple continuous conduction mode (CCM) pulse-width-modulated (PWM) controller for high power factor boost converters is introduced. The duty ratios were obtained by the comparison of a sensed signal from inductor current or switch current and a negative slope ramp carrier waveform in each switching period. Due to the proposed control requires only the inductor current or switch current sensor and the output voltage sensor, its circuit implementation was very simple. To verify the proposed control, the circuit experimentation of a 350 W boost converter with the proposed control was applied. From the results, the input current waveform was shaped to be closely sinusoidal, implying high power factor and low harmonics.

Keywords: High power factor converters, boost converters, low harmonic rectifiers, power factor correction, and current control.

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Authors: Suresh Alapati, Sreehari Rao Patri, K. S. R. Krishna Prasad

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Anultra-low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gainenhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 )A. An undershot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 )s for the output voltage undershooting case. The load regulation is of 2.77 )V/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: Capacitor-less LDO, frequency compensation, Transient response, latch, self-biased differential amplifier.

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Authors: S. Ganesh

Abstract:

Power distribution systems typically have tie and sectionalizing switches whose states determine the topological configuration of the network. The aim of network reconfiguration of the distribution network is to minimize the losses for a load arrangement at a particular time. Thus the objective function is to minimize the losses of the network by satisfying the distribution network constraints. The various constraints are radiality, voltage limits and the power balance condition. In this paper the status of the switches is obtained by using Artificial Bee Colony (ABC) algorithm. ABC is based on a particular intelligent behavior of honeybee swarms. ABC is developed based on inspecting the behaviors of real bees to find nectar and sharing the information of food sources to the bees in the hive. The proposed methodology has three stages. In stage one ABC is used to find the tie switches, in stage two the identified tie switches are checked for radiality constraint and if the radilaity constraint is satisfied then the procedure is proceeded to stage three otherwise the process is repeated. In stage three load flow analysis is performed. The process is repeated till the losses are minimized. The ABC is implemented to find the power flow path and the Forward Sweeper algorithm is used to calculate the power flow parameters. The proposed methodology is applied for a 33–bus single feeder distribution network using MATLAB.

Keywords: Artificial Bee Colony (ABC) algorithm, Distribution system, Loss reduction, Network reconfiguration.

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Authors: Bharat B. Gulyani, Anuj Jain, Shalendra Kumar

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Customarily, the LMTD correction factor, FT, is used to screen alternative designs for a heat exchanger. Designs with unacceptably low FT values are discarded. In this paper, authors have proposed a more fundamental criterion, based on feasibility of a multipass exchanger as the only criteria, followed by economic optimization. This criterion, coupled with asymptotic energy targets, provide the complete optimization space in a heat exchanger network (HEN), where cost-optimization of HEN can be performed with only Heat Recovery Approach temperature (HRAT) and number-of-shells as variables.

Keywords: heat exchanger, heat exchanger networks, LMTD correction factor, shell targeting.

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Authors: Yi-Hsiang Pan

Abstract:

The purpose of this study was to develop a “teachers’ self-efficacy scale for high school physical education teachers (TSES-HSPET)” in Taiwan. This scale is based on the self-efficacy theory of Bandura [1], [2]. This study used exploratory and confirmatory factor analyses to test the reliability and validity. The participants were high school physical education teachers in Taiwan. Both stratified random sampling and cluster sampling were used to sample participants for the study. 350 teachers were sampled in the first stage and 234 valid scales (male 133, female 101) returned. During the second stage, 350 teachers were sampled and 257 valid scales (male 143, female 110, 4 did not indicate gender) returned. The exploratory factor analysis was used in the first stage, and it got 60.77% of total variance for construct validity. The Cronbach’s alpha coefficient of internal consistency was 0.91 for sumscale, and subscales were 0.84 and 0.90. In the second stage, confirmatory factor analysis was used to test construct validity. The result showed that the fit index could be accepted (χ2 (75) =167.94, p <.05, RMSEA =0.07, SRMR=0.05, GFI=0.92, NNFI=0.97, CFI=0.98, PNFI=0.79). Average variance extracted of latent variables were 0.43 and 0.53, which composite reliability are 0.78 and 0.90. It is concluded that the TSES-HSPET is a well-considered measurement instrument with acceptable validity and reliability. It may be used to estimate teachers’ self-efficacy for high school physical education teachers.

Keywords: teaching in physical education, teacher's self-efficacy, teacher's belief

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