Search results for: superconducting circuits

Authors: Nassim Ourabia, Malika Ourabia

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A new and efficient method is presented for the analysis of arbitrarily shaped discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions, and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources.

Keywords: CAD analysis, contour integral approach, microwave circuits, s-parameters

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Authors: B. Manikandan, A. Vijayaprabhu

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The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area.

Keywords: DET, QCA, reversible logic gates, POS, SOP, latches, flip flops

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Authors: G. N. Srinivas, K. Raju

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This paper presents Markov processes for determining the reliability indices of distribution system. The continuous Markov modeling is applied to a complex radial distribution system and electrical equivalent circuits are developed for the modeling. In general PSPICE is being used for electrical and electronic circuits and various applications of power system like fault analysis, transient analysis etc. In this paper, the SPICE modeling equivalent circuits which are developed are applied in a novel way to Distribution System reliability analysis. These circuits are simulated using PSPICE software to obtain the state probabilities, the basic and performance indices. Thus the basic indices and the performance indices obtained by this method are compared with those obtained by FMEA technique. The application of the concepts presented in this paper are illustrated and analyzed for IEEE-Roy Billinton Test System (RBTS).

Keywords: distribution system, Markov Model, reliability indices, spice simulation

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Authors: N. Chérif, T. Allaoui, M. Benasla, H. Chaib

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Industrialization and population growth are the prime factors for which the consumption of electricity is steadily increasing. Thus, to have a balance between production and consumption, it is necessary at first to increase the number of power plants, lines and transformers, which implies an increase in cost and environmental degradation. As a result, it is now important to have mesh networks and working close to the limits of stability in order to meet these new requirements. The transient stability studies involve large disturbances such as short circuits, loss of work or production group. The consequence of these defects can be very serious, and can even lead to the complete collapse of the network. This work focuses on the regulation means that networks can help to keep their stability when submitted to strong disturbances. The magnetic energy storage-based superconductor (SMES) comprises a superconducting coil short-circuited on it self. When such a system is connected to a power grid is able to inject or absorb the active and reactive power. This system can be used to improve the stability of power systems.

Keywords: short-circuit, power oscillations, multiband PSS, power system, SMES, transient stability

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Authors: M. Hossain, A. Abdkader, C. Cherif, A. Berger, M. Sparing, R. Hühne, L. Schultz, K. Nielsch

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Due to the best quality of yarn and the flexibility of the machine, the ring spinning process is the most widely used spinning method for short staple yarn production. However, the productivity of these machines is still much lower in comparison to other spinning systems such as rotor or air-jet spinning process. The main reason for this limitation lies on the twisting mechanism of the ring spinning process. In the ring/traveler twisting system, each rotation of the traveler along with the ring inserts twist in the yarn. The rotation of the traveler at higher speed includes strong frictional forces, which in turn generates heat. Different ring/traveler systems concerning with its geometries, material combinations and coatings have already been implemented to solve the frictional problem. However, such developments can neither completely solve the frictional problem nor increase the productivity. The friction free superconducting magnetic bearing (SMB) system can be a right alternative replacing the existing ring/traveler system. The unique concept of SMB bearings is that they possess a self-stabilizing behavior, i.e. they remain fully passive without any necessity for expensive position sensing and control. Within the framework of a research project funded by German research foundation (DFG), suitable concepts of the SMB-system have been designed, developed, and integrated as a twisting device of ring spinning replacing the existing ring/traveler system. With the help of the developed mathematical model and experimental investigation, the physical limitations of this innovative twisting device in the spinning process have been determined. The interaction among the parameters of the spinning process and the superconducting twisting element has been further evaluated, which derives the concrete information regarding the new spinning process. Moreover, the influence of the implemented SMB twisting system on the yarn quality has been analyzed with respect to different process parameters. The presented work reveals the enormous potential of the innovative twisting mechanism, so that the productivity of the ring spinning process especially in case of thermoplastic materials can be at least doubled for the first time in a hundred years. The SMB ring spinning tester has also been presented in the international fair “International Textile Machinery Association (ITMA) 2015”.

Keywords: ring spinning, superconducting magnetic bearing, yarn properties, productivity

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Salleh, Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics

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Authors: Mohammadreza Heydariazad

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Productivity growth of wind energy as a clean source needed to achieve improved strategy in production and transmission and management of wind resources in order to increase quality of power and reduce costs. New technologies based on power converters that cause changing turbine speed to suit the wind speed blowing turbine improve extraction efficiency power from wind. This article introduces variable speed wind turbines and optimization of power, and presented methods to use superconducting inductor in the composition of power converter and is proposed the dc measurement for the wind farm and especially is considered techniques available to them. In fact, this article reviews mechanisms and function, changes of wind speed turbine according to speed control strategies of various types of wind turbines and examines power possible transmission and ac from producing location to suitable location for a strong connection integrating wind farm generators, without additional cost or equipment. It also covers main objectives of the dynamic control of wind turbines, and the methods of exploitation and the ways of using it that includes the unique process of these components. Effective algorithm is presented for power control in order to extract maximum active power and maintains power factor at the desired value.

Keywords: wind energy, generator, superconducting inductor, wind turbine power

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Authors: Lokes Parvatha Kumaran S., Sakthi Jay Mahenthar C., Sathyaprakash P., Jayakumar V., Shobanadevi A.

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With the evolution of technology, the need to solve complex computational problems like machine learning and deep learning has shot up. But even the most powerful classical supercomputers find it difficult to execute these tasks. With the recent development of quantum computing, researchers and tech-giants strive for new quantum circuits for machine learning tasks, as present works on Quantum Machine Learning (QML) ensure less memory consumption and reduced model parameters. But it is strenuous to simulate classical deep learning models on existing quantum computing platforms due to the inflexibility of deep quantum circuits. As a consequence, it is essential to design viable quantum algorithms for QML for noisy intermediate-scale quantum (NISQ) devices. The proposed work aims to explore Variational Quantum Circuits (VQC) for Deep Reinforcement Learning by remodeling the experience replay and target network into a representation of VQC. In addition, to reduce the number of model parameters, quantum information encoding schemes are used to achieve better results than the classical neural networks. VQCs are employed to approximate the deep Q-value function for decision-making and policy-selection reinforcement learning with experience replay and the target network.

Keywords: quantum computing, quantum machine learning, variational quantum circuit, deep reinforcement learning, quantum information encoding scheme

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Authors: Zhangquan Zhou, Guilin Qi

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Materialization is an important reasoning service for applications built on the Web Ontology Language (OWL). To make materialization efficient in practice, current research focuses on deciding tractability of an ontology language and designing parallel reasoning algorithms. However, some well-known large-scale ontologies, such as YAGO, have been shown to have good performance for parallel reasoning, but they are expressed in ontology languages that are not parallelly tractable, i.e., the reasoning is inherently sequential in the worst case. This motivates us to study the problem of parallel tractability of ontology materialization from a theoretical perspective. That is we aim to identify the ontologies for which materialization is parallelly tractable, i.e., in the NC complexity. Since the NC complexity is defined based on Boolean circuit that is widely used to investigate parallel computing problems, we first transform the problem of materialization to evaluation of Boolean circuits, and then study the problem of parallel tractability based on circuits. In this work, we focus on datalog rewritable ontology languages. We use Boolean circuits to identify two classes of datalog rewritable ontologies (called parallelly tractable classes) such that materialization over them is parallelly tractable. We further investigate the parallel tractability of materialization of a datalog rewritable OWL fragment DHL (Description Horn Logic). Based on the above results, we analyze real-world datasets and show that many ontologies expressed in DHL belong to the parallelly tractable classes.

Keywords: ontology materialization, parallel reasoning, datalog, Boolean circuit

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Jalal M. Abdallah

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This paper presents experimental studies carried out on a three phase transformer to investigate and develop the transformer models, which help in testing procedures, describing and evaluating the transformer dielectric conditions process and methods such as: the partial discharge (PD) localization in windings. The measurements are based on the transfer function methods in transformer windings by frequency response analysis (FRA). Numbers of tests conditions were applied to obtain the sensitivity frequency responses of a transformer for different type of faults simulated in a particular phase. The frequency responses were analyzed for the sensitivity of different test conditions to detect and identify the starting of small faults, which are sources of PD. In more detail, the aim is to explain applicability and sensitivity of advanced PD measurements for small short circuits and its localization. The experimental results presented in the paper will help in understanding the sensitivity of FRA measurements in detecting various types of internal winding short circuits in the transformer.

Keywords: frequency response analysis (FRA), measurements, transfer function, transformer

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Authors: Kaiwen Zheng, Wanting Zhou, Nan Tang, Lei Li, Yuanhang He

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The integrated circuit industry has become a cornerstone of the information society, finding widespread application in areas such as industry, communication, medicine, and aerospace. However, with the increasing complexity of integrated circuits, Hardware Trojans (HTs) implanted by attackers have become a significant threat to their security. In this paper, we proposed a hardware trojan detection method for large-scale circuits. As HTs introduce physical characteristic changes such as structure, area, and power consumption as additional redundant circuits, we proposed a machine-learning-based hardware trojan detection method based on the physical characteristics of gate-level netlists. This method transforms the hardware trojan detection problem into a machine-learning binary classification problem based on physical characteristics, greatly improving detection speed. To address the problem of imbalanced data, where the number of pure circuit samples is far less than that of HTs circuit samples, we used the SMOTETomek algorithm to expand the dataset and further improve the performance of the classifier. We used three machine learning algorithms, K-Nearest Neighbors, Random Forest, and Support Vector Machine, to train and validate benchmark circuits on Trust-Hub, and all achieved good results. In our case studies based on AES encryption circuits provided by trust-hub, the test results showed the effectiveness of the proposed method. To further validate the method’s effectiveness for detecting variant HTs, we designed variant HTs using open-source HTs. The proposed method can guarantee robust detection accuracy in the millisecond level detection time for IC, and FPGA design flows and has good detection performance for library variant HTs.

Keywords: hardware trojans, physical properties, machine learning, hardware security

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Authors: Anjela Koblischka-Veneva, Michael R. Koblischka

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In this contribution, the Transmission-Kikuchi Diffraction (TKD, or sometimes called t-EBSD) is applied to bulk, melt-grown YBa₂Cu₃O₇ (YBCO) superconductors prepared by the MTMG (melt-textured melt-grown) technique and the infiltration growth (IG) technique. TEM slices required for the analysis were prepared by means of Focused Ion-Beam (FIB) milling using mechanically polished sample surfaces, which enable a proper selection of the interesting regions for investigations. The required optical transparency was reached by an additional polishing step of the resulting surfaces using FIB-Ga-ion and Ar-ion milling. The improved spatial resolution of TKD enabled the investigation of the tiny YBa₂Cu₃O₅ (Y-211) particles having a diameter of about 50-100 nm embedded within the YBCO matrix and of other added secondary phase particles. With the TKD technique, the microstructural properties of the YBCO matrix are studied in detail. It is observed that the matrix shows the effects of stress/strain, depending on the size and distribution of the embedded particles, which are important for providing additional flux pinning centers in such superconducting bulk samples. Using the Kernel Average Misorientation (KAM) maps, the strain induced in the superconducting matrix around the particles, which increases the flux pinning effectivity, can be clearly revealed. This type of analysis of the EBSD/TKD data is, therefore, also important for other material systems, where nanoparticles are embedded in a matrix.

Keywords: transmission Kikuchi diffraction, EBSD, TKD, embedded particles, superconductors YBa₂Cu₃O₇

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Authors: Arabi Abderrazak, Bourouba Nacerdine, Ayad Mouloud, Belaout Abdeslam

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In this paper, a new test technique of analog circuits using time mode simulation is proposed for the single catastrophic faults detection in analog circuits. This test process is performed to overcome the problem of catastrophic faults being escaped in a DC mode test applied to the inverter amplifier in previous research works. The circuit under test is a second-order low pass filter constructed around this type of amplifier but performing a function that differs from that of the previous test. The test approach performed in this work is based on two key- elements where the first one concerns the unique square pulse signal selected as an input vector test signal to stimulate the fault effect at the circuit output response. The second element is the filter response conversion to a square pulses sequence obtained from an analog comparator. This signal conversion is achieved through a fixed reference threshold voltage of this comparison circuit. The measurement of the three first response signal pulses durations is regarded as fault effect detection parameter on one hand, and as a fault signature helping to hence fully establish an analog circuit fault diagnosis on another hand. The results obtained so far are very promising since the approach has lifted up the fault coverage ratio in both modes to over 90% and has revealed the harmful side of faults that has been masked in a DC mode test.

Keywords: analog circuits, analog faults diagnosis, catastrophic faults, fault detection

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Authors: Azizi Cherifa, O. Benzaoui

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The thermal aspects in the design of power circuits often deserve as much attention as pure electric components aspects as the operating temperature has a direct influence on their static and dynamic characteristics. MOSFET is fundamental in the circuits, it is the most widely used device in the current production of semiconductor components using their honorable performance. The aim of this contribution is devoted to the effect of the temperature on the properties of MOSFETs. The study enables us to calculate the drain current as function of bias in both linear and saturated modes. The effect of temperature is evaluated using a numerical simulation, using the laws of mobility and saturation velocity of carriers as a function of temperature.

Keywords: temperature, MOSFET, mobility, transistor

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Authors: Anjela Koblischka-Veneva, Michael Koblischka

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In this contribution, the transmission-Kikuchi diffrac-tion (TKD, or sometimes called t-EBSD) is applied to bulk, melt-grown YBa2Cu3O7 (YBCO) superconductors prepared by the MTMG (melt-textured melt-grown) technique and the infiltration (IG) growth technique. TEM slices required for the analysis were prepared by means of focused ion-beam (FIB) milling using mechanically polished sample surfaces, which enable a proper selection of the in-teresting regions for investigations. The required optical transparency was reached by an additional polishing step of the resulting surfaces using FIB-Ga-ion and Ar-ion milling. The improved spatial resolution of TKD enabled the investigation of the tiny Y2BaCuO5 (Y-211) particles having a diameter of about 50-100 nm embedded within the YBCO matrix and of other added secondary phase particles. With the TKD technique, the microstructural properties of the YBCO matrix are studied in detail. It is observed that the matrix shows effects of stress/strain, depending on the size and distribution of the embedded particles, which are important for providing additional flux pinning centers in such superconducting bulk samples. Using the Kernel average misorientation (KAM) maps, the strain induced in the superconducting matrix around the particles, which increases the flux pinning effectivity, can be clearly revealed. This type of analysis of the EBSD/TKD data is, therefore, also important for other material systems, where nanoparticles are embedded in a matrix.

Keywords: electron backscatter Diffraction, transmission Kikuchi diffraction, SEM, YBCO, microstructure, nanoparticles

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Authors: Nahla Elazab, Mohamed Aboudina, Ghada Ibrahim, Hossam Fahmy, Ahmed Khalil

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This paper presents the developed memristor based demodulators for eight circular Quadrature Amplitude Modulation (QAM) and Binary Frequency Shift Keying (BFSK) operating at relatively high frequency. In our implementations, the experimental-based ‘nonlinear’ dopant drift model is adopted along with the proposed circuits providing incorporation of all known non-idealities of practically realized memristor and gaining high operation frequency. The suggested designs leverage the distinctive characteristics of the memristor device, definitely, its changeable average memristance versus the frequency, phase and amplitude of the periodic excitation input. The proposed demodulators feature small integration area, low power consumption, and easy implementation. Moreover, the proposed QAM demodulator precludes the requirement for the carrier recovery circuits. In doing so, the designs were validated by transient simulations using the nonlinear dopant drift memristor model. The simulations results show high agreement with the theory presented.

Keywords: BFSK, demodulator, high frequency memristor applications, memristor based analog circuits, nonlinear dopant drift model, QAM

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Authors: Suleiman Babani, Jazuli Sanusi Kazaure

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In this paper, two coupled-line couplers are designed and simulated using stripline technology. The coupled-line couplers (A and B) are designed with different values of coupling coefficient 6dB and 10dB respectively. Both of circuits have a coupled output port, a through output port and an isolated output port. Moreover, both circuits are tuned to function around 2.45 GHz. The design results are presented by simulation results obtained using ADS 2012.08 (Advanced Design System) software.

Keywords: ADS, coupled-line coupler, directional coupler, stripline

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Authors: Patikineti Sreenivasulu, K. srinivasa Rao, A. Vinaya Babu

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The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits.

Keywords: power consumption, ultra-low power, leakage, sub threshold, MTCMOS

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Authors: Jun-Geol Park, Kyoung-Il Do, Min-Ju Kwon, Kyung-Hyun Park, Yong-Seo Koo

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This paper analyzed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuits with the turn-on time characteristics. The structures are the LVTSCR (Low Voltage Triggered SCR), the ZTSCR (Zener Triggered SCR) and the PTSCR (P-Substrate Triggered SCR). The three structures are for the 5V power clamp. In general, the structures with the low trigger voltage structure can have the fast turn-on characteristics than other structures. All the ESD protection circuits have the low trigger voltage by using the N+ bridge region of LVTSCR, by using the zener diode structure of ZTSCR, by increasing the trigger current of PTSCR. The simulation for the comparison with the turn-on time was conducted by the Synopsys TCAD simulator. As the simulation results, the LVTSCR has the turn-on time of 2.8 ns, ZTSCR of 2.1 ns and the PTSCR of 2.4 ns. The HBM simulation results, however, show that the PTSCR is the more robust structure of 430K in HBM 8kV standard than 450K of LVTSCR and 495K of ZTSCR. Therefore the PTSCR is the most effective ESD protection circuit for the 5V power clamp.

Keywords: ESD, SCR, turn-on time, trigger voltage, power clamp

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Authors: Sangguk Ahn, Youngyu Kim, Jaheon Gu, Gyoutae Park

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In this paper, we developed a dual gas leak instrument to detect Hydrocarbon (HC) and Monoxide (CO) gases. To two kinds of gases, it is necessary to design compact structure for sensors. And then it is important to draw sensing circuits such as measuring, amplifying and filtering. After that, it should be well programmed with robust, systematic and module coding methods. In center of them, improvement of accuracy and initial response time are a matter of vital importance. To manufacture distinguished gas leak detector, we applied intrinsically safe explosion-proof structure to lithium ion battery, main circuits, a pump with motor, color LCD interfaces and sensing circuits. On software, to enhance measuring accuracy we used numerical analysis such as Lagrange and Neville interpolation. Performance test result is conducted by using standard Methane with seven different concentrations with three other products. We want raise risk prevention and efficiency of gas safe management through distributing to the field of gas safety. Acknowledgment: This study was supported by Small and Medium Business Administration under the research theme of ‘Commercialized Development of a portable intrinsically safe explosion-proof type dual gas leak detector’, (task number S2456036).

Keywords: gas leak, dual gas detector, intrinsically safe, explosion proof

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Authors: Biswarup Mukherjee, Aniruddha Ghosal

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In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Dong Zhao

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Even though the recent claim of room temperature superconductivity by LK-99 was confirmed an unsuccessful attempt, this work reawakened people’s century striving to get applicable superconductors with Tc of room temperature or higher and under ambient pressure. One of the efforts was focusing on exploring the thorium salts. This is because certain thorium compounds revealed an unusual property of having both high electrical conductivity and diamagnetism or the so-called “coexistence of high electrical conductivity and diamagnetism.” It is well known that this property of the coexistence of high electrical conductivity and diamagnetism is held by superconductors because of the electron pairings. Consequently, the likelihood for these thorium compounds to have superconducting properties becomes great. However, as a surprise, these thorium salts possess this property at room temperature and atmosphere pressure. This gives rise to solid evidence for these thorium compounds to be room-temperature superconductors without a need for external pressure. Among these thorium compound superconductors claimed in that work, thorium di-iodide (ThI₂) is a unique one and has received comprehensive discussion. ThI₂ was synthesized and structurally analyzed by the single crystal diffraction method in the 1960s. Its special property of coexistence of high electrical conductivity and diamagnetism was revealed. Because of this unique property, a special molecular configuration was sketched. Except for an ordinary oxidation of +2 for the thorium cation, the thorium’s oxidation state in ThI₂ is +4. According to the experimental results, ThI₂‘s actual molecular configuration was determined as an unusual one of [Th4+(e-)2](I-)2. This means that the ThI₂ salt’s cation is composed of a [Th4+(e-)2]2+ cation core. In other words, the cation of ThI₂ is constructed by combining an oxidation state +4 of the thorium atom and a pair of electrons or an electron lone pair located on the thorium atom. This combination of the thorium atom and the electron lone pair leads to an oxidation state +2 for the [Th4+(e-)2]2+ cation core. This special construction of the thorium cation is very distinctive, which is believed to be the factor that grants ThI₂ the room temperature superconductivity. Actually, the key for ThI₂ to become a room-temperature superconductor is this characteristic electron lone pair residing on the thorium atom along with the formation of a network constructed by the thorium atoms. This network specializes in a way that allows the electron lone pairs to hop over it and, thus, to generate the supercurrent. This work will discuss, in detail, the special electrical and magnetic properties of ThI₂ as well as its structural features at ambient conditions. The exploration of how the electron pairing in combination with the structurally specialized network works together to bring ThI₂ into a superconducting state. From the experimental results, strong evidence has definitely pointed out that the ThI₂ should be a superconductor, at least at room temperature and under atmosphere pressure.

Keywords: co-existence of high electrical conductivity and diamagnetism, electron lone pair, room temperature superconductor, special molecular configuration of thorium di-iodide ThI₂

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Authors: Fawzia Al-Sakeer, Hassan Aldeeb

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Development in the communications field is proceeding at an amazing speed, which has led researchers to improve and develop electronic circuits by increasing their efficiency and reducing their size to reduce the weight of electronic devices. One of the most important of these circuits is the band-pass filter, which is what made us carry out this research, which aims to use an alternate technology to design a dual band-pass filter by using a stepped impedance microstrip transmission line. We designed a filter that works at two center frequency bands by designing with the ADS program, and the results were excellent, as we obtained the two design frequencies, which are 1 and 3GHz, and the values of insertion loss S11, which was more than 21dB with a small area.

Keywords: band pass filter, dual band band-pass filter, ADS, microstrip filter, stepped impedance

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Authors: Mohamed Mahmoud

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This paper has developed an effect-cause analysis technique for fault diagnosis in digital circuits. The main algorithm of our technique is based on the Enhanced Deduction Algorithm, which processes the real response of the CUT to the applied test T to deduce the values of the internal lines. An experimental version of the algorithm has been implemented in C++. The code takes about 7592 lines. The internal values are determined based on the logic values under the permanent stuck-fault model. Using a backtracking strategy guarantees that the actual values are covered by at least one solution, or no solution is found.

Keywords: enhanced deduction algorithm, backtracking strategy, automatic test equipment, verfication

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Authors: K. Shaji Mon, P. R. John Sreenidhi

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In deep-submicrometer CMOS processes, time-domain resolution of a digital signal is becoming higher than voltage resolution of analog signals. This claim is nowadays pushing toward a new circuit design paradigm in which the traditional analog signal processing is expected to be progressively substituted by the processing of times in the digital domain. Within this novel paradigm, digitally controlled delay lines (DCDL) should play the role of digital-to-analog converters in traditional, analog-intensive, circuits. Digital delay locked loops are highly prevalent in integrated systems.The proposed paper addresses the glitches present in delay circuits along with area,power dissipation and signal integrity.The digitally controlled delay lines(DCDL) under study have been designed in a 90 nm CMOS technology 6 layer metal Copper Strained SiGe Low K Dielectric. Simulation and synthesis results show that the novel circuits exhibit no glitches for dual output coarse DCDL with less power dissipation and consumes less area compared to the glitch free NAND based DCDL.

Keywords: glitch free, NAND-based DCDL, CMOS, deep-submicrometer

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Authors: Jerome G. Chandraseelan, Samuel M. D. Oliveira, Antti Häkkinen, Sofia Startceva, Andre S. Ribeiro

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We used live E. coli containing synthetic genetic oscillators to study how the degree of synchrony between the genetic circuits of sister cells changes with temperature. We found that both the mean and the variability of the degree of synchrony between the fluorescence signals from sister cells are affected by temperature. Also, while most pairs of sister cells were found to be highly synchronous in each condition, the number of asynchronous pairs increased with increasing temperature, which was found to be due to disruptions in the oscillations. Finally we provide evidence that these disruptions tend to affect multiple generations as opposed to individual cells. These findings provide insight in how to design more robust synthetic circuits and in how cell division can affect their dynamics.

Keywords: repressilator, robustness, synchrony, synthetic biology

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Authors: Abdeljalil Metioui

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The purpose of this article is to present the results of two-stage qualitative research. The first involved the identification of the alternative conceptions of 80 elementary pre-service teachers from Quebec in Canada about the operation of simple electrical circuits. To do this, they completed a two-choice questionnaire (true or false) with justification. Data analysis identifies many conceptual difficulties. For example, for their majority, whatever the electrical device that composes an electrical circuit, the current source (power supply), and the generated electrical power is constant. The second step was to develop a double multiple-choice questionnaire based on the identified designs. It allows teachers to quickly diagnose their students' conceptions and take them into account in their teaching.

Keywords: development, electrical circuits, two-tier diagnostic test, secondary and high school

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: M. A. Grigoryev, A. N. Shishkov, D. A. Sychev

Abstract:

The article defines the necessity of choosing the optimal power circuits scheme of the electric drive with field regulated reluctance machine. The specific weighting factors are calculation, the linear regression dependence of specific losses in semiconductor frequency converters are presented depending on the values of the rated current. It is revealed that with increase of the carrier frequency PWM improves the output current waveform, but increases the loss, so you will need depending on the task in a certain way to choose from the carrier frequency. For task of optimization by criterion of the minimum electrical losses regression dependence of the electrical losses in the frequency converter circuit at a frequency of a PWM signal of 0 Hz. The surface optimization criterion is presented depending on the rated output torque of the motor and number of phases. In electric drives with field regulated reluctance machine with at low output power optimization criterion appears to be the worst for multiphase circuits. With increasing output power this trend hold true, but becomes insignificantly different optimal solutions for three-phase and multiphase circuits. This is explained to the linearity of the dependence of the electrical losses from the current.

Keywords: field regulated reluctance machine, the electrical losses, multiphase power circuit, the surface optimization criterion

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