Search results for: power delay product

Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

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In this paper, the transient device performance analysis of n-type Gate Inside Junctionless Transistor (GIJLT)has been evaluated. 3-D Bohm Quantum Potential (BQP)transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor(TGF) and unity gain cut-off frequency (fT) and subthreshold slope (SS) of the GI-JLT and Gate-all-around junctionless transistor(GAA-JLT) have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: gate-inside junctionless transistor GI-JLT, gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product

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Authors: Gagnesh Kumar, Prashant Gupta

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This paper investigates the performance of the bundle of single wall carbon nanotubes (SWCNT) for low-power and high-speed interconnects for future VLSI applications. The power dissipation, delay and power delay product (PDP) of SWCNT bundle interconnects are examined and compared with that of the Cu interconnects at 22 nm technology node for both intermediate and global interconnects. The results show that SWCNT bundle consume less power and also faster than Cu for intermediate and global interconnects. It is concluded that the metallic SWCNT has been regarded as a viable candidate for intermediate and global interconnects in future technologies.

Keywords: carbon nanotube, SWCNT, low power, delay, power delay product, global and intermediate interconnects

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Authors: Ata Khorami, Mohammad Sharifkhani

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In the dynamic comparators, the pre-amplifier amplifies the input differential voltage and when the output Vcm of the pre-amplifier becomes larger than Vth of the latch input transistors, the latch is activated and finalizes the comparison. As a result, the pre-amplification delay is fixed to a value and cannot be set at the minimum required delay, thus, significant power and delay are imposed. In this paper, a novel structure is proposed through which the pre-amplification delay can be set at any low value saving power and time. Simulations show that using the proposed structure, by setting the pre-amplification delay at the minimum required value the power and comparison delay can be reduced by 55% and 100ps respectively.

Keywords: dynamic comparator, low power comparator, analog to digital converter, pre-amplification delay

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Authors: Guo-Ming Sung, Ramavath Naga Raju Naik

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This paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Shao-Ku Kao

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This paper presents an active rectifier with time-domain delay compensation to enhance the efficiency. A delay calibration circuit is designed to convert delay time to voltage and adaptive control on/off delay in variable input voltage. This circuit is designed in 0.18 mm CMOS process. The input voltage range is from 2 V to 3.6 V with the output voltage from 1.8 V to 3.4 V. The efficiency can maintain more than 85% when the load from 50 Ω ~ 1500 Ω for 3.6 V input voltage. The maximum efficiency is 92.4 % at output power to be 38.6 mW for 3.6 V input voltage.

Keywords: wireless power transfer, active diode, delay compensation, time to voltage converter, PCE

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Authors: Goutom K. Pall

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At the very heart of the power system, power transmission (PT) acts as an essential link between power generation and distribution. Timely completion of PT infrastructures is therefore crucial to support the development of power system as a whole. Yet despite the importance, studies on PT infrastructure development projects are embryonic and, hence, PT projects undergoing widespread delays worldwide. These delay factors are idiosyncratic and identifying the critical delay factors is essential if the PT industry professionals are to complete their projects efficiently and within the expected timeframes. This study identifies and categorizes 46 causes of PT project delay under ten major groups using six sector expert’s recommendations studied by a preliminary questionnaire survey. Based on the experts’ strong recommendations, two new groups are introduced in the final questionnaire survey: sector specific factors (SSF) and general factors (GF). SSF pertain to delay factors applicable only to the PT projects, while GF represents less biased samples with shared responsibilities of all project parties involved in a project. The study then uses 112 data samples from the contractors to rank the delay factors using relative importance index (RII). The results reveal that SSF, GF and external factors are the most critical groups, while the highest ranked delay factors include the right of way (RoW) problems of transmission lines (TL), delay in payments, frequent changes in TL routes, poor communication and coordination among the project parties and accessibility to TL tower locations. Finally, recommendations are made to minimize the identified delay. The findings are expected to be of substantial benefit to professionals in minimizing time overrun in PT projects implementation, as well as power generation, power distribution, and non-power linear construction projects worldwide.

Keywords: delay, project delay, power transmission projects, time-overruns

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Authors: Ch. Ashok Babu, J. V. R. Ravindra, K. Lalkishore

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Power has became a burning issue in modern VLSI design. As the technology advances especially below 45nm, technology of leakage power became a big problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder, DTMOS full adder. This paper shows different types of adders and their power consumption, area, and delay. All the experiments have been carried out using Cadence® Virtuoso® design lay out editor which shows power consumption of different types of adders.

Keywords: average power, leakage power, delay, DTMOS, PDP

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Authors: Naima Guenifi, Shiromani Balmukund Rahi, Amina Bechka

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Tunnel FET is one of the most suitable alternatives FET devices for conventional CMOS technology for low-power electronics and applications. Due to its lower subthreshold swing (SS) value, it is a strong follower of low power applications. It is a quantum FET device that follows the band to band (B2B) tunneling transport phenomena of charge carriers. Due to band to band tunneling, tunnel FET is suffering from a lower switching current than conventional metal-oxide-semiconductor field-effect transistor (MOSFET). For improvement of device features and limitations, the newly invented negative capacitance concept of ferroelectric material is implemented in conventional Tunnel FET structure popularly known as NC TFET. The present research work has implemented the idea of high-k gate dielectric added with ferroelectric material on double gate Tunnel FET for implementation of negative capacitance. It has been observed that the idea of negative capacitance further improves device features like SS value. It helps to reduce power dissipation and switching energy. An extensive investigation for circularity uses for digital, analog/RF and linearity features of double gate NCTFET have been adopted here for research work. Several essential designs paraments for analog/RF and linearity parameters like transconductance(gm), transconductance generation factor (gm/IDS), its high-order derivatives (gm2, gm3), cut-off frequency (fT), gain-bandwidth product (GBW), transconductance generation factor (gm/IDS) has been investigated for low power RF applications. The VIP₂, VIP₃, IMD₃, IIP₃, distortion characteristics (HD2, HD3), 1-dB, the compression point, delay and power delay product performance have also been thoroughly studied.

Keywords: analog/digital, ferroelectric, linearity, negative capacitance, Tunnel FET, transconductance

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Authors: Tzu-Yang Lin, Chuan-Ching Sue

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Sleep mechanisms are commonly used to ensure the energy efficiency of each optical network unit (ONU) that concerns a single class delay constraint in the Ethernet Passive Optical Network (EPON). How long the ONUs can sleep without violating the delay constraint has become a research problem. Particularly, we can derive an analytical model to determine the optimal sleep time of ONUs in every cycle without violating the maximum class delay constraint. The bandwidth allocation considering such optimal sleep time is called Green Bandwidth Allocation (GBA). Although the GBA mechanism guarantees that the different class delay constraints do not violate the maximum class delay constraint, packets with a more relaxed delay constraint will be treated as those with the most stringent delay constraint and may be sent early. This means that the ONU will waste energy in active mode to send packets in advance which did not need to be sent at the current time. Accordingly, we proposed a QoS-aware GBA using a novel intra-ONU scheduling to control the packets to be sent according to their respective delay constraints, thereby enhancing energy efficiency without deteriorating delay performance. If packets are not explicitly classified but with different packet delay constraints, we can modify the intra-ONU scheduling to classify packets according to their packet delay constraints rather than their classes. Moreover, we propose the switchable ONU architecture in which the ONU can switch the architecture according to the sleep time length, thus improving energy efficiency in the QoS-aware GBA. The simulation results show that the QoS-aware GBA ensures that packets in different classes or with different delay constraints do not violate their respective delay constraints and consume less power than the original GBA.

Keywords: Passive Optical Networks, PONs, Optical Network Unit, ONU, energy efficiency, delay constraint

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Authors: K. Shaji Mon, P. R. John Sreenidhi

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In deep-submicrometer CMOS processes, time-domain resolution of a digital signal is becoming higher than voltage resolution of analog signals. This claim is nowadays pushing toward a new circuit design paradigm in which the traditional analog signal processing is expected to be progressively substituted by the processing of times in the digital domain. Within this novel paradigm, digitally controlled delay lines (DCDL) should play the role of digital-to-analog converters in traditional, analog-intensive, circuits. Digital delay locked loops are highly prevalent in integrated systems.The proposed paper addresses the glitches present in delay circuits along with area,power dissipation and signal integrity.The digitally controlled delay lines(DCDL) under study have been designed in a 90 nm CMOS technology 6 layer metal Copper Strained SiGe Low K Dielectric. Simulation and synthesis results show that the novel circuits exhibit no glitches for dual output coarse DCDL with less power dissipation and consumes less area compared to the glitch free NAND based DCDL.

Keywords: glitch free, NAND-based DCDL, CMOS, deep-submicrometer

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Authors: Nithiya C., Komathi B. J., Praveena N. G., Samuda Prathima

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At present, the ultimate aim in digital system designs, especially at the gate level and lower levels of design abstraction, is power optimization. Adders are a nearly universal component of today's integrated circuits. Most of the research was on the design of high-speed adders to execute addition based on various adder structures. This paper discusses the ideal path for selecting an arithmetic unit for IoT applications. Based on the analysis of eight types of 16-bit adders, we found out Carry Look-ahead (CLA) produces low power. Additionally, multiplier and accumulator (MAC) unit is implemented with the Booth multiplier by using the low power adders in the order of preference. The design is synthesized and verified using Synopsys Design Compiler and VCS. Then it is implemented by using Cadence Encounter. The total power consumed by the CLA based booth multiplier is 0.03527mW, the total area occupied is 11260 um², and the speed is 2034 ps.

Keywords: carry look-ahead, carry select adder, CSA, internet of things, ripple carry adder, design rule check, power delay product, multiplier and accumulator

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Authors: Y. Gholipour, E. Rezazadeh

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Delay is one of the most serious and common problems of construction project that can affect project delivery unfavorably. This research presents the most important causes of delay in large dam projects based on a survey on some executed dam construction in Iran. In this survey a randomly selected samples of owners, consultants and contractors have been involved. The outcome of this survey revealed that scheduled payments, site management, shop drawing review process, unforeseen ground conditions and contractor experience as the most important factors affecting on delay in dam construction projects.

Keywords: delay, dam construction, project management, Iran

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Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim

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Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

Keywords: deadline, dynamic voltage frequency scaling, power state transition

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Authors: Kala Bharathan, R. Seshasayanan

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In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Mohsen Maadani, Seyed Ahmad Motamedi

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The use of wireless technology in industrial networks has gained vast attraction in recent years. In this paper, we have thoroughly analyzed the effect of contention window (CW) size on the performance of IEEE 802.11-based industrial wireless networks (IWN), from delay and reliability perspective. Results show that the default values of CWmin, CWmax, and retry limit (RL) are far from the optimum performance due to the industrial application characteristics, including short packet and noisy environment. An adaptive CW algorithm (payload-dependent) has been proposed to minimize the average delay. Finally a simple, but effective CW and RL setting has been proposed for industrial applications which outperforms the minimum-average-delay solution from maximum delay and jitter perspective, at the cost of a little higher average delay. Simulation results show an improvement of up to 20%, 25%, and 30% in average delay, maximum delay and jitter respectively.

Keywords: average delay, contention window, distributed coordination function (DCF), jitter, industrial wireless network (IWN), maximum delay, reliability, retry limit

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Authors: Arpita Saha, Satish Chandra, Indrajit Ghosh

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Delay implicates the time loss of a traveler while crossing an intersection. Efficiency of traffic operation at signalized intersections is assessed in terms of delay caused to an individual vehicle. Highway Capacity Manual (HCM) method and Webster’s method are the most widely used in India for delay estimation purpose. However, in India, traffic is highly heterogeneous in nature with extremely poor lane discipline. Therefore, to explore best delay estimation technique for Indian condition, a comparison was made. In this study, seven signalized intersections from three different cities where chosen. Data was collected for both during morning and evening peak hours. Only under saturated cycles were considered for this study. Delay was estimated based on the field data. With the help of Simpson’s 1/3 rd rule, delay of under saturated cycles was estimated by measuring the area under the curve of queue length and cycle time. Moreover, the field observed delay was compared with the delay estimated using HCM, Webster, Probabilistic, Taylor’s expansion and Regression methods. The drawbacks of the existing delay estimation methods to be use in Indian heterogeneous traffic conditions were figured out, and best method was proposed. It was observed that direct estimation of delay using field measured data is more accurate than existing conventional and modified methods.

Keywords: delay estimation technique, field delay, heterogeneous traffic, signalised intersection

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Authors: Sunil Verma

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This report is concerned with study of autoignition delay characterstics of n-pentane. Experiments are done for different equivalents ratio on Rapid compression machine. Dependence of autoignition delay period is clearly explained from lean to rich mixtures. Equivalence ratio is varied from 0.33 to 0.6.

Keywords: combustion, autoignition, ignition delay, rapid compression machine

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Authors: H. Namazi, H. T. N. Kuan

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Fick's first law relates the diffusive flux to the concentration field, by postulating that the flux goes from regions of high concentration to regions of low concentration, with a magnitude that is proportional to the concentration gradient (spatial derivative). It is clear that the diffusion of flux cannot be instantaneous and should be some time delay in this propagation. But Fick’s first law doesn’t consider this delay which results in some errors especially when there is a considerable time delay in the process. In this paper, we introduce a time delay to Fick’s first law. By this modification, we consider that the diffusion of flux cannot be instantaneous. In order to verify this claim an application sample in fluid diffusion is discussed and the results of modified Fick’s first law, Fick’s first law and the experimental results are compared. The results of this comparison stand for the accuracy of the modified model. The modified model can be used in any application where the time delay has considerable value and neglecting its effect reflects in undesirable results.

Keywords: Fick's first law, flux, diffusion, time delay, modified Fick’s first law

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Authors: Abdullah Alsehaimi

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Over decades, there have been many studies of delay in construction, and this type of study continues to be popular in construction management research. A synthesis and critical evaluation of delay studies in developing countries reveals that poor project management is cited as one of the main causes of delay. However, despite such consensus, most of the previous studies fall short in providing clear recommendations demonstrating how project management practice could be improved. Moreover, the majority of recommendations are general and not devoted to solving the difficulties associated with particular delay causes. This paper aims to demonstrate that the root cause of this state of affairs is that typical research into delay tends to be descriptive and explanatory, making it inadequate for solving persistent managerial problems in construction. It is contended that many problems in construction could be mitigated via alternative research approaches, i.e. action and constructive research. Such prescriptive research methods can assist in the development and implementation of innovative tools tackling managerial problems of construction, including that of delay. In so doing, those methods will better connect research and practice, and thus strengthen the relevance of academic construction management.

Keywords: construction delay, action research, constructive research, industrial engineering

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Authors: Chhavi Saxena

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FinFETs can be a replacement for bulk-CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable supply voltage schemes. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, the output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model.

Keywords: FinFET, 7T SRAM cell, leakage current, delay

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Authors: Chun-Chuan Yang, Jeng-Yueng Chen, Yi-Ting Mai, Hsieh-Hua Liu

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By introduction of Relay Nodes (RNs), LTE-Advanced can provide enhanced coverage and capacity at cell edges and hot-spot areas. The authors have been researching the issue of power saving in mobile communications technology such as WiMax and LTE for some years. Based on the idea of Load-Based Power Saving (LBPS), three efficient power saving schemes for the user equipment (UE) were proposed in the authors’ previous work. In this paper, three revised schemes of the previous work in order to integrate RN and UE in power saving are proposed. Simulation study shows the proposed schemes can achieve significantly better power saving efficiency than the standard based scheme at the cost of moderately increased delay.

Keywords: DRX, LTE-A, power saving, RN

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Authors: Iyai Davies, Olivier L. C. Haas

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In this paper, the problem of stability and stabilization for neutral delay-differential systems with infinite delay is investigated. Using Lyapunov method, new delay-independent sufficient condition for the stability of neutral systems with infinite delay is obtained in terms of linear matrix inequality (LMI). Memory-less state feedback controllers are then designed for the stabilization of the system using the feasible solution of the resulting LMI, which are easily solved using any optimization algorithms. Numerical examples are given to illustrate the results of the proposed methods.

Keywords: infinite delays, Lyapunov method, linear matrix inequality, neutral systems, stability

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Authors: Sulaiman Yunus

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The need for modeling response to urban fire disaster cannot be over emphasized, as recurrent fire outbreaks have gutted most cities of the world. This necessitated the need for a prompt and efficient response system in order to mitigate the impact of the disaster. Promptness, as a function of time, is seen to be the fundamental determinant for efficiency of a response system and magnitude of a fire disaster. Delay, as a result of several factors, is one of the major determinants of promptgness of a response system and also the magnitude of a fire disaster. Response Delay Model (RDM) intends to bridge the gap in urban fire disaster response system through incorporating and synchronizing the delay moments in measuring the overall efficiency of a response system and determining the magnitude of a fire disaster. The model identified two delay moments (pre-notification and Intra-reflex sequence delay) that can be elastic and collectively plays a significant role in influencing the efficiency of a response system. Due to variation in the elasticity of the delay moments, the model provides for measuring the length of delays in order to arrive at a standard average delay moment for different parts of the world, putting into consideration geographic location, level of preparedness and awareness, technological advancement, socio-economic and environmental factors. It is recommended that participatory researches should be embarked on locally and globally to determine standard average delay moments within each phase of the system so as to enable determining the efficiency of response systems and predicting fire disaster magnitudes.

Keywords: delay moment, fire disaster, reflex sequence, response, response delay moment

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Authors: Latif Adnane, Benaatou Wafa, Pla Vicent

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Handover is of great significance to achieve seamless connectivity in wireless networks. This paper gives an impression of the main factors which are being affected by the soft and the hard handovers techniques. To know and understand the handover process in The Universal Mobile Telecommunications System (UMTS) network, different statistics are calculated. This paper focuses on the quality of service (QoS) of soft and hard handover in UMTS network, which includes the analysis of received power, signal to noise radio, throughput, delay traffic, traffic received, delay, total transmit load, end to end delay and upload response time using OPNET simulator.

Keywords: handover, UMTS, mobility, simulation, OPNET modeler

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Authors: Jong-Jy Shyu, Soo-Chang Pei, Yun-Da Huang

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In this paper, design of wide-range variable fractional-delay (WR-VFD) finite impulse response (FIR) digital filters is proposed. With respect to the conventional VFD filter which is designed such that its delay is adjustable within one unit, the proposed VFD FIR filter is designed such that its delay can be tunable within a wider range. By the traces of coefficients of the fractional-delay FIR filter, it is found that the conventional method of polynomial substitution for filter coefficients no longer satisfies the design demand, and the circuits perform the sinc function (sinc converter) are added to overcome this problem. In this paper, least-squares method is adopted to design WR-VFD FIR filter. Throughout this paper, several examples will be proposed to demonstrate the effectiveness of the presented methods.

Keywords: digital filter, FIR filter, variable fractional-delay (VFD) filter, least-squares approximation

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Authors: Ahmed Alutaibi, Ganti Sudhakar

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Providing better Quality-of-Service (QoS) to end users has been a challenging problem for researchers and service providers. Building applications relying on best effort network protocols hindered the adoption of guaranteed service parameters and, ultimately, Quality of Service. The introduction of Software Defined Networking (SDN) opened the door for a new paradigm shift towards a more controlled programmable configurable behavior. Openflow has been and still is the main implementation of the SDN vision. To facilitate better QoS for applications, the network must calculate and measure certain parameters. One of those parameters is the delay between the two ends of the connection. Using the power of SDN and the knowledge of application and network behavior, SDN networks can adjust to different conditions and specifications. In this paper, we use the capabilities of SDN to implement multiple algorithms to measure delay end-to-end not only inside the SDN network. The results of applying the algorithms on an emulated environment show that we can get measurements close to the emulated delay. The results also show that depending on the algorithm, load on the network and controller can differ. In addition, the transport layer handshake algorithm performs best among the tested algorithms. Out of the results and implementation, we show the limitations of Openflow and develop suggestions to solve them.

Keywords: software defined networking, quality of service, delay measurement, openflow, mininet

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Authors: Reza Sadeghi

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In this study, microwave heating was employed for controlling Oryzaephilus mercator. adults infesting stored Iranian dried fig. For this purpose, the dried fig samples were artificially infested with O. mercator and then heated in a microwave oven (2450 MHz) at the power outputs of 450, 720, and 900 W for 10, 20, 30, and 40 s, respectively. Subsequently, changes in the colors of the product samples under the effects of the varied microwave applications were investigated in terms of lightness (ΔL*), redness (Δa*), and yellowness (Δb*) using an image processing technique. The results revealed that both parameters of microwave power and exposure time had significant impacts on the pest mortality rates (p<0.01). In fact, a direct positive relationship was obtained between the mortality rate and microwave irradiation power. Complete mortality was achieved for the pest at the power of 900 W and exposure time of 40 s. The dried fig samples experienced fewer changes in their color parameters. Considering the successful pest control and acceptable changes in the product quality, microwave irradiation can be introduced as an appropriate alternative to chemical fumigants.

Keywords: colorimetric assay, microwave heating, Oryzaephilus mercator, mortality

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Authors: Purva Joshi, Rohit Thanki, Omar Hanif

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Unmanned aerial vehicles (UAVs) are becoming increasingly important in various industrial applications and sectors. Nowadays, a multi UAV network is used for specific types of communication (e.g., military) and monitoring purposes. Therefore, it is critical to reducing propagation delay during communication between UAVs, which is essential in a multi UAV network. This paper presents how the propagation delay between the base station (BS) and the UAVs is reduced using a searching algorithm. Furthermore, the iterative-based K-nearest neighbor (k-NN) algorithm and Travelling Salesmen Problem (TSP) algorthm were utilized to optimize the distance between BS and individual UAV to overcome the problem of propagation delay in multi UAV networks. The simulation results show that this proposed method reduced complexity, improved reliability, and reduced propagation delay in multi UAV networks.

Keywords: multi UAV network, optimal distance, propagation delay, K - nearest neighbor, traveling salesmen problem

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

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CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE

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Authors: Ibrahim Mahamid, A. Al-Ghonamy, M. Aichouni

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This study aims at identifying the risk matrix for delay causes in construction projects in Saudi Arabia from consultants’ viewpoint. A questionnaire survey was undertaken of 51 consultants working on construction projects in the Northern Province of Saudi Arabia. 35 delay causes were identified through a literature review. The study concluded that the top delay causes in construction projects in Saudi Arabia from consultants’ perspective are: bid award for lowest price, changes in material types and specifications during construction, contract management, duration of contract period, fluctuation of prices of materials, frequent changes in design, improper planning, inflationary pressure, lack of adequate manpower, long period of design and time of implementation, payments delay, poor labor productivity, and rework.

Keywords: delays, construction, consultants, contributors, risk map

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