Search results for: CNFET

Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE

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Authors: Jagpal Singh Ubhi, Jai Kumar Yadav, Candy Goyal

Abstract:

The demand for portable electronics is increasing at an exponential rate. The speed of the circuit is another challenge to keep the power dissipation at an acceptable range. Full adder (FA) is the essential and critical part of the system; any circuit optimization in FA can optimize the whole system. As the technology is shrinking towards the nano-scale regime, leakage power is increasing at an exponential rate. The designing of the inexact FA circuit utilizing a carbon nanotube field-effect transistor (CNFET) is proposed in this paper, which improves the figure of merits such as delay, leakage power, and energy consumption of the FA circuit. Inexact circuits are an effective way for the improvement of efficiency of the courses. The aim is to design the approximate FA circuit for low-power image processing applications. Simulation is done at two levels, such as application and circuit levels, At the circuit level, matrices, the average power, propagation delay, power-delay product (PDP), energy-delay product, and leakage power dissipation are measured and compared to reported data and the design/circuit given in this paper has best results. In this paper, the peak-signal-to-noise ratio (PSNR) is also calculated to at the application level to show the superiority of the design.

Keywords: full adder, carbon nanotube field-effect transistor, peak-signal-to-noise ratio, power-delay product

Procedia PDF Downloads 33