Search results for: three dimensional integration circuits

Authors: Wieslaw Marszalek, Zdzislaw Trzaska

Abstract:

Interesting properties of various one-period loops of singularly perturbed memristive circuits with mixed-mode oscillations (MMOs) are analyzed in this paper. The analysis is mixed, both analytical and numerical and focused on the properties of pinched hysteresis of the memristive element and other one-period loops formed by pairs of time-series solutions for various circuits' variables. The memristive element is the only nonlinear element in the two circuits. A theorem on periods of mixed-mode oscillations of the circuits is formulated and proved. Replacements of memristors by parallel G-C or series R-L circuits for a MMO response with equivalent RMS values is also discussed.

Keywords: mixed-mode oscillations, memristive circuits, pinched hysteresis, one-period loops, singularly perturbed circuits

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Authors: Zouari Ezzeddine, Tarchoun Monaem

Abstract:

Despite the multiplicity of advanced approaches, the concept of financial integration couldn’t be an explicit analysis. Indeed, empirical studies appear that the measures of international financial integration are one-dimensional analyses. For the ambivalence of the concept and its multiple determinants, it must be analyzed in multidimensional level. The interest of this research is a proposal of a decision support by multicriteria approach for determining the positions of countries according to their international and financial dependencies links with the behavior of financial actors (trying to make governance decisions or diversification strategies of international portfolio ...

Keywords: financial integration, decision support, behavior, multicriteria approach, governance and diversification

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Authors: Kwan-Ho Kim, Jin-Hong Park

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The multi-valued logic (MVL) circuits, which can handle more than two logic states, are one of the promising solutions to overcome the bit density limitations of conventional binary logic systems. Recently, tunneling devices such as Esaki diode and resonant tunneling diode (RTD) have been extensively explored to construct the MVL circuits. These tunneling devices present a negative differential resistance (NDR) phenomenon in which a current decreases as a voltage increases in a specific applied voltage region. Due to this non-monotonic current behavior, the tunneling devices have more than two threshold voltages, consequently enabling construction of MVL circuits. Recently, the emergence of two dimensional (2D) van der Waals (vdW) crystals has opened up the possibility to fabricate such tunneling devices easily. Owing to the defect-free surface of the 2D crystals, a very abrupt junction interface could be formed through a simple stacking process, which subsequently allowed the implementation of a high-performance tunneling device. Here, we report a vdW heterostructure based tunneling device with multiple threshold voltages, which was fabricated with black phosphorus (BP) and hafnium diselenide (HfSe₂). First, we exfoliated BP on the SiO₂ substrate and then transferred HfSe₂ on BP using dry transfer method. The BP and HfSe₂ form type-Ⅲ heterojunction so that the highly doped n+/p+ interface can be easily implemented without additional electrical or chemical doping process. Owing to high natural doping at the junction, record high peak to valley ratio (PVCR) of 16 was observed to the best our knowledge in 2D materials based NDR device. Furthermore, based on this, we first demonstrate the feasibility of the ternary latch by connecting two multi-threshold voltage devices in series.

Keywords: two dimensional van der Waals crystal, multi-valued logic, negative differential resistnace, tunneling device

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Authors: Nesrine Toubaline, Djamel Bennouar, Ali Mahdoum

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3D technology can lead to a significant reduction in power and average hop-count in Networks on Chip (NoCs). It offers short and fast vertical links which copes with the long wire problem in 2D NoCs. This work proposes heuristic-based method to optimize number and placement of vertical links to achieve specified performance goals. Experiments show that significant improvement can be achieved by using a specific number of vertical interconnect.

Keywords: interconnect optimization, monolithic inter-tier vias, network on chip, system on chip, through silicon vias, three dimensional integration circuits

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Authors: Man Wai Lei, Charles Mark Zaroff

Abstract:

Objective: A majority of studies suggest that people with Autism Spectrum Disorder (ASD) have multisensory integration deficits. However, normal and even supranormal multisensory integration abilities have also been reported. Additionally, little of this work has been undertaken utilizing a dimensional conceptualization of ASD; i.e., a broader autism phenotype. Utilizing methodology that controls for common potential confounds, the current study aimed to examine if deficits in multisensory integration are associated with ASD traits in a non-clinical population. The contribution of affective versus non-affective components of sensory hypersensitivity to multisensory integration was also examined. Methods: Participants were 147 undergraduate university students in Macau, a Special Administrative Region of China, of Chinese ethnicity, aged 16 to 21 (Mean age = 19.13; SD = 1.07). Participants completed the Autism-Spectrum Quotient, the Sensory Perception Quotient, and the Adolescent/Adult Sensory Profile, in order to measure ASD traits, non-affective, and affective aspects of sensory/perceptual hypersensitivity, respectively. In order to explore multisensory integration across visual and haptic domains, participants were asked to judge which one of two equally weighted, but different sized cylinders was heavier, as a means of detecting the presence of the size-weight illusion (SWI). Results: ASD trait level was significantly and negatively correlated with susceptibility to the SWI (p < 0.05); this correlation was not associated with either accuracy in weight discrimination or gender. Examining the top decile of the non-normally distributed SWI scores revealed a significant negative association with sensation avoiding, but not other aspects of effective or non-effective sensory hypersensitivity. Conclusion and Implications: Within the normal population, a greater degree of ASD traits is associated with a lower likelihood of multisensory integration; echoing was often found in individuals with a clinical diagnosis of ASD, and providing further evidence for the dimensional nature of this disorder. This tendency appears to be associated with dysphoric emotional reactions to sensory input.

Keywords: Autism Spectrum Disorder, dimensional, multisensory integration, size-weight illusion

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Authors: Su Yin Chiam, Qing Xin Zhang, Jaehoon Chung

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Complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) have obtained increased attention in the biosensor community because CMOS technology provides cost-effective and high-performance signal processing at a mass-production level. In order to supply biological samples and reagents effectively to the sensing elements, there are increasing demands for seamless integration of microfluidic components on the fabricated CMOS wafers by post-processing. Although the PDMS microfluidic channels replicated from separately prepared silicon mold can be typically aligned and bonded onto the CMOS wafers, it remains challenging owing the inherently limited aligning accuracy ( > ± 10 μm) between the two layers. Here we present a new post-processing method to create three-dimensional microfluidic components using two different polarities of photoresists, an epoxy-based negative SU-8 photoresist and positive SPR220-7 photoresist. The positive photoresist serves as a sacrificial layer and the negative photoresist was utilized as a structural material to generate three-dimensional structures. Because both photoresists are patterned using a standard photolithography technology, the dimensions of the structures can be effectively controlled as well as the alignment accuracy, moreover, is dramatically improved (< ± 2 μm) and appropriately can be adopted as an alternative post-processing method. To validate the proposed processing method, we applied this technique to build cell-trapping structures. The SU8 photoresist was mainly used to generate structures and the SPR photoresist was used as a sacrificial layer to generate sub-channel in the SU8, allowing fluid to pass through. The sub-channel generated by etching the sacrificial layer works as a cell-capturing site. The well-controlled dimensions enabled single-cell capturing on each site and high-accuracy alignment made cells trapped exactly on the sensing units of CMOS biosensors.

Keywords: SU-8, microfluidic, MEMS, microfabrication

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Authors: J. Hajri, H. Hrizi, N. Sboui, H. Baudrand

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This paper presents a study of SIW circuits (Substrate Integrated Waveguide) with a rigorous and fast original approach based on Iterative process (WCIP). The theoretical suggested study is validated by the simulation of two different examples of SIW circuits. The obtained results are in good agreement with those of measurement and with software HFSS.

Keywords: convergence study, HFSS, modal decomposition, SIW circuits, WCIP method

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Authors: Shiang-Hwua Yu, Po-Hsun Wu

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This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier.

Keywords: self-oscillation, sigma-delta modulator, pendulum clock, Coulomb friction, class-D amplifier

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Authors: Mohamad Baqer Heidari, Hefzollah.Mohammadian

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This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

Keywords: analog signal processing, current-mode operation, functional core, multiplier, reconfigurable circuits, industrial package systems

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Authors: Hasan Çiçekli, Ahmet Gökçen, Uğur Çam

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In this paper, a comparative performance analysis of mostly used four nonlinearity cancellation techniques used to realize the passive resistor by MOS transistors is presented. The comparison is done by using an integrator circuit which is employing sequentially Op-amp, OTRA and ICCII as active element. All of the circuits are implemented by MOS-C realization and simulated by PSPICE program using 0.35 µm process TSMC MOSIS model parameters. With MOS-C realization, the circuits became electronically tunable and fully integrable which is very important in IC design. The output waveforms, frequency responses, THD analysis results and features of the nonlinearity cancellation techniques are also given.

Keywords: integrator circuits, MOS-C realization, nonlinearity cancellation, tuneable resistors

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Authors: Masaya Yoshikawa, Toshiya Asai, Ryoma Matsuhisa, Yusuke Nozaki, Kensaku Asahi

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Recently, side-channel attacks, which estimate secret keys using side-channel information such as power consumption and compromising emanations of cryptography circuits embedded in hardware, have become a serious problem. In particular, electromagnetic analysis attacks against cryptographic circuits between information processing and electromagnetic fields, which are related to secret keys in cryptography circuits, are the most threatening side-channel attacks. Therefore, it is important to evaluate tamper resistance against electromagnetic analysis attacks for cryptography circuits. The present study performs basic examination of the tamper resistance of cryptography circuits using electromagnetic analysis attacks with noise resources.

Keywords: tamper resistance, cryptographic circuit, hardware security evaluation, noise resources

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Authors: Nahla Elazab, Mohamed Aboudina, Ghada Ibrahim, Hossam Fahmy, Ahmed Khalil

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This paper presents the developed memristor based demodulators for eight circular Quadrature Amplitude Modulation (QAM) and Binary Frequency Shift Keying (BFSK) operating at relatively high frequency. In our implementations, the experimental-based ‘nonlinear’ dopant drift model is adopted along with the proposed circuits providing incorporation of all known non-idealities of practically realized memristor and gaining high operation frequency. The suggested designs leverage the distinctive characteristics of the memristor device, definitely, its changeable average memristance versus the frequency, phase and amplitude of the periodic excitation input. The proposed demodulators feature small integration area, low power consumption, and easy implementation. Moreover, the proposed QAM demodulator precludes the requirement for the carrier recovery circuits. In doing so, the designs were validated by transient simulations using the nonlinear dopant drift memristor model. The simulations results show high agreement with the theory presented.

Keywords: BFSK, demodulator, high frequency memristor applications, memristor based analog circuits, nonlinear dopant drift model, QAM

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Authors: Ching-Feng Chen, Ching-Chih Tsai

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With the size of the transistor gradually approaching the physical limit, it challenges the persistence of Moore’s Law due to the development of the high numerical aperture (high-NA) lithography equipment and other issues such as short channel effects. In the context of the ever-increasing technical requirements of portable devices and high-performance computing, relying on the law continuation to enhance the chip density will no longer support the prospects of the electronics industry. Weighing the chip’s power consumption-performance-area-cost-cycle time to market (PPACC) is an updated benchmark to drive the evolution of the advanced wafer nanometer (nm). The advent of two and half- and three-dimensional (2.5 and 3D)- Very-Large-Scale Integration (VLSI) packaging based on Through Silicon Via (TSV) technology has updated the traditional die assembly methods and provided the solution. This overview investigates the up-to-date and cutting-edge packaging technologies for 2.5D and 3D integrated circuits (ICs) based on the updated transistor structure and technology nodes. The author concludes that multi-chip solutions for 2.5D and 3D IC packagings are feasible to prolong Moore’s Law.

Keywords: moore’s law, high numerical aperture, power consumption-performance-area-cost-cycle time to market, 2.5 and 3D- very-large-scale integration, packaging, through silicon via

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Authors: Jurriaan Gillissen

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This work is concerned with stabilizing the numerical integration of the Navier-Stokes equation (NSE), backwards in time. Applications involve the detection of sources of, e.g., sound, heat, and pollutants. Stable reverse numerical integration of parabolic differential equations is also relevant for image de-blurring. While the literature addresses the reverse integration problem of the advection-diffusion equation, the problem of numerical reverse integration of the NSE has, to our knowledge, not yet been addressed. Owing to the presence of viscosity, the NSE is irreversible, i.e., when going backwards in time, the fluid behaves, as if it had a negative viscosity. As an effect, perturbations from the perfect solution, due to round off errors or discretization errors, grow exponentially in time, and reverse integration of the NSE is inherently unstable, regardless of using an implicit time integration scheme. Consequently, some sort of filtering is required, in order to achieve a stable, numerical, reversed integration. The challenge is to find a filter with a minimal adverse affect on the accuracy of the reversed integration. In the present work, we explore an adjoint gradient method (AGM) to achieve this goal, and we apply this technique to two-dimensional (2D), decaying turbulence. The AGM solves for the initial velocity field u0 at t = 0, that, when integrated forward in time, produces a final velocity field u1 at t = 1, that is as close as is feasibly possible to some specified target field v1. The initial field u0 defines a minimum of a cost-functional J, that measures the distance between u1 and v1. In the minimization procedure, the u0 is updated iteratively along the gradient of J w.r.t. u0, where the gradient is obtained by transporting J backwards in time from t = 1 to t = 0, using the adjoint NSE. The AGM thus effectively replaces the backward integration by multiple forward and backward adjoint integrations. Since the viscosity is negative in the adjoint NSE, each step of the AGM is numerically stable. Nevertheless, when applied to turbulence, the AGM develops instabilities, which limit the backward integration to small times. This is due to the exponential divergence of phase space trajectories in turbulent flow, which produces a multitude of local minima in J, when the integration time is large. As an effect, the AGM may select unphysical, noisy initial conditions. In order to improve this situation, we propose two remedies. First, we replace the integration by a sequence of smaller integrations, i.e., we divide the integration time into segments, where in each segment the target field v1 is taken as the initial field u0 from the previous segment. Second, we add an additional term (regularizer) to J, which is proportional to a high-order Laplacian of u0, and which dampens the gradients of u0. We show that suitable values for the segment size and for the regularizer, allow a stable reverse integration of 2D decaying turbulence, with accurate results for more then O(10) turbulent, integral time scales.

Keywords: time reversed integration, parabolic differential equations, adjoint gradient method, two dimensional turbulence

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Authors: Patikineti Sreenivasulu, K. srinivasa Rao, A. Vinaya Babu

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The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits.

Keywords: power consumption, ultra-low power, leakage, sub threshold, MTCMOS

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Authors: Juhi Faridi, Mohd. Ajmal Kafeel

Abstract:

The advancements in the field of Artificial Intelligence (AI) and technology has led to an evolution of an intelligent era. Neural networks, having the computational power and learning ability similar to the brain is one of the key AI technologies. Neuromorphic computing system (NCS) consists of the synaptic device, neuronal circuit, and neuromorphic architecture. Memristor are a promising candidate for neuromorphic computing systems, but when it comes to neuromorphic computing, the conductance behavior of the synaptic memristor or neuronal memristor needs to be studied thoroughly in order to fathom the neuroscience or computer science. Furthermore, there is a need of more simulation work for utilizing the existing device properties and providing guidance to the development of future devices for different performance requirements. Hence, development of NCS needs more simulation work to make use of existing device properties. This work aims to provide an insight to build neuronal circuits using memristors to achieve a Memristor based NCS.  Here we throw a light on the research conducted in the field of memristors for building analog and digital circuits in order to motivate the research in the field of NCS by building memristor based neural circuits for advanced AI applications. This literature is a step in the direction where we describe the various Key findings about memristors and its analog and digital circuits implemented over the years which can be further utilized in implementing the neuronal circuits in the NCS. This work aims to help the electronic circuit designers to understand how the research progressed in memristors and how these findings can be used in implementing the neuronal circuits meant for the recent progress in the NCS.

Keywords: analog circuits, digital circuits, memristors, neuromorphic computing systems

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Authors: Mudavath Raju, Bhaskar Gugulothu, B. Rajendra Naik

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The rapid advances in Very Large Scale Integration (VLSI) technology has resulted in the reduction of minimum feature size to sub-quarter microns and switching time in tens of picoseconds or even less. As a result, the degradation of high-speed digital circuits due to signal integrity issues such as coupling effects, clock feedthrough, crosstalk noise and delay uncertainty noise. Crosstalk noise in VLSI interconnects is a major concern and reduction in VLSI interconnect has become more important for high-speed digital circuits. It is the most effectively considered in Deep Sub Micron (DSM) and Ultra Deep Sub Micron (UDSM) technology. Increasing spacing in-between aggressor and victim line is one of the technique to reduce the crosstalk. Guard trace or shield insertion in-between aggressor and victim is also one of the prominent options for the minimization of crosstalk. In this paper, far end crosstalk noise is estimated with mutual inductance and capacitance RLC interconnect model. Also investigated the extent of crosstalk in capacitive and inductively coupled interconnects to minimizes the same through shield insertion technique.

Keywords: VLSI, interconnects, signal integrity, crosstalk, shield insertion, guard trace, deep sub micron

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Authors: N. Ourabia, M. Boubaker Ourabia

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An approach for modeling and numerical simulation of passive planar structures using the edge line concept is developed. With this method, we develop an efficient modeling technique for microstrip discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then, it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources.

Keywords: optimization, CAD analysis, microwave circuits, S-parameters

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Authors: S. Y. Cicekli

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In this study, tree-dimensional model of tree was created by using terrestrial close range photogrammetry. For this close range photos were taken. Photomodeler Pro 5 software was used for camera calibration and create three-dimensional model of trees. In first test, three-dimensional model of a tree was created, in the second test three-dimensional model of three trees were created. This study aim is creating three-dimensional model of trees and indicate the use of close-range photogrammetry in forestry. At the end of the study, three-dimensional model of tree and three trees were created. This study showed that usability of close-range photogrammetry for monitoring tree and forests three-dimensional model.

Keywords: close- range photogrammetry, forest, tree, three-dimensional model

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Authors: Fuyang Peng, Donghong Li

Abstract:

The aim of information systems integration is to make all the data sources, applications and business flows integrated into the new environment so that unwanted redundancies are reduced and bottlenecks and mismatches are eliminated. Two issues have to be dealt with to meet such requirements: the software architecture that supports resource integration, and the adaptor development tool that help integration and migration of legacy applications. In this paper, a service-enabled dependable integration environment (SDIE), is presented, which has two key components, i.e., a dependable service integration platform and a legacy application integration tool. For the dependable platform for service integration, the service integration bus, the service management framework, the dependable engine for service composition, and the service registry and discovery components are described. For the legacy application integration tool, its basic organization, functionalities and dependable measures taken are presented. Due to its service-oriented integration model, the light-weight extensible container, the service component combination-oriented p-lattice structure, and other features, SDIE has advantages in openness, flexibility, performance-price ratio and feature support over commercial products, is better than most of the open source integration software in functionality, performance and dependability support.

Keywords: application integration, dependability, legacy, SOA

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Authors: Khlif Hamadi

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Supply chain integration has become a potentially valuable way of securing shared information and improving supply chain performance since competition is no longer between organizations but among supply chains. This research conceptualizes and develops three dimensions of supply chain integration (integration with customers, integration with suppliers, and the interorganizational integration) and tests the relationships between supply chain integration, information sharing, and supply chain performance. Furthermore, the four types of information sharing namely; information sharing with customers, information sharing with suppliers, inter-functional information sharing, and intra-organizational information sharing; and the four constructs of Supply Chain Performance represents expenses of costs, asset utilization, supply chain reliability, and supply chain flexibility and responsiveness. The theoretical and practical implications of the study, as well as directions for future research, are discussed.

Keywords: supply chain integration, supply chain management, information sharing, supply chain performance

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Authors: Ahmed Moulay, Mariia Zhuldybina, Mirko Torres, Mike Rozel, Ngoc Duc Trinh, Chloé Bois

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Hybrid printed electronics technology (HPE) provides innovative opportunities to enhance conventional electronics applications, which are often based on printed circuit boards (PCB). By combining the best of both performance from conventional electronic components and the flexibility from printed circuits makes it possible to manufacture HPE at high volumes using roll-to-roll printing processes. However, several challenges must be overcome in order to accurately integrate an electronic component on a printed circuit. In this presentation, we will demonstrate the integration process of electronic components from the lab scale to the industrialization. Both the printing quality and the integration technique must be studied to define the optimal conditions. To cover the parameters that influence the print quality of the printed circuit, different printing processes, flexible substrates, and conductive inks will be used to determine the optimized printing process/ink/substrate system. After the systems is selected, an electronic component of 2.5 mm2 chip size will be integrated to validate the functionality of the printed, electronic circuit. Critical information such as the conductive adhesive, the curing conditions, and the chip encapsulation will be determined. Thanks to these preliminary results, we are able to demonstrate the chip integration on a printed circuit using industrial equipment, showing the potential of industrialization, compatible using roll-to-roll printing and integrating processes.

Keywords: flat bed screen-printing, hybrid printed electronics, integration, large-scale production, roll-to-roll printing, rotary screen printing

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Authors: Vanessa Funk, Steven Blum, Stephanie Cole, Jorge Maciel, Matthew Lux

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Paper-based synthetic gene circuits offer a new paradigm for programmable, fieldable biodetection. We demonstrate that by freeze-drying gene circuits with in vitro expression machinery, we can use complimentary RNA sequences to trigger colorimetric changes upon rehydration. We have successfully utilized both green fluorescent protein and luciferase-based reporters for easy visualization purposes in solution. Through several efforts, we are aiming to use this new platform technology to address a variety of needs in portable detection by demonstrating several more expression and reporter systems for detection functions on paper. In addition to RNA-based biodetection, we are exploring the use of various mechanisms that cells use to respond to environmental conditions to move towards all-hazards detection. Examples include explosives, heavy metals for water quality, and toxic chemicals.

Keywords: cell-free lysates, detection, gene circuits, in vitro

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Authors: Abdelhamid Zerroug, Mlle Ismahene Sehili

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Spectral methods are usually applied to solve uni-dimensional boundary value problems. With the advantage of the creation of multidimensional basis, we propose a new spectral method for bi-dimensional problems. In this article, we start by creating bi-spectral basis by different ways, we developed also a new relations to determine the expressions of spectral coefficients in different partial derivatives expansions. Finally, we propose the principle of a new bi-spectral method for the bi-dimensional problems.

Keywords: boundary value problems, bi-spectral methods, bi-dimensional Legendre basis, spectral method

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Authors: S. Summart, C. Saetiaw, T. Thosdeekoraphat, C. Thongsopa

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This article presents new current-mode oscillator circuits using CDTAs which is designed from block diagram. The proposed circuits consist of two CDTAs and two grounded capacitors. The condition of oscillation and the frequency of oscillation can be adjusted by electronic method. The circuits have high output impedance and use only grounded capacitors without any external resistor which is very appropriate to future development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis.

Keywords: current-mode, quadrature oscillator, block diagram, CDTA

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Authors: Mir Shahriar Emami

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Although it is fully impossible to ensure that a software system is quite secure, developing an acceptable secure software system in a convenient platform is not unreachable. In this paper, we attempt to analyze software development life cycle (SDLC) models from the hardware systems and circuits point of view. To date, the SDLC models pay merely attention to the software security from the software perspectives. In this paper, we present new features for SDLC stages to emphasize the role of systems and circuits in developing secure software system through the software development stages, the point that has not been considered previously in the SDLC models.

Keywords: SDLC, SSDLC, software security, software process engineering, hardware systems and circuits security

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Authors: Sujit K. Basak, Simon Collin

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The aim of this paper is to examine the technology access and use on the affecting social integration of local students at university. This aim is achieved by designing a structural equation modeling (SEM) in terms of integration with peers, integration with faculty, faculty support and on the other hand, examining the socio demographic impact on the technology access and use. The collected data were analyzed using the WarpPLS 5.0 software. This study was survey based and it was conducted at a public university in Canada. The results of the study indicated that technology has a strong impact on integration with faculty, faculty support, but technology does not have an impact on integration with peers. However, the social demographic has also an impact on the technology access and use.

Keywords: faculty, integration, peer, technology access and use

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Authors: Meng Miao, Jeongwoo Han, Cam Nguyen

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Ultra-wideband (UWB) time-domain impulse communication and radar systems use ultra-short duration pulses in the sub-nanosecond regime, instead of continuous sinusoidal waves, to transmit information. The pulse directly generates a very wide-band instantaneous signal with various duty cycles depending on specific usages. In UWB systems, the total transmitted power is spread over an extremely wide range of frequencies; the power spectral density is extremely low. This effectively results in extremely small interference to other radio signals while maintains excellent immunity to interference from these signals. UWB devices can therefore work within frequencies already allocated for other radio services, thus helping to maximize this dwindling resource. Therefore, impulse UWB technique is attractive for realizing high-data-rate, short-range communications, ground penetrating radar (GPR), and military radar with relatively low emission power levels. UWB antennas are the key element dictating the transmitted and received pulse shape and amplitude in both time and frequency domain. They should have good impulse response with minimal distortion. To facilitate integration with transmitters and receivers employing microwave integrated circuits, UWB antennas enabling direct integration are preferred. We present the development of two UWB antennas operating from 3.1 to 10.6 GHz and 0.3-6 GHz for UWB systems that provide direct integration with microwave integrated circuits. The operation of these antennas is based on the principle of wave propagation on a non-uniform transmission line. Time-domain EM simulation is conducted to optimize the antenna structures to minimize reflections occurring at the open-end transition. Calculated and measured results of these UWB antennas are presented in both frequency and time domains. The antennas have good time-domain responses. They can transmit and receive pulses effectively with minimum distortion, little ringing, and small reflection, clearly demonstrating the signal fidelity of the antennas in reproducing the waveform of UWB signals which is critical for UWB sensors and communication systems. Good performance together with seamless microwave integrated-circuit integration makes these antennas good candidates not only for UWB applications but also for integration with printed-circuit UWB transmitters and receivers.

Keywords: antennas, ultra-wideband, UWB, UWB communication systems, UWB radar systems

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Authors: Meng Su

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High-dimensional data analysis often presents challenges in capturing the complex, nonlinear relationships and manifold structures inherent to the data. This article presents a novel approach that leverages the strengths of two powerful techniques, Diffusion Maps and Diffusion Probabilistic Models (DPMs), to address these challenges. By integrating the dimensionality reduction capability of Diffusion Maps with the data modeling ability of DPMs, the proposed method aims to provide a comprehensive solution for analyzing and generating high-dimensional data. The Diffusion Map technique preserves the nonlinear relationships and manifold structure of the data by mapping it to a lower-dimensional space using the eigenvectors of the graph Laplacian matrix. Meanwhile, DPMs capture the dependencies within the data, enabling effective modeling and generation of new data points in the low-dimensional space. The generated data points can then be mapped back to the original high-dimensional space, ensuring consistency with the underlying manifold structure. Through a detailed example implementation, the article demonstrates the potential of the proposed hybrid approach to achieve more accurate and effective modeling and generation of complex, high-dimensional data. Furthermore, it discusses possible applications in various domains, such as image synthesis, time-series forecasting, and anomaly detection, and outlines future research directions for enhancing the scalability, performance, and integration with other machine learning techniques. By combining the strengths of Diffusion Maps and DPMs, this work paves the way for more advanced and robust data analysis methods.

Keywords: diffusion maps, diffusion probabilistic models (DPMs), manifold learning, high-dimensional data analysis

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Authors: D. Ponnamma, E. Alper, P. Sharma, M. A. AlMaadeed

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Integrating efficient energy harvesting materials into soft, flexible and eco-friendly substrates could yield significant breakthroughs in wearable and flexible electronics. Here we present a tri phasic filler combination of one-dimensional titanium dioxide nanotubes, two-dimensional reduced graphene oxide, and three-dimensional strontium titanate, introduced into a semi crystalline polymer, Poly(vinylidene fluoride-co-hexafluoropropylene). Simple mixing method is adopted for the composite fabrication after ensuring a high interaction among the various fillers. The films prepared were mainly tested for the piezoelectric responses and the mechanical stretchability. The results show that the piezoelectric constant has increased while changing the total filler concentration. We propose an integration of these materials in fabricating energy conversion devices useful in flexible and wearable electronics.

Keywords: dielectric property, hydrothermal growth, piezoelectricity, polymer nanocomposites

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