Search results for: field effect transistor

Authors: Sang Hoon Lee, Tae Il Lee, Su Jeong Lee, Jae Min Myoung

Abstract:

In order to manufacture short gap single Si nanowire (NW) field effect transistor (FET) by imprinting and transferring method, we introduce the method using Al2O3 sacrificial layer. The diameters of cylindrical Si NW addressed between Au electrodes by dielectrophoretic (DEP) alignment method are controlled to 106, 128, and 148 nm. After imprinting and transfer process, cylindrical Si NW is embedded in PVP adhesive and dielectric layer. By curing transferred cylindrical Si NW and Au electrodes on PVP-coated p++ Si substrate with 200nm-thick SiO2, 3μm gap Si NW FET fabrication was completed. As the diameter of embedded Si NW increases, the mobility of FET increases from 80.51 to 121.24 cm2/V•s and the threshold voltage moves from –7.17 to –2.44 V because the ratio of surface to volume gets reduced.

Keywords: Al2O3 sacrificial transfer layer, cylindrical silicon nanowires, dielectrophorestic alignment, field effect transistor

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Authors: Jingqi Li

Abstract:

A new vertical carbon nanotube field effect transistor (CNTFET) has been developed. The source, drain and gate are vertically stacked in this structure. The carbon nanotubes are put on the side wall of the vertical stack. Unique transfer characteristics which depend on both silicon type and the sign of drain voltage have been observed in silicon integrated CNTFETs. The significant advantage of this CNTFET is that the short channel of the transistor can be fabricated without using complicate lithography technique.

Keywords: carbon nanotubes, field-effect transistors, electrical property, short channel fabrication

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Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, kink effect

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Authors: M. Kessi

Abstract:

We investigated the effect of the magnetic field on carrier transport phenomena in the transistor channel region of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). This explores the Lorentz force and basic physical properties of solids exposed to a constant external magnetic field. The magnetic field modulates the electrons and potential distribution in the case of silicon Tunnel FETs. This modulation shows up in the device's external electrical characteristics such as ON current (ION), subthreshold leakage current (IOF), the threshold voltage (VTH), the magneto-transconductance (gm) and the output magneto-conductance (gDS) of Tunnel FET. Moreover, the channel doping concentration and potential distribution are obtained using the numerical method by solving Poisson’s transport equation in 3D modules semiconductor magnetic sensors available in Silvaco TCAD tools. The numerical simulations of the magnetic nano-sensors are relatively new. In this work, we present the results of numerical simulations based on 3D magnetic sensors. The results show excellent accuracy comportment and good agreement compared with that obtained in the experimental study of MOSFETs technology.

Keywords: single-gate MOSFET, magnetic field, hall field, Lorentz force

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Authors: Mehdi Saeidmanesh, Razali Ismail

Abstract:

Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: graphene nanoribbon, field effect transistors, short channel effects, channel length modulation

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Authors: P. Geetha, R. S. D. Wahida Banu

Abstract:

The crowning advances in Silicon based electronic technology have dominated the computation world for the past decades. The captivating performance of Si devices lies in sustainable scaling down of the physical dimensions, by that increasing device density and improved performance. But, the fundamental limitations due to physical, technological, economical, and manufacture features restrict further miniaturization of Si based devices. The pit falls are due to scaling down of the devices such as process variation, short channel effects, high leakage currents, and reliability concerns. To fix the above-said problems, it is needed either to follow a new concept that will manage the current hitches or to support the available concept with different materials. The new concept is to design spintronics, quantum computation or two terminal molecular devices. Otherwise, presently used well known three terminal devices can be modified with different materials that suits to address the scaling down difficulties. The first approach will occupy in the far future since it needs considerable effort; the second path is a bright light towards the travel. Modelling paves way to know not only the current-voltage characteristics but also the performance of new devices. So, it is desirable to model a new device of suitable gate control and project the its abilities towards capability of handling high current, high power, high frequency, short delay, and high velocity with excellent electronic and optical properties. Carbon nanotube became a thriving material to replace silicon in nano devices. A well-planned optimized utilization of the carbon material leads to many more advantages. The unique nature of this organic material allows the recent developments in almost all fields of applications from an automobile industry to medical science, especially in electronics field-on which the automation industry depends. More research works were being done in this area. This paper reviews the carbon nanotube field effect transistor with various gate configurations, number of channel element, CNT wall configurations and different modelling techniques.

Keywords: array of channels, carbon nanotube field effect transistor, double gate transistor, gate wrap around transistor, modelling, multi-walled CNT, single-walled CNT

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Authors: Debabrata Bhadra, B. K. Chaudhuri

Abstract:

The operation of organic thin film transistors (OFETs) with low voltage is currently a prevailing issue. We have fabricated anthracene thin-film transistor (TFT) with an ultrathin layer (~450nm) of Poly-vinylidene fluoride (PVDF)/CuO nanocomposites as a gate insulator. We obtained a device with excellent electrical characteristics at low operating voltages (<1V). Different layers of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constant (εr ). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films were investigated. This device was found to have highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of 0.34V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such favorable combination of properties means that these OFETs can be utilized successfully as voltages below 1V. A very simple fabrication process has been used along with step wise poling process for enhancing the pyroelectric effects on the device performance. The output characteristic of OFET after poling were changed and exhibited linear current-voltage relationship showing the evidence of large polarization. The temperature dependent response of the device was also investigated. The stable performance of the OFET after poling operation makes it reliable in temperature sensor applications. Such High-ε CuO/PVDF gate dielectric appears to be highly promising candidates for organic non-volatile memory and sensor field-effect transistors (FETs).

Keywords: organic field effect transistors, thin film transistor, gate dielectric, organic semiconductor

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Authors: Manasa Kalla, Narasimha Raju Chebrolu, Ashok Chatterjee

Abstract:

We have studied the quantum transport properties of a single molecular transistor in the presence of an external magnetic field using the Keldysh Green function technique. We also used the Anderson-Holstein-Caldeira-Leggett Model to describe the single molecular transistor that consists of a molecular quantum dot (QD) coupled to two metallic leads and placed on a substrate that acts as a heat bath. The phonons are eliminated by the Lang-Firsov transformation and the effective Hamiltonian is used to study the effect of an external magnetic field on the spectral density function, Tunneling Current, Differential Conductance and Spin polarization. A peak in the spectral function corresponds to a possible excitation. In the presence of a magnetic field, the spin-up and spin-down states are degenerate and this degeneracy is lifted by the magnetic field leading to the splitting of the central peak of the spectral function. The tunneling current decreases with increasing magnetic field. We have observed that even the differential conductance peak in the zero magnetic field curve is split in the presence electron-phonon interaction. As the magnetic field is increased, each peak splits into two peaks. And each peak indicates the existence of an energy level. Thus the number of energy levels for transport in the bias window increases with the magnetic field. In the presence of the electron-phonon interaction, Differential Conductance in general gets reduced and decreases faster with the magnetic field. As magnetic field strength increases, the spin polarization of the current is increasing. Our results show that a strongly interacting QD coupled to metallic leads in the presence of external magnetic field parallel to the plane of QD acts as a spin filter at zero temperature.

Keywords: Anderson-Holstein model, Caldeira-Leggett model, spin-polarization, quantum dots

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Authors: Su Jeong Lee, Tae Il Lee, Jung Han Kim, Chul-Hong Kim, Gee Sung Chae, Jae-Min Myoung

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The contact resistance between source/drain electrodes and semiconductor layer is an important parameter affecting electron transporting performance in the thin film transistor (TFT). In this work, we introduced a transparent and the solution prossable single-walled carbon nanotube (SWCNT)/Al-doped ZnO nano particle (AZO NP) bilayer electrodes showing low contact resistance with indium-oxide (In2O3) sol gel thin film. By inserting low work function AZO NPs into the interface between the SWCNTs and the In2O3 which has a high energy barrier, we could obtain an electrical Ohmic contact between them. Finally, with the SWCNT-AZO NP bilayer electrodes, we successfully fabricated a TFT showing a field effect mobility of 5.38 cm2/V∙s at 250 °C.

Keywords: single-walled carbon nanotube (SWCNT), Al-doped ZnO (AZO) nanoparticle, contact resistance, thin-film transistor (TFT)

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Authors: Ashwani Kumar

Abstract:

Abstract- This study presents an analytical modeling approach for analyzing the drain current behavior in Tunnel Field-Effect Transistor (TFET) biosensors used for the detection of DNA biomolecules. The proposed model focuses on elucidating the relationship between the drain current and the presence of DNA biomolecules, taking into account the impact of various device parameters and biomolecule characteristics. Through comprehensive analysis, the model offers insights into the underlying mechanisms governing the sensing performance of TFET biosensors, aiding in the optimization of device design and operation. A non-local tunneling model is incorporated with other essential models to accurately trace the simulation and modeled data. An experimental validation of the model is provided, demonstrating its efficacy in accurately predicting the drain current response to DNA biomolecule detection. The sensitivity attained from the analytical model is compared and contrasted with the ongoing research work in this area.

Keywords: biosensor, double-gate TFET, DNA detection, drain current modeling, sensitivity

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Authors: Muhamad Azuddin Hassan, Siti Shafura Karim, Ambri Mohamed, Iskandar Yahya

Abstract:

Human serum albumin plays a significant part in the physiological functions of the human body system (HSA).HSA level monitoring is critical for early detection of HSA-related illnesses. The goal of this study is to show that a field effect transistor (FET)-based immunosensor can assess HSA using high aspect ratio carbon nanotubes network (CNT) as a transducer. The CNT network were deposited using air brush technique, and the FET device was made using a shadow mask process. Field emission scanning electron microscopy and a current-voltage measurement system were used to examine the morphology and electrical properties of the CNT network, respectively. X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy were used to confirm the surface alteration of the CNT. The detection process is based on covalent binding interactions between an antibody and an HSA target, which resulted in a change in the manufactured biosensor's drain current (Id).In a linear range between 1 ng/ml and 10zg/ml, the biosensor has a high sensitivity of 0.826 mA (g/ml)-1 and a LOD value of 1.9zg/ml.HSA was also identified in a genuine serum despite interference from other biomolecules, demonstrating the CNT-FET immunosensor's ability to quantify HSA in a complex biological environment.

Keywords: carbon nanotubes network, biosensor, human serum albumin

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Salleh, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics

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Authors: Lin Gong, Holger Göbel

Abstract:

In the present study, we have investigated the influence of UV/ozone treatment on pentacene-based organic field effect transistors (OFETs) with a bilayer gate dielectric. The OFETs for this study were fabricated on heavily n-doped Si substrates with a thermally deposited SiO2 dielectric layer (300nm). On the SiO2 dielectric a very thin (≈ 15nm) buffer layer of polystyrene (PS) was first spin-coated and then treated by UV/ozone to modify the surface prior to the deposition of pentacene. We found out that by extending the UV/ozone treatment time the threshold voltage of the OFETs was monotonically shifted towards positive values, whereas the field effect mobility first decreased but eventually reached a stable value after a treatment time of approximately thirty seconds. Since the field effect mobility of the UV/ozone treated bilayer OFETs was found to be higher than the value of a comparable transistor with a single layer dielectric, we propose that the bilayer (SiO2/PS) structure can be used to shift the threshold voltage to a desired value without sacrificing field effect mobility.

Keywords: buffer layer, organic field effect transistors, threshold voltage, UV/ozone treatment

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

Abstract:

This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

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Authors: Mohammad Hosseini

Abstract:

Ultrafast transistor laser investigated here has the graded index separate confinement heterostructure (GRIN-SCH) in its base region. Resonance-free optical frequency response with -3dB bandwidth of more than 26 GHz has been achieved for a single quantum well transistor laser by using graded index layers of AlξGa1-ξAs (ξ: 0.1→0) on the left side of the quantum well and AlξGa1-ξAs (ξ: 0.05→0) in the right side of quantum well. All required parameters, including quantum well and base transit time, optical confinement factor and spontaneous recombination lifetime, have been calculated using a self-consistent charge control model.

Keywords: transistor laser, ultrafast, GRIN-SCH, -3db optical bandwidth, AlξGa1-ξAs

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Authors: Peihao Huang, Chun Zhao

Abstract:

Thin-film transistors(TFTs) have the advantages of low power consumption, short reaction time, and have high research value in the field of semiconductors, based on this reason, people have focused on gallium oxide-indium oxide thin-film transistors, a relatively common thin-film transistor, elaborated and analyzed his production process, "aqueous solution method", explained the purpose of each step of operation, and finally explored the influence of potassium ions doped in the channel layer on the electrical properties of the device, as well as the effect of oxygen vacancies on its switching ratio and memory, and summarized the conclusions.

Keywords: aqueous solution, oxygen vacancies, switch ratio, thin-film transistor(TFT)

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Authors: A. N. Moulai Khatir

Abstract:

SOI-Multifin-FETs are placed to be the workhorse of the industry for the coming few generations, and thus, in a few years because their excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation, and negligible body bias dependency. The corner effect may also exist in the two lower corners; this effect is called the BOX effect, which can also occur in the direction X-Z. The electric field lines from the source and drain cross the bottom oxide and arrive in the silicon. This effect is also called DIVSB (Drain Induced Virtual Substrate Basing). The potential in the silicon film in particular near the drain is increased by the drain bias. It is similar to DIBL and result in a decrease of the threshold voltage. This work provides an understanding of the limitation of this effect by reducing the fin width for components with increased fin number.

Keywords: SOI, finFET, corner effect, dual-gate, tri-gate, BOX, multi-finFET

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Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

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In this paper, the transient device performance analysis of n-type Gate Inside Junctionless Transistor (GIJLT)has been evaluated. 3-D Bohm Quantum Potential (BQP)transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor(TGF) and unity gain cut-off frequency (fT) and subthreshold slope (SS) of the GI-JLT and Gate-all-around junctionless transistor(GAA-JLT) have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: gate-inside junctionless transistor GI-JLT, gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product

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Authors: Suruchi Saini, Hitender Kumar Tyagi

Abstract:

With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively.

Keywords: current on-off ratio, FinFET, short-channel effects, transconductance

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Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, inverter modeling, transistor current mode, timing model

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Authors: Nikhil Jain, Bin Yu

Abstract:

We explore the potential of using ultra-thin hexagonal boron nitride (h-BN) as both supporting substrate and gate dielectric for graphene-channel field effect transistors (GFETs). Different from commonly used oxide-based dielectric materials which are typically amorphous, very rough in surface, and rich with surface traps, h-BN is layered insulator free of dangling bonds and surface states, featuring atomically smooth surface. In a graphene-channel-last device structure with local buried metal gate electrode (TiN), thin h-BN multilayer is employed as both supporting “substrate” and gate dielectric for graphene active channel. We observed superior carrier mobility and electrical conduction, significantly improved from that in GFETs with SiO2 as substrate/gate insulator. In addition, we report excellent dielectric behavior of layered h-BN, including ultra-low leakage current and high critical electric field for breakdown.

Keywords: graphene, field-effect transistors, hexagonal boron nitride, dielectric strength, tunneling

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Authors: T. Bielewicz, S. Dogan, C. Klinke

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Two-dimensional, solution-processable semiconductor materials are interesting for low-cost electronic applications [1]. We demonstrate the synthesis of lead sulfide nanosheets and how their size, shape and height can be tuned by varying concentrations of pre-cursors, ligands and by varying the reaction temperature. Especially, the charge carrier confinement in the nanosheets’ height adjustable from 2 to 20 nm has a decisive impact on their electronic properties. This is demonstrated by their use as conduction channel in a field effect transistor [2]. Recently we also showed that especially thin nanosheets show a high carrier multiplication (CM) efficiency [3] which could make them, through the confinement induced band gap and high photoconductivity, very attractive for application in photovoltaic devices. We are already able to manufacture photovoltaic devices out of single nanosheets which show promising results.

Keywords: physical sciences, chemistry, materials, chemistry, colloids, physics, condensed-matter physics, semiconductors, two-dimensional materials

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Authors: Naima Guenifi, Shiromani Balmukund Rahi, Amina Bechka

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Tunnel FET is one of the most suitable alternatives FET devices for conventional CMOS technology for low-power electronics and applications. Due to its lower subthreshold swing (SS) value, it is a strong follower of low power applications. It is a quantum FET device that follows the band to band (B2B) tunneling transport phenomena of charge carriers. Due to band to band tunneling, tunnel FET is suffering from a lower switching current than conventional metal-oxide-semiconductor field-effect transistor (MOSFET). For improvement of device features and limitations, the newly invented negative capacitance concept of ferroelectric material is implemented in conventional Tunnel FET structure popularly known as NC TFET. The present research work has implemented the idea of high-k gate dielectric added with ferroelectric material on double gate Tunnel FET for implementation of negative capacitance. It has been observed that the idea of negative capacitance further improves device features like SS value. It helps to reduce power dissipation and switching energy. An extensive investigation for circularity uses for digital, analog/RF and linearity features of double gate NCTFET have been adopted here for research work. Several essential designs paraments for analog/RF and linearity parameters like transconductance(gm), transconductance generation factor (gm/IDS), its high-order derivatives (gm2, gm3), cut-off frequency (fT), gain-bandwidth product (GBW), transconductance generation factor (gm/IDS) has been investigated for low power RF applications. The VIP₂, VIP₃, IMD₃, IIP₃, distortion characteristics (HD2, HD3), 1-dB, the compression point, delay and power delay product performance have also been thoroughly studied.

Keywords: analog/digital, ferroelectric, linearity, negative capacitance, Tunnel FET, transconductance

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Authors: Zina Saheb, Ezz El-Masry

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As CMOS technology scaling down, Silicon oxide thickness (SiO2) become very thin (few Nano meters). When SiO2 is less than 3nm, gate direct tunneling (DT) leakage current becomes a dormant problem that impacts the transistor performance. Floating gate MOSFET (FGMOSFET) has been used in many low-voltage and low-power applications. Most of the available simulation models of FGMOSFET for analog circuit design does not account for gate DT current and there is no accurate analysis for the gate DT. It is a crucial to use an accurate mode in order to get a realistic simulation result that account for that DT impact on FGMOSFET performance effectively.

Keywords: CMOS transistor, direct-tunneling current, floating-gate, gate-leakage current, simulation model

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Authors: Nur Syarafina Binti Othman, Tsubasa Jindo, Makato Yamada, Miho Tsuyama, Hitoshi Nakano

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A novel method to produce a fast high voltage solid states switch using Insulated Gate Bipolar Transistors (IGBTs) is presented for discharge-pumped gas lasers. The IGBTs are connected in series to achieve a high voltage rating. An avalanche transistor is used as the gate driver. The fast pulse generated by the avalanche transistor quickly charges the large input capacitance of the IGBT, resulting in a switch out of a fast high-voltage pulse. The switching characteristic of fast-high voltage solid state switch has been estimated in the multi-stage series-connected IGBT with the applied voltage of several tens of kV. Electrical circuit diagram and the mythology of fast-high voltage solid state switch as well as experimental results obtained are presented.

Keywords: high voltage, IGBT, solid state switch, bipolar transistor

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: Hassane Ouazzani Chahdi, Omar Helli, Bourzgui Nour Eddine, Hassan Maher, Ali Soltani

Abstract:

The real-time knowledge of the NO, NO₂ concentration at high temperature, would allow manufacturers of automobiles to meet the upcoming stringent EURO7 anti-pollution measures for diesel engines. Knowledge of the concentration of each of these species will also enable engines to run leaner (i.e., more fuel efficient) while still meeting the anti-pollution requirements. Our proposed technology is promising in the field of automotive sensors. It consists of nanostructured semiconductors based on gallium nitride and zirconia dioxide. The development of new technologies for selective detection of NO and NO₂ gas species would be a critical enabler of superior depollution. The current response was well correlated to the NO concentration in the range of 0–2000 ppm, 0-2500 ppm NO₂, and 0-300 ppm NH₃ at a temperature of 600.

Keywords: NOₓ sensors, HEMT transistor, anti-pollution, gallium nitride, gas sensor

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Authors: Olfat A. Fadali, Mohamed S. Mahmoud, Omnia H. Abdelraheem, Shimaa G. Mohammed

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The effect of electromagnetic field (EMF) on the removal of edible oil from oil-in-water emulsion by means of electrocoagulation was investigated in rectangular batch electrochemical cell with DC current. Iron (Fe) plate anodes and stainless steel cathodes were employed as electrodes. The effect of different magnetic field intensities (1.9, 3.9 and 5.2 tesla), three different positions of EMF (below, perpendicular and parallel to the electrocoagulation cell), as well as operating time; had been investigated. The application of electromagnetic field (5.2 tesla) raises percentage of oil removal from 72.4% for traditional electrocoagulation to 90.8% after 20 min.

Keywords: electrocoagulation, electromagnetic field, Oil-water emulsion, edible oil

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Authors: Birinderjit Singh Kalyan, Inderpreet Kaur, Balwinder Singh Sohi

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In this paper, an equivalent model for floating gate transistor has been proposed. Using the floating gate voltage value, capacitive coupling coefficients has been found at different bias conditions. The amount of charge present on the gate has been then calculated using the transient models of hot electron programming and Fowler-Nordheim Tunnelling. The proposed model can be extended to the transient conditions as well. The SPICE equivalent model is designed and current-voltage characteristics and Transfer characteristics are comparatively analysed. The dc current-voltage characteristics, as well as dc transfer characteristics, have been plotted for an FGMOS with W/L=0.25μm/0.375μm, the inter-poly capacitance of 0.8fF for both programmed and erased states. The Comparative analysis has been made between the present model and capacitive coefficient coupling methods which were already available.

Keywords: FGMOS, floating gate transistor, capacitive coupling coefficient, SPICE model

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Authors: Tomas Vincze, Michal Micjan, Milan Pavuk, Martin Weis

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In recent years, alternative materials are gaining attention to replace polycrystalline and amorphous silicon, which are a standard for low requirement devices, where silicon is unnecessarily and high cost. For that reason, metal oxides are envisioned as the new materials for these low-requirement applications such as sensors, solar cells, energy storage devices, or field-effect transistors. Their most common way of layer growth is sputtering; however, this is a high-cost fabrication method, and a more industry-suitable alternative is the sol-gel method. In this group of materials, many oxides exhibit a semiconductor-like behavior with sufficiently high mobility to be applied as transistors. The sol-gel method is a cost-effective deposition technique for semiconductor-based devices. Copper oxides, as p-type semiconductors with free charge mobility up to 1 cm2/Vs., are suitable replacements for poly-Si or a-Si:H devices. However, to reach the potential of silicon devices, a fine-tuning of material properties is needed. Here we focus on the optimization of the electrical parameters of copper oxide-based field-effect transistors by modification of precursor solvent (usually 2-methoxy ethanol). However, to achieve solubility and high-quality films, a better solvent is required. Since almost no solvents have both high dielectric constant and high boiling point, an alternative approach was proposed with blend solvents. By mixing isopropyl alcohol (IPA) and 2-methoxy ethanol (2ME) the precursor reached better solubility. The quality of the layers fabricated using mixed solutions was evaluated in accordance with the surface morphology and electrical properties. The IPA:2ME solution mixture reached optimum results for the weight ratio of 1:3. The cupric oxide layers for optimal mixture had the highest crystallinity and highest effective charge mobility.

Keywords: copper oxide, field-effect transistor, semiconductor, sol-gel method

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