Search results for: CMOS capacitor array

Authors: Biswarup Mukherjee, Aniruddha Ghosal

Abstract:

In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Zina Saheb, Ezz El-Masry

Abstract:

As CMOS technology scaling down, Silicon oxide thickness (SiO2) become very thin (few Nano meters). When SiO2 is less than 3nm, gate direct tunneling (DT) leakage current becomes a dormant problem that impacts the transistor performance. Floating gate MOSFET (FGMOSFET) has been used in many low-voltage and low-power applications. Most of the available simulation models of FGMOSFET for analog circuit design does not account for gate DT current and there is no accurate analysis for the gate DT. It is a crucial to use an accurate mode in order to get a realistic simulation result that account for that DT impact on FGMOSFET performance effectively.

Keywords: CMOS transistor, direct-tunneling current, floating-gate, gate-leakage current, simulation model

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Authors: S. Neelima, P. S. Subramanyam

Abstract:

A distribution system is an interface between the bulk power system and the consumers. Among these systems, radial distributions system is popular because of low cost and simple design. In distribution systems, the voltages at buses reduces when moved away from the substation, also the losses are high. The reason for a decrease in voltage and high losses is the insufficient amount of reactive power, which can be provided by the shunt capacitors. But the placement of the capacitor with an appropriate size is always a challenge. Thus, the optimal capacitor placement problem is to determine the location and size of capacitors to be placed in distribution networks in an efficient way to reduce the power losses and improve the voltage profile of the system. For this purpose, in this paper, two stage methodologies are used. In the first stage, the load flow of pre-compensated distribution system is carried out using ‘dimension reducing distribution load flow algorithm (DRDLFA)’. On the basis of this load flow the potential locations of compensation are computed. In the second stage, Genetic Algorithm (GA) technique is used to determine the optimal location and size of the capacitors such that the cost of the energy loss and capacitor cost to be a minimum. The above method is tested on IEEE 9 and 34 bus system and compared with other methods in the literature.

Keywords: dimension reducing distribution load flow algorithm, DRDLFA, genetic algorithm, electrical distribution network, optimal capacitors placement, voltage profile improvement, loss reduction

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Authors: Amit Kumar Baghel, Sisir Kumar Nayak

Abstract:

The proposed metamaterial design help to increase the radiation efficiency at 2.9 GHz by reducing the side and back lobes by making the phase difference of the waves emerging from the phase center of the horn antenna same after passing through metamaterial array. The unit cell of the metamaterial is having concentric ring structure made of copper of 0.035 mm thickness on both sides of FR4 sheet. The inner ring diameter is kept as 3 mm, and the outer ring diameters are changed according to the path and tramission phase difference of the unit cell from the phase center of the antenna in both the horizontal and vertical direction, i.e., in x- and y-axis. In this case, the ring radius varies from 3.19 mm to 6.99 mm with the respective S21 phase difference of -62.25° to -124.64°. The total phase difference can be calculated by adding the path difference of the respective unit cell in the array to the phase difference of S21. Taking one of the unit cell as the reference, the total phase difference between the reference unit cell and other cells must be integer multiple of 360°. The variation of transmission coefficient S21 with the ring radius is greater than -6 dB. The array having 5 x 5 unit cell is kept inside the pyramidal horn antenna (L X B X H = 295.451 x 384.233 x 298.66 mm3) at a distance of 36.68 mm from the waveguide throat. There is an improvement in side lobe level in E-plane by 14.6 dB when the array is used. The front to back lobe ration is increased by 1 dB by using the array. The proposed antenna with metamaterial array can be used in beam shaping for wireless power transfer applications.

Keywords: metamaterial, side lobe level, front to back ratio, beam forming

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Authors: Hassan M. Elkamchouchi, Samy H. Darwish, Yasser H. Elkamchouchi, M. E. Morsy

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Methodology is suggested to design a linear rectangular microstrip array antenna based on Yagi antenna theory. The antenna with different directors' lengths as parasitic elements were designed, simulated, and analyzed using HFSS. The calculus and results illustrate the effectiveness of using specific parasitic elements to improve the directivity and gain for microstrip array antenna. The results have shown that the suggested methodology has the potential to be applied for improving the antenna performance. Maximum radiation intensity (Umax) of the order of 0.47w/st was recorded, directivity of 6.58dB, and gain better than 6.07dB are readily achievable for the antenna that working.

Keywords: directivity, director, microstrip antenna, gain improvment

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Authors: K. Shaji Mon, P. R. John Sreenidhi

Abstract:

In deep-submicrometer CMOS processes, time-domain resolution of a digital signal is becoming higher than voltage resolution of analog signals. This claim is nowadays pushing toward a new circuit design paradigm in which the traditional analog signal processing is expected to be progressively substituted by the processing of times in the digital domain. Within this novel paradigm, digitally controlled delay lines (DCDL) should play the role of digital-to-analog converters in traditional, analog-intensive, circuits. Digital delay locked loops are highly prevalent in integrated systems.The proposed paper addresses the glitches present in delay circuits along with area,power dissipation and signal integrity.The digitally controlled delay lines(DCDL) under study have been designed in a 90 nm CMOS technology 6 layer metal Copper Strained SiGe Low K Dielectric. Simulation and synthesis results show that the novel circuits exhibit no glitches for dual output coarse DCDL with less power dissipation and consumes less area compared to the glitch free NAND based DCDL.

Keywords: glitch free, NAND-based DCDL, CMOS, deep-submicrometer

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Authors: Muhaned Zaidi, Ian Grout, Abu Khari bin A’ain

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In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process.

Keywords: op-amp, rail-to-rail output, Miller compensation, Negative Miller capacitance

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Authors: Nakarin Prempri

Abstract:

Single-phase induction motors are widely used in industry. Most manufacturing processes use capacitor-run single-phase induction motors to drive mechanical loads. The selection of a suitable motor for driving is important. The optimum operating range of the motor can help the motor operate efficiently. Thus, this paper presents an operating range analysis of capacitor-run single-phase induction motors and a determination of suitability between motor and mechanical loads. an observational study found that the optimum operating range of the motor can be used to determine the suitability between the motor and the mechanical load. Such considerations ensure that the motor uses no more current than necessary and operates efficiently.

Keywords: single phase induction motor, operating range, torque curve, efficiency curve

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Authors: D. Sun, T. F. Lu, A. Zander, M. Trinkle

Abstract:

This paper investigates the potential use of airborne ultrasonic phased arrays for imaging in outdoor environments as a means of overcoming the limitations experienced by kinect sensors, which may fail to work in the outdoor environments due to the oversaturation of the infrared photo diodes. Ultrasonic phased arrays have been well studied for static media, yet there appears to be no comparable examination in the literature of the impact of a flowing medium on the focusing behaviour of near field focused ultrasonic arrays. This paper presents a method for predicting the sound pressure fields produced by a single ultrasound element or an ultrasonic phased array influenced by airflows. The approach can be used to determine the actual focal point location of an array exposed in a known flow field. From the presented simulation results based upon this model, it can be concluded that uniform flows in the direction orthogonal to the acoustic propagation have a noticeable influence on the sound pressure field, which is reflected in the twisting of the steering angle of the array. Uniform flows in the same direction as the acoustic propagation have negligible influence on the array. For an array impacted by a turbulent flow, determining the location of the focused sound field becomes difficult due to the irregularity and continuously changing direction and the speed of the turbulent flow. In some circumstances, ultrasonic phased arrays impacted by turbulent flows may not be capable of producing a focused sound field.

Keywords: airborne, airflow, focused sound field, ultrasonic phased array

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Authors: Olawale J. Olaluyi, Ayodele S. Oluwole, O. Akinsanmi, Johnson O. Adeogo

Abstract:

Communication using visible light VLC is considered a cutting-edge technology used for data transmission and illumination since it uses less energy than radio frequency (RF) technology and has a large bandwidth, extended lifespan, and high security. The room's irregular distribution of small base stations, or LED array distribution, is the cause of the obscured area, minimum signal-to-noise ratio (SNR), and received power. In order to maximize the received power distribution and SNR at the center of the room for an indoor VLC system, the researchers offer an innovative model for the placement of eight LED array distributions in this work. We have investigated the arrangement of the LED array distribution with regard to receiving power to fill the open space in the center of the room. The suggested LED array distribution saved 36.2% of the transmitted power, according to the simulation findings. Aside from that, the entire room was equally covered. This leads to an increase in both received power and SNR.

Keywords: visible light communication (VLC), light emitted diodes (LED), optical power distribution, signal-to-noise ratio (SNR).

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Authors: Anatoly D. Pluzhnikov, Elena N. Pribludova, Alexander G. Ryndyk

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In conjunction with the problem of the target selection on a clutter background, the analysis of the scanning rate influence on the spatial-temporal signal structure, the generalized multivariate correlation function and the quality of the resolution with the increase pulse repetition frequency is made. The possibility of the object space-distance resolution, which is conditioned by the range-to-angle conversion with an increased scanning rate, is substantiated. The calculations for the real cylindrical array at high scanning rate are presented. The high scanning rate let to get the signal to noise improvement of the order of 10 dB for the space-time signal processing.

Keywords: antenna pattern, array, signal processing, spatial resolution

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Authors: P. Kamphikul, P. Krachodnok, R. Wongsan

Abstract:

This paper presents the gain improvement of a sector antenna for mobile phone base station by using the new technique to enhance its gain for microstrip antenna (MSA) array without construction enlargement. The curved woodpile Electromagnetic Band Gap (EBG) has been utilized to improve the gain instead. The advantages of this proposed antenna are reducing the length of MSAs array but providing the higher gain and easy fabrication and installation. Moreover, it provides a fan-shaped radiation pattern, wide in the horizontal direction and relatively narrow in the vertical direction, which appropriate for mobile phone base station. The paper also presents the design procedures of a 1x8 MSAs array associated with U-shaped reflector for decreasing their back and side lobes. The fabricated curved woodpile EBG exhibits bandgap characteristics at 2.1 GHz and is utilized for realizing a resonant cavity of MSAs array. This idea has been verified by both the Computer Simulation Technology (CST) software and experimental results. As the results, the fabricated proposed antenna achieves a high gain of 20.3 dB and the half-power beam widths in the E- and H-plane of 36.8 and 8.7 degrees, respectively. Good qualitative agreement between measured and simulated results of the proposed antenna was obtained.

Keywords: gain improvement, microstrip antenna array, electromagnetic band gap, base station

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

Abstract:

In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: Chien-Ju Chen, Chia-Jui Yu, Jyun-Hao Liao, Chia-Ching Wu, Meng-Chyi Wu

Abstract:

A 64 × 64 GaN-based micro-light-emitting diode array (μLEDA) with 20 μm in pixel size and 40 μm in pitch by flip-chip bonding (FCB) is demonstrated in this study. Besides, an underfilling (UF) technology is applied to the process for improving the uniformity of device. With those configurations, good characteristics are presented, operation voltage and series resistance of a pixel in the 450 nm flip chip μLEDA are 2.89 V and 1077Ω (4.3 mΩ-cm²) at 25 A/cm², respectively. The μLEDA can sustain higher current density compared to conventional LED, and the power of the device is 9.5 μW at 100 μA and 0.42 mW at 20 mA.

Keywords: GaN, micro-light-emitting diode array(μLEDA), flip-chip bonding, underfilling

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Authors: Udayan Patankar, Shashwati Bhagat, Vilas Nitneware, Ants Koel

Abstract:

An ISM band power amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically used for driving the antenna of a transmitter. Due to drastic changes in telecommunication generations may lead to the requirements of improvements. Rapid changes in communication lead to the wide implementation of WLAN technology for its excellent characteristics, such as high transmission speed, long communication distance, and high reliability. Many applications such as WLAN, Bluetooth, and ZigBee, etc. were evolved with 2.4GHz to 5 GHz ISM Band, in which the power amplifier (PA) is a key building block of RF transmitters. There are many manufacturing processes available to manufacture a power amplifier for desired power output, but the major problem they have faced is about the power it consumed for its proper working, as many of them are fabricated on the GaN HEMT, Bi COMS process. In this paper we present a CMOS Base two stage cascode design of power amplifier working on 2.4GHz ISM frequency band. To lower the costs and allow full integration of a complete System-on-Chip (SoC) we have chosen 0.13µm low power CMOS technology for design. While designing a power amplifier, it is a real task to achieve higher power efficiency with minimum resources. This design showcase the Multi biased Cascode methodology to implement a two-stage CMOS power amplifier using ADS and LTSpice simulating tool. Main source is maximum of 2.4V which is internally distributed into different biasing point VB driving and VB driven as required for distinct stages of two stage RF power amplifier. It shows maximum power added efficiency near about 70.195% whereas its Power added efficiency calculated at 1 dB compression point is 44.669 %. Biased MOSFET is used to reduce total dc current as this circuit is designed for different wireless applications comes under 2.4GHz ISM Band.

Keywords: RFIC, PAE, RF CMOS, impedance matching

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Authors: Shahpar Yilmaz, Yasir Nadeem, Syed A. Mehdi

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Searching for a record in a dataset is always a frequent task for any data structure-related application. Hence, a fast and efficient algorithm for the approach has its importance in yielding the quickest results and enhancing the overall productivity of the company. Interpolation search is one such technique used to search through a sorted set of elements. This paper proposes a new algorithm, an advancement over interpolation search for the application of search over a sorted array. Pattern Recognition Search or PR Search (PRS), like interpolation search, is a pattern-based divide and conquer algorithm whose objective is to reduce the sample size in order to quicken the process and it does so by treating the array as a perfect arithmetic progression series and thereby deducing the key element’s position. We look to highlight some of the key drawbacks of interpolation search, which are accounted for in the Pattern Recognition Search.

Keywords: array, complexity, index, sorting, space, time

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Authors: Hamid Aslani, Ahmed Radwan

Abstract:

In this paper, a single element microstrip antenna is presented for UWB applications by using techniques as partial ground plane and modified the shape of the patch. The antenna is properly designed to have a compact size and constant gain against frequency. The simulated results have done using two EM software and show good agreement with the measured results for the fabricated antenna. Then a designing of two elements patch antenna array for UWB in the frequency band of 3.1-10 GHz is presented in this paper. The array is constructed by means of feeding two omni-directional modified circular patch elements with a modified power divider. Experimental results show that the array has a stable radiation pattern and low return loss over a broad bandwidth of 64% (3.1–10 GHz). Due to its planar profile, physically compact size, wide impedance bandwidth, directive performance over a wide bandwidth proposed antenna is a good candidate for portable UWB applications and other UWB integrated circuits.

Keywords: ultra wide band, radiation performance, microstrip antenna, size miniaturized antenna

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Authors: Syed Islam, Yiyun Huang, Sebastian Magierowski, Ebrahim Ghafar-Zadeh

Abstract:

This paper presents system level CMOS solid-state nanopore techniques enhancement for speedup next generation molecular recording and high throughput channels. This discussion also considers optimum number of base-pair (bp) measurements through channel as an important role to enhance potential read accuracy. Effective power consumption estimation offered suitable rangeof multi-channel configuration. Nanopore bp extraction model in statistical method could contribute higher read accuracy with longer read-length (200 < read-length). Nanopore ionic current switching with Time Multiplexing (TM) based multichannel readout system contributed hardware savings.

Keywords: DNA, nanopore, amplifier, ADC, multichannel

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Authors: W. J. Zhang, Y. Q. Du, M. L. Wang

Abstract:

Noninvasive diagnostics of diseases via breath analysis has attracted considerable scientific and clinical interest for many years and become more and more promising with the rapid advancement in nanotechnology and biotechnology. The volatile organic compounds (VOCs) in exhaled breath, which are mainly blood borne, particularly provide highly valuable information about individuals’ physiological and pathophysiological conditions. Additionally, breath analysis is noninvasive, real-time, painless and agreeable to patients. We have developed a wireless sensor array based on single-stranded DNA (ssDNA)-decorated single-walled carbon nanotubes (SWNT) for the detection of a number of physiological indicators in breath. Eight DNA sequences were used to functionalize SWNT sensors to detect trace amount of methanol, benzene, dimethyl sulfide, hydrogen sulfide, acetone and ethanol, which are indicators of heavy smoking, excessive drinking, and diseases such as lung cancer, breast cancer, cirrhosis and diabetes. Our tests indicated that DNA functionalized SWNT sensors exhibit great selectivity, sensitivity, reproducibility, and repeatability. Furthermore, different molecules can be distinguished through pattern recognition enabled by this sensor array. Thus, the DNA-SWNT sensor array has great potential to be applied in chemical or bimolecular detection for the noninvasive diagnostics of diseases and health monitoring.

Keywords: breath analysis, diagnosis, DNA-SWNT sensor array, noninvasive

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

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CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE

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Authors: Cinna Soltanpur, Mohammad Ghamari, Behzad Momahed Heravi, Fatemeh Zare

Abstract:

Low-density parity-check (LDPC) codes have been shown to deliver capacity approaching performance; however, problematic graphical structures (e.g. trapping sets) in the Tanner graph of some LDPC codes can cause high error floors in bit-error-ratio (BER) performance under conventional sum-product algorithm (SPA). This paper presents a serial concatenation scheme to avoid the trapping sets and to lower the error floors of LDPC code. The outer code in the proposed concatenation is the LDPC, and the inner code is a high rate array code. This approach applies an interactive hybrid process between the BCJR decoding for the array code and the SPA for the LDPC code together with bit-pinning and bit-flipping techniques. Margulis code of size (2640, 1320) has been used for the simulation and it has been shown that the proposed concatenation and decoding scheme can considerably improve the error floor performance with minimal rate loss.

Keywords: concatenated coding, low–density parity–check codes, array code, error floors

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

Abstract:

This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm

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Authors: Kübra Taşkıran, Bahattin Türetken

Abstract:

In this paper, a microstrip array antenna with circular polarization at 2.4 GHz frequency has been designed using the in order to provide image and telemetric data transmission in Unmanned Aerial Vehicle and Armed Unmanned Aerial Vehicle Systems. In addition to the antenna design, the power divider design was made and the antennas were fed in phase. As a result of the analysis, it was observed that the antenna operates at a frequency of 2.4016 GHz with 12.2 dBi directing gain. In addition, this designed array antenna was transformed into a form compatible with the rocket surface used in A-UAV Systems, and analyzes were made. As a result of these analyzes, it has been observed that the antenna operates on the surface of the missile at a frequency of 2.372 GHz with a directivity gain of 10.2 dBi.

Keywords: cicrostrip array antenna, circular polarization, 2.4 GHz, image and telemetric data, transmission, surface compatible, UAV and armed UAV

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Authors: Somayeh Komeylian

Abstract:

The direction of arrival (DoA) estimation is the crucial aspect of the radar technologies for detecting and dividing several signal sources. In this scenario, the antenna array output modeling involves numerous parameters including noise samples, signal waveform, signal directions, signal number, and signal to noise ratio (SNR), and thereby the methods of the DoA estimation rely heavily on the generalization characteristic for establishing a large number of the training data sets. Hence, we have analogously represented the two different optimization models of the DoA estimation; (1) the implementation of the decision directed acyclic graph (DDAG) for the multiclass least-squares support vector machine (LS-SVM), and (2) the optimization method of the deep neural network (DNN) radial basis function (RBF). We have rigorously verified that the LS-SVM DDAG algorithm is capable of accurately classifying DoAs for the three classes. However, the accuracy and robustness of the DoA estimation are still highly sensitive to technological imperfections of the antenna arrays such as non-ideal array design and manufacture, array implementation, mutual coupling effect, and background radiation and thereby the method may fail in representing high precision for the DoA estimation. Therefore, this work has a further contribution on developing the DNN-RBF model for the DoA estimation for overcoming the limitations of the non-parametric and data-driven methods in terms of array imperfection and generalization. The numerical results of implementing the DNN-RBF model have confirmed the better performance of the DoA estimation compared with the LS-SVM algorithm. Consequently, we have analogously evaluated the performance of utilizing the two aforementioned optimization methods for the DoA estimation using the concept of the mean squared error (MSE).

Keywords: DoA estimation, Adaptive antenna array, Deep Neural Network, LS-SVM optimization model, Radial basis function, and MSE

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Authors: MeiBo, ZhaoXing, LuoLei, YuQingkui, TangMin, HanZhengsheng

Abstract:

The Single Event Transients (SETs) were investigated on 0.18μm PDSOI transistors and 100 series CMOS inverter chain using pulse laser. The effect of different laser energy and device bias for waveform on SET was characterized experimentally, as well as the generation and propagation of SET in inverter chain. In this paper, the effects of struck transistors type and struck locations on SETs were investigated. The results showed that when irradiate NMOSFETs from 100th to 2nd stages, the SET pulse width measured at the output terminal increased from 287.4 ps to 472.9 ps; and when irradiate PMOSFETs from 99th to 1st stages, the SET pulse width increased from 287.4 ps to 472.9 ps. When struck locations were close to the output of the chain, the SET pulse was narrow; however, when struck nodes were close to the input, the SET pulse was broadening. SET pulses were progressively broadened up when propagating along inverter chains. The SET pulse broadening is independent of the type of struck transistors. Through analysis, history effect induced threshold voltage hysteresis in PDSOI is the reason of pulse broadening. The positive pulse observed by oscilloscope, contrary to the expected results, is because of charging and discharging of capacitor.

Keywords: single event transients, pulse laser, partially-depleted silicon-on-insulator, propagation-induced pulse broadening effect

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Authors: Ju-Hong Lee, Ching-Wei Liao

Abstract:

Owing to close antenna spacing between antenna sensors within a compact space, a part of data in one antenna sensor would outflow to other antenna sensors when the antenna sensors in an antenna array operate simultaneously. This phenomenon is called mutual coupling effect (MCE). It has been shown that the performance of antenna array systems can be degraded when the antenna sensors are in close proximity. Especially, in a systems equipped with massive antenna sensors, the degradation of beamforming performance due to the MCE is significantly inevitable. Moreover, it has been shown that even a small angle error between the true direction angle of the desired signal and the steering angle deteriorates the effectiveness of an array beamforming system. However, the true direction vector of the desired signal may not be exactly known in some applications, e.g., the application in land mobile-cellular wireless systems. Therefore, it is worth developing robust techniques to deal with the problem due to the MCE and steering angle error for array beamforming systems. In this paper, we present an efficient technique for performing adaptive beamforming with robust capabilities against the MCE and the steering angle error. Only the data vector received by an antenna array is required by the proposed technique. By using the received array data vector, a correlation matrix is constructed to replace the original correlation matrix associated with the received array data vector. Then, the mutual coupling matrix due to the MCE on the antenna array is estimated through a recursive algorithm. An appropriate estimate of the direction angle of the desired signal can also be obtained during the recursive process. Based on the estimated mutual coupling matrix, the estimated direction angle, and the reconstructed correlation matrix, the proposed technique can effectively cure the performance degradation due to steering angle error and MCE. The novelty of the proposed technique is that the implementation procedure is very simple and the resulting adaptive beamforming performance is satisfactory. Simulation results show that the proposed technique provides much better beamforming performance without requiring complicated complexity as compared with the existing robust techniques.

Keywords: adaptive beamforming, mutual coupling effect, recursive algorithm, steering angle error

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Authors: Kittipong Tripetch

Abstract:

This paper proposes studies of input impedance of two types of the CMOS active inductor. It derives two input impedance formulas. The first formula is the input impedance of a grounded active inductor. The second formula is an input impedance of floating active inductor. After that, these formulas can be used to simulate magnitude and phase response of input impedance as a function of current consumption with MATLAB. Common mode rejection ratio (CMRR) of a fully differential bandpass amplifier is derived based on superposition principle. CMRR as a function of input frequency is plotted as a function of current consumption

Keywords: grounded active inductor, floating active inductor, fully differential bandpass amplifier

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Authors: Sung-Won Seo, Jang-Young Choi

Abstract:

The rare earth magnets used in synchronous generators offer many advantages, including high efficiency, greatly reduced the size, and weight. The permanent magnet linear synchronous generator (PMLSG) allows for direct drive without the need for a mechanical device. Therefore, the PMLSG is well suited to translational applications, such as wave energy converters and free piston energy converters. This manuscript compares the effects of different magnetization patterns on the characteristics of double-sided PMLSGs in slotless stator structures. The Halbach array has a higher flux density in air-gap than the Vertical array, and the advantages of its performance and efficiency are widely known. To verify the advantage of Halbach array, we apply a finite element method (FEM) and analytical method. In general, a FEM and an analytical method are used in the electromagnetic analysis for determining model characteristics, and the FEM is preferable to magnetic field analysis. However, the FEM is often slow and inflexible. On the other hand, the analytical method requires little time and produces accurate analysis of the magnetic field. Therefore, the flux density in air-gap and the Back-EMF can be obtained by FEM. In addition, the results from the analytical method correspond well with the FEM results. The model of the Halbach array reveals less copper loss than the model of the Vertical array, because of the Halbach array’s high output power density. The model of the Vertical array is lower core loss than the model of Halbach array, because of the lower flux density in air-gap. Therefore, the current density in the Vertical model is higher for identical power output. The completed manuscript will include the magnetic field characteristics and structural features of both models, comparing various results, and specific comparative analysis will be presented for the determination of the best model for application in a wave energy converting system.

Keywords: wave energy converter, permanent magnet linear synchronous generator, finite element method, analytical method

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Authors: Nattachote Rugthaicharoencheep

Abstract:

This paper presents a feeder reconfiguration problem in distribution systems. The objective is to minimize the system power loss and to improve bus voltage profile. The optimization problem is subjected to system constraints consisting of load-point voltage limits, radial configuration format, no load-point interruption, and feeder capability limits. A method based on genetic algorithm, a search algorithm based on the mechanics of natural selection and natural genetics, is proposed to determine the optimal pattern of configuration. The developed methodology is demonstrated by a 33-bus radial distribution system with distributed generations and feeder capacitors. The study results show that the optimal on/off patterns of the switches can be identified to give the minimum power loss while respecting all the constraints.

Keywords: network reconfiguration, distributed generation capacitor placement, loss reduction, genetic algorithm

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Authors: Devin Atkin, Orly Yadid-Pecht

Abstract:

The continual demands for increasing resolution and dynamic range in CMOS image sensors have resulted in exponential increases in the amount of data that needs to be read out of an image sensor, and existing readouts cannot keep up with this demand. Interesting approaches such as sparse and burst readouts have been proposed and show promise, but at considerable trade-offs in other specifications. To this end, we have begun designing and evaluating various new readout topologies centered around an attempt to parallelize the sensor readout. In this paper, we have designed, simulated, and started testing a new light-controlled oscillator topology with dual column and row readouts. We expect the parallel readout structure to offer greater speed and alleviate the trade-off typical in this topology, where slow pixels present a major framerate bottleneck.

Keywords: CMOS image sensors, high-speed capture, wide dynamic range, light controlled oscillator

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