Search results for: CMOS FSK receiver

Authors: Udayan Patankar, Shashwati Bhagat, Vilas Nitneware, Ants Koel

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An ISM band power amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically used for driving the antenna of a transmitter. Due to drastic changes in telecommunication generations may lead to the requirements of improvements. Rapid changes in communication lead to the wide implementation of WLAN technology for its excellent characteristics, such as high transmission speed, long communication distance, and high reliability. Many applications such as WLAN, Bluetooth, and ZigBee, etc. were evolved with 2.4GHz to 5 GHz ISM Band, in which the power amplifier (PA) is a key building block of RF transmitters. There are many manufacturing processes available to manufacture a power amplifier for desired power output, but the major problem they have faced is about the power it consumed for its proper working, as many of them are fabricated on the GaN HEMT, Bi COMS process. In this paper we present a CMOS Base two stage cascode design of power amplifier working on 2.4GHz ISM frequency band. To lower the costs and allow full integration of a complete System-on-Chip (SoC) we have chosen 0.13µm low power CMOS technology for design. While designing a power amplifier, it is a real task to achieve higher power efficiency with minimum resources. This design showcase the Multi biased Cascode methodology to implement a two-stage CMOS power amplifier using ADS and LTSpice simulating tool. Main source is maximum of 2.4V which is internally distributed into different biasing point VB driving and VB driven as required for distinct stages of two stage RF power amplifier. It shows maximum power added efficiency near about 70.195% whereas its Power added efficiency calculated at 1 dB compression point is 44.669 %. Biased MOSFET is used to reduce total dc current as this circuit is designed for different wireless applications comes under 2.4GHz ISM Band.

Keywords: RFIC, PAE, RF CMOS, impedance matching

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Authors: Syed Islam, Yiyun Huang, Sebastian Magierowski, Ebrahim Ghafar-Zadeh

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This paper presents system level CMOS solid-state nanopore techniques enhancement for speedup next generation molecular recording and high throughput channels. This discussion also considers optimum number of base-pair (bp) measurements through channel as an important role to enhance potential read accuracy. Effective power consumption estimation offered suitable rangeof multi-channel configuration. Nanopore bp extraction model in statistical method could contribute higher read accuracy with longer read-length (200 < read-length). Nanopore ionic current switching with Time Multiplexing (TM) based multichannel readout system contributed hardware savings.

Keywords: DNA, nanopore, amplifier, ADC, multichannel

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

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CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE

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Authors: H. Fekhar

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Design and implementation acquisition system using radio frequency (RF) ASK module and micro controllers PIC is proposed in this work. The paper includes hardware and software design. The design tools are divided into two units , namely the sender MCU and receiver.The system was designed to measure temperatures of two furnaces and pressure pneumatic process. The wireless transmitter unit use the 433.95 MHz band directly interfaced to micro controller PIC18F4620. The sender unit consists of temperatures-pressure sensors , conditioning circuits , keypad GLCD display and RF module.Signal conditioner converts the output of the sensors into an electric quantity suitable for operation of the display and recording system.The measurements circuits are connected directly to 10 bits multiplexed A/D converter.The graphic liquid crystal display (GLCD) is used . The receiver (RF) module connected to a second microcontroller ,receive the signal via RF receiver , decode the Address/data and reproduces the original data . The strategy adopted for establishing communication between the sender MCU and receiver uses the specific protocol “Header, Address and data”.The communication protocol dealing with transmission and reception have been successfully implemented . Some experimental results are provided to demonstrate the effectiveness of the proposed wireless system. This embedded system track temperatures – pressure signal reasonably well with a small error.

Keywords: microcontrollers, sensors, graphic liquid cristal display, protocol, temperature, pressure

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

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This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm

Procedia PDF Downloads 374

Authors: Myoung-Jin Kim, Yeong-Seop Ahn, Hyun-Jee Yang, Hyoung-Kyu Song

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This paper proposes the new cooperative communication scheme for the wireless communication system. When the receiver is located in the edge of coverage, the signal from the transmitter is distorted by the inter-cell interference (ICI) and power reduction by distance. In order to improve communication performance, the proposed scheme adds the relay. By using the relay, the receiver receives the signal from the transmitter and relay at the same time. Therefore, the new cooperative communication scheme obtains diversity gain and is improved by the relay.

Keywords: cooperative communication, diversity gain, OFDM, MIMO

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Authors: Kittipong Tripetch

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This paper proposes studies of input impedance of two types of the CMOS active inductor. It derives two input impedance formulas. The first formula is the input impedance of a grounded active inductor. The second formula is an input impedance of floating active inductor. After that, these formulas can be used to simulate magnitude and phase response of input impedance as a function of current consumption with MATLAB. Common mode rejection ratio (CMRR) of a fully differential bandpass amplifier is derived based on superposition principle. CMRR as a function of input frequency is plotted as a function of current consumption

Keywords: grounded active inductor, floating active inductor, fully differential bandpass amplifier

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Authors: Devin Atkin, Orly Yadid-Pecht

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The continual demands for increasing resolution and dynamic range in CMOS image sensors have resulted in exponential increases in the amount of data that needs to be read out of an image sensor, and existing readouts cannot keep up with this demand. Interesting approaches such as sparse and burst readouts have been proposed and show promise, but at considerable trade-offs in other specifications. To this end, we have begun designing and evaluating various new readout topologies centered around an attempt to parallelize the sensor readout. In this paper, we have designed, simulated, and started testing a new light-controlled oscillator topology with dual column and row readouts. We expect the parallel readout structure to offer greater speed and alleviate the trade-off typical in this topology, where slow pixels present a major framerate bottleneck.

Keywords: CMOS image sensors, high-speed capture, wide dynamic range, light controlled oscillator

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Authors: T. Angeline Priyanka, R. Ganesan

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Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described.

Keywords: quantum cellular automata, carry look ahead adder, ripple carry adder, lossy application, majority gate, crossover

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Authors: Temidayo Otunniyi

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This paper presents a low computational channelization algorithm for the multi-standards platform using poly phase implementation of a critically sampled hybrid Trigonometry generalized Discrete Fourier Transform, (HGDFT). An HGDFT channelization algorithm exploits the orthogonality of two trigonometry Fourier functions, together with the properties of Quadrature Mirror Filter Bank (QMFB) and Exponential Modulated filter Bank (EMFB), respectively. HGDFT shows improvement in its implementation in terms of high reconfigurability, lower filter length, parallelism, and medium computational activities. Type 1 and type 111 poly phase structures are derived for real-valued HGDFT modulation. The design specifications are decimated critically and over-sampled for both single and multi standards receiver platforms. Evaluating the performance of oversampled single standard receiver channels, the HGDFT algorithm achieved 40% complexity reduction, compared to 34% and 38% reduction in the Discrete Fourier Transform (DFT) and tree quadrature mirror filter (TQMF) algorithm. The parallel generalized discrete Fourier transform (PGDFT) and recombined generalized discrete Fourier transform (RGDFT) had 41% complexity reduction and HGDFT had a 46% reduction in oversampling multi-standards mode. While in the critically sampled multi-standard receiver channels, HGDFT had complexity reduction of 70% while both PGDFT and RGDFT had a 34% reduction.

Keywords: software defined radio, channelization, critical sample rate, over-sample rate

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Authors: Sina Mahdavi, Faeze Noruzpur, Aysuda Noruzpur

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This paper proposes a high linear, low power and wideband Variable Gain Amplifier (VGA) with a direct current (DC) gain range of -10.2dB to 60.7dB. By applying the proposed idea to the folded cascade amplifier, it is possible to achieve a 71dB DC gain, 35MHz (-3dB) bandwidth, accompanied by high linearity and low sensitivity as well. It is noteworthy that the proposed idea can be able to apply on every differential amplifier, too. Moreover, the total power consumption and unity gain bandwidth of the proposed VGA is 1.41mW with a power supply of 1.8 volts and 4.37GHz, respectively, and 0.8pF capacitor load is applied at the output nodes of the amplifier. Furthermore, the proposed structure is simulated in whole process corners and different temperatures in the region of -60 to +90 ºC. Simulations are performed for all corner conditions by HSPICE using the BSIM3 model of the 180nm CMOS technology and MATLAB software.

Keywords: variable gain amplifier, low power, low voltage, folded cascade, amplifier, DC gain

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Authors: Gaurav Prabhudesai, Gaetan Brill

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The sun's energy source comes from a hydrogen-to-helium thermonuclear reaction, generating a temperature of about 5760 K on its outer layer. On account of this high temperature, energy is radiated by the sun, a part of which reaches the earth. This sunlight, even after losing part of its energy en-route to scattering and absorption, provides a time and space averaged solar flux of 174.7 W/m^2 striking the earth’s surface. According to one study, the solar energy striking earth’s surface in one and a half hour is more than the energy consumption that was recorded in the year 2001 from all sources combined. Thus, technology for extraction of solar energy holds much promise for solving energy crisis. Of the many technologies developed in this regard, Concentrating Solar Power (CSP) plants with central solar tower and receiver system are very impressive because of their capability to provide a renewable energy that can be stored in the form of heat. One design of central receiver towers is an open cavity where sunlight is concentrated into by using mirrors (also called heliostats). This concentrated solar flux produces high temperature inside the cavity which can be utilized in an energy conversion process. The amount of energy captured is reduced by losses occurring at the cavity through all three modes viz., radiation to the atmosphere, conduction to the adjoining structure and convection. This study investigates the natural convection losses to the environment from the receiver. Computational fluid dynamics were used to simulate the fluid flow and heat transfer of the receiver; since no analytical solution can be obtained and no empirical correlations exist for the given geometry. The results provide guide lines for predicting natural convection losses for hexagonal and circular shaped open cavities. Additionally, correlations are given for various inclination angles and aspect ratios. These results provide methods to minimize natural convection through careful design of receiver geometry and modification of the inclination angle, and aspect ratio of the cavity.

Keywords: concentrated solar power (CSP), central receivers, natural convection, CFD, open cavities

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Authors: H. El-Kamchouchi, Heba Gaber, Fatma Ahmed, Dalia H. El-Kamchouchi

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Fault tolerance and data security are two important issues in modern communication systems. During the transmission of data between the sender and receiver, errors may occur frequently. Therefore, the sender must re-transmit the data to the receiver in order to correct these errors, which makes the system very feeble. To improve the scalability of the scheme, we present a proxy signature scheme with fault tolerance over an efficient and secure authenticated key agreement protocol based on the improved RSA system. Authenticated key agreement protocols have an important role in building a secure communications network between the two parties.

Keywords: fault tolerance, improved RSA, key agreement, proxy signature

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Authors: Myoung-Jin Kim, Chang-Bin Ha, Yeong-Seop Ahn, Hyoung-Kyu Song

Abstract:

This paper proposes a cooperative communication scheme for improve wireless communication performance. When the receiver is located in the edge of coverage, the signal from the transmitter is distorted for various reasons such as inter-cell interference (ICI), power reduction, incorrect channel estimation. In order to improve communication performance, the proposed scheme adds the relay. By the relay, the receiver has diversity gain. In this paper, two base stations, one relay and one destination are considered. The two base stations transmit same time to relay and destination. The relay forwarding to destination and the destination detects signals.

Keywords: cooperative communication, diversity gain, OFDM, MMSE

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Authors: Alaa Abdullah Altaee

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This paper presents an adaptive decision feedback equalizer (ADFE) for multi-Gbps serial links utilizing a fix-step error signal extracted from cross-points of received data symbols. The extracted signal is generated based on violation of received data symbols with minimum detection requirements at the clock and data recovery (CDR) stage. The iterations of the adaptation process search for the optimum feedback tap coefficients to maximize the data eye-opening and minimize the adaptation convergence time. The effectiveness of the proposed architecture is validated using the simulation results of a serial link designed in an IBM 130 nm 1.2V CMOS technology. The data link with variable channel lengths is analyzed using Spectre from Cadence Design Systems with BSIM4 device models.

Keywords: adaptive DFE, CMOS equalizer, error detection, serial links, timing jitter, wire-line communication

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Authors: Khalid Mahmud

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In this paper, an analytic approach is presented to evaluate the Bit Error Rate (BER) and round trip distance for a UWB chipless RFID system using diversity technique at the reader receiver using different modulation technique. The analysis is carried out with multiresonator based chipless RFID tags using frequency range from 3 GHz − 6 GHz and bandwidth of 500 M Hz in outdoor non-line-of-sight (NLOS) environment. SISO configuration is used to communicate from the reader to the tag and SIMO configuration is used do vice versa. Maximal Ratio Combining (MRC) technique is used in the reader. MPSK, DQPSK, DBPSK, BPSK, QPSK and DMPSK modulation techniques are considered with coherent demodulation to evaluate the BER performance. From the numerical analysis of the results, it is found that at a given BER maximum possible round trip distance can be achieved using DMPSK modulation technique. In addition, it has been proved that, while using DMPSK modulation technique, the application of diversity has very little effect on the overall improvement in reader receiver sensitivity and achievable distance. Finally the method not only proves to be a very good way for tag detection in case of a chipless RFID system but also gives a clear insight regarding the interrelationship between BER, read range, reader received power, number of receiving antenna in outdoor NLOS environment.

Keywords: EGC, MRC, BER, read range, diversity

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Authors: H. El-Kamchouchi, Heba Gaber, Fatma Ahmed, Dalia H. El-Kamchouchi

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Due to the rapid growth in modern communication systems, fault tolerance and data security are two important issues in a secure transaction. During the transmission of data between the sender and receiver, errors may occur frequently. Therefore, the sender must re-transmit the data to the receiver in order to correct these errors, which makes the system very feeble. To improve the scalability of the scheme, we present a secure proxy signature scheme with fault tolerance over an efficient and secure authenticated key agreement protocol based on RSA system. Authenticated key agreement protocols have an important role in building a secure communications network between the two parties.

Keywords: proxy signature, fault tolerance, rsa, key agreement protocol

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Authors: Kim Jin Sup

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This paper presents a vertical hall effect device using current-mode. Among different geometries that have been studied and simulated using COMSOL Multiphysics, optimized cross-shaped model displayed the best sensitivity. The cross-shaped model emerged as the optimum plate to fit the lowest noise and residual offset and the best sensitivity. The symmetrical cross-shaped hall plate is widely used because of its high sensitivity and immunity to alignment tolerances resulting from the fabrication process. The hall effect device has been designed using a 0.18-μm CMOS technology. The simulation uses the nominal bias current of 12μA. The applied magnetic field is from 0 mT to 20 mT. Simulation results achieved in COMSOL and validated with respect to the electrical behavior of equivalent circuit for Cadence. Simulation results of the one structure over the 13 available samples shows for the best geometry a current-mode sensitivity of 6.6 %/T at 20mT. Acknowledgment: This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No. R7117-16-0165, Development of Hall Effect Semiconductor for Smart Car and Device).

Keywords: vertical hall device, current-mode, crossed-shaped model, CMOS technology

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Authors: Mario A. Blanco, Nicholas Burkhardt

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An important problem in satellite communication systems which operate in the Ka and EHF frequency bands consists of the overall degradation in link performance of mobile terminals due to various types of degradations in the link/channel, such as fading, blockage of the link to the satellite (especially in urban environments), intentional as well as other types of interference, etc. In this paper, we focus primarily on the interference problem, and we develop a very efficient and cost-effective solution based on the use of fountain codes. We first introduce a satellite communications (SATCOM) terminal uplink interference channel model that is classically used against communication systems that use spread-spectrum waveforms. We then consider the use of fountain codes, with focus on Raptor codes, as our main mitigation technique to combat the degradation in link/receiver performance due to the interference signal. The performance of the receiver is obtained in terms of average probability of bit and message error rate as a function of bit energy-to-noise density ratio, Eb/N0, and other parameters of interest, via a combination of analysis and computer simulations, and we show that the use of fountain codes is extremely effective in overcoming the effects of intentional interference on the performance of the receiver and associated communication links. We then show this technique can be extended to mitigate other types of SATCOM channel degradations, such as those caused by channel fading, shadowing, and hard-blockage of the uplink signal.

Keywords: SATCOM, interference mitigation, fountain codes, turbo codes, cross-layer

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Salleh, Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics

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Authors: Zhai Yuan, Wu Xueqing

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This article statistics the technology which used by Chinese and foreign excellent players in the game, including types and serves areas,receive technology and effect and utilization ratio receiving and losing points. The sample is che videos which is world's top matches of excellent badminton athletes of che single, including Chinese players’ 43 games and foreign players’ 38 games. Conclusion: For the serving, Chinese and foreign single players are to give priority to forehand short-low serve and the long-high serve. And Chinese and foreign players in using forehand short-low serve and drive server exist significant differences; For the serves areas, Chinese and foreign players serve area is concentrated in area 1,5,6. Area 6 has the highest rate of all the district areas, following by the area 1and area 5. Among the 2ed serve area Sino-foreign player, there exist significant differences; In the receiver, when returning the frontcourt shutter, players is given priority to net lift and push. When returning the backcourt shutter, receiver's the best ball is smash, followed by clear and drop shot. Foreign players have higher utilization rate in smash than Chinese players in the backcourt; In the receiver result, Chinese players give priority to actively and equally situation than foreign players, but in negatively receiving is just opposite.

Keywords: badminton, woman’s singles, technique and tactics, comparative analysis

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Authors: Se-Mi Lim, Won-Jae Jung, Jin-Sup Kim, Jun-Seok Park, Hyung-Il Chae

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This paper presents a current-mode vertical hall device (VHD) structure using metal layers in a CMOS process. The proposed metal layer based vertical hall device (MLVHD) utilizes vertical connection among metal layers (from M1 to the top metal) to facilitate hall effect. The vertical metal structure unit flows a bias current Ibias from top to bottom, and an external magnetic field changes the current distribution by Lorentz force. The asymmetric current distribution can be detected by two differential-mode current outputs on each side at the bottom (M1), and each output sinks Ibias/2 ± Ihall. A single vertical metal structure generates only a small amount of hall effect of Ihall due to the short length from M1 to the top metal as well as the low conductivity of the metal, and a series connection between thousands of vertical structure units can solve the problem by providing NxIhall. The series connection between two units is another vertical metal structure flowing current in the opposite direction, and generates negative hall effect. To mitigate the negative hall effect from the series connection, the differential current outputs at the bottom (M1) from one unit merges on the top metal level of the other unit. The proposed MLVHD is simulated in a 3-dimensional model simulator in COMSOL Multiphysics, with 0.35 μm CMOS process parameters. The simulated MLVHD unit size is (W) 10 μm × (L) 6 μm × (D) 10 μm. In this paper, we use an MLVHD with 10 units; the overall hall device size is (W) 10 μm × (L)78 μm × (D) 10 μm. The COMSOL simulation result is as following: the maximum hall current is approximately 2 μA with a 12 μA bias current and 100mT magnetic field; This work was supported by Institute for Information & communications Technology Promotion(IITP) grant funded by the Korea government(MSIP) (No.R7117-16-0165, Development of Hall Effect Semiconductor for Smart Car and Device).

Keywords: CMOS, vertical hall device, current mode, COMSOL

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Authors: Patikineti Sreenivasulu, K. srinivasa Rao, A. Vinaya Babu

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The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits.

Keywords: power consumption, ultra-low power, leakage, sub threshold, MTCMOS

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Authors: M. Tawfik, X. Tonnellier, C. Sansom

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The Lens-Lens Beam Generator (LLBG) is a Fresnel-based optical concentrating technique which provides flexibility in selecting the solar receiver location compared to conventional techniques through generating a powerful concentrated collimated solar beam. In order to achieve that, two successive lenses are used and followed by a flat mirror. Hence the generated beam emerging from the LLBG has a high power flux which impinges on the target receiver, it is important to determine the precision of the system output. In this present work, mathematical investigation of different parameters affecting the precision of the output beam is carried out. These parameters include: Deflection in sun-facing lens and its holding arm, delay in updating the solar tracking system, and the flat mirror surface flatness. Moreover, relationships that describe the power lost due to the effect of each parameter are derived in this study.

Keywords: Fresnel lens, LLBG, solar concentrator, solar tracking

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Authors: Alexander Sutor, David Demetz

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We present methods for developing wireless and traceable sensors for photobioreactors or photoreactors in general. The main focus of application are reactors which are wirelessly powered. Due to the promising properties of the propagation of magnetic fields under water we implemented an inductive link with an on/off switched hartley-oscillator as transmitter and an LC-tank as receiver. For this inductive link we used a carrier frequency of 298 kHz. With this system we performed measurements to demonstrate the independence of the magnetic field from water or salty water. In contrast we showed the strongly reduced range of RF-transmitter-receiver systems at higher frequencies (433 MHz and 2.4 GHz) in water and in salty water. For implementing the traceability of the sensors, we performed measurements to show the well defined orientation of the magnetic field of a coil. This information will be used in future work for implementing an inductive link based traceability system for our sensors.

Keywords: wireless sensors, photoreactor, internal illumination, wireless power

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

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While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: power efficiency, static power consumption, dynamic power consumption, CMOS

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Authors: Yo-Sheng Lin, Chien-Chin Wang, Yun-Wen Lin, Chien-Yo Lee

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A wide band power amplifier (PA) for 60 GHz and 77 GHz direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises a cascode input stage with a wide band T-type input-matching network and inductive interconnection and load, followed by a common-source (CS) gain stage and a CS output stage. To increase the saturated output power (PSAT) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss transmission-line inductors are used at the input and output terminals of each of the output stages for wide band input and output impedance matching to 100 ohm. This in turn results in further PSAT and PAE enhancement. The PA consumes 92.2 mW and achieves maximum power gain (S21) of 23.3 dB at 56 GHz, and S21 of 21.7 dB and 14 dB, respectively, at 60 GHz and 77 GHz. In addition, the PA achieves excellent saturated output power (PSAT) of 10.6 dB and maximum power added efficiency (PAE) of 12.3% at 60 GHz. At 77 GHz, the PA achieves excellent PSAT of 10.4 dB and maximum PAE of 6%. These results demonstrate the proposed wide band PA architecture is very promising for 60 GHz wireless personal local network (WPAN) and 77 GHz automobile radar systems.

Keywords: 60 GHz, 77 GHz, PA, WPAN, automotive radar

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Authors: Alibakhsh Kasaeian, Mohammad Sameti, Zahra Noori, Mona Rastgoo Bahambari

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Nowadays, the parabolic trough solar collector technology has become the most promising large-scale technology among various solar thermal generations. In this paper, a detailed numerical heat transfer model for a parabolic trough collector with nanofluid is presented based on the finite difference approach for which a MATLAB code was developed. The model was used to simulate the performance of a parabolic trough solar collector’s linear receiver, called a heat collector element (HCE). In this model, the heat collector element of the receiver was discretized into several segments in axial directions and energy balances were used for each control volume. All the heat transfer correlations, the thermodynamic equations and the optical properties were considered in details and the set of algebraic equations were solved simultaneously using iterative numerical solutions. The modeling assumptions and limitations are also discussed, along with recommendations for model improvement.

Keywords: heat transfer, nanofluid, numerical analysis, trough

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Authors: Morsy Ahmed Morsy Ismail

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In this paper, the structure of a coherent homodyne receiver for the Binary Phase Shift Keying (BPSK) Optical Code Division Multiple Access (OCDMA) network is introduced based on the Multi-Length Weighted Modified Prime Code (ML-WMPC) for multimedia applications. The Bit Error Rate (BER) of this homodyne detection is evaluated as a function of the number of active users and the signal to noise ratio for different code lengths according to the multimedia application such as audio, voice, and video. Besides, the Mach-Zehnder interferometer is used as an external phase modulator in homodyne detection. Furthermore, the Multiple Access Interference (MAI) and the receiver noise in a shot-noise limited regime are taken into consideration in the BER calculations.

Keywords: OCDMA networks, bit error rate, multiple access interference, binary phase-shift keying, multimedia

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Authors: Yaacoub Tina, Youssef Roua, Radoi Emanuel, Burel Gilles

Abstract:

Recently, low-complexity sub-Nyquist sampling schemes based on the Finite Rate of Innovation (FRI) theory have been introduced to sample parametric signals at minimum rates. The multichannel modulating waveforms (MCMW) is such an efficient scheme, where the received signal is mixed with an appropriate set of arbitrary waveforms, integrated and sampled at rates far below the Nyquist rate. In this paper, the MCMW scheme is adapted to the special case of ultra wideband (UWB) channel estimation, characterized by dense multipaths. First, an appropriate structure, which accounts for the bandpass spectrum feature of UWB signals, is defined. Then, a novel approach to decrease the number of processing channels and reduce the complexity of this sampling scheme is presented. Finally, the proposed concepts are validated by simulation results, obtained with real filters, in the framework of a coherent Rake receiver.

Keywords: coherent rake receiver, finite rate of innovation, sub-nyquist sampling, ultra wideband

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