Search results for: reconfigurable circuits

Authors: S. Padmapriya, V. Lakshmi Prabha

Abstract:

In this paper, an efficient reconfigurable fixed-point Least Mean Square Adaptive FIR filter is proposed. The proposed architecture has two methods of operation: one is area efficient design and the other is optimized power. Pipelining of the adder blocks and partial product generator are used to achieve low area and reversible logic is used to obtain low power design. Depending upon the input samples and filter coefficients, one of the techniques is chosen. Least-Mean-Square adaptation is performed to update the weights. The architecture is coded using Verilog and synthesized in cadence encounter 0.18μm technology. The synthesized results show that the area reduction ratio of the proposed when compared with conventional technique is about 1.2%.

Keywords: adaptive filter, carry select adder, least mean square algorithm, reversible logic

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Authors: Tesfaw Belayneh Abebe

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Integrating low-altitude earth orbit (LEO) satellites and unmanned aerial vehicles (UAVs) within a non-terrestrial network (NTN) with the assistance of reconfigurable intelligent surfaces (RIS), we investigate the problem of how to enhance throughput through integrated LEO satellites and UAVs with the assistance of RIS. We propose a method to jointly optimize the associations with the LEO satellite, the 3D trajectory of the UAV, and the phase shifts of the RIS to maximize communication throughput for RIS-assisted integrated LEO satellite and UAV-enabled wireless communications, which is challenging due to the time-varying changes in the position of the LEO satellite, the high mobility of UAVs, an enormous number of possible control actions, and also the large number of RIS elements. Utilizing a multi-agent double deep Q-network (MADDQN), our approach dynamically adjusts LEO satellite association, UAV positioning, and RIS phase shifts. Simulation results demonstrate that our method significantly outperforms baseline strategies in maximizing throughput. Lastly, thanks to the integrated network and the RIS, the proposed scheme achieves up to 65.66x higher peak throughput and 25.09x higher worst-case throughput.

Keywords: integrating low-altitude earth orbit (LEO) satellites, unmanned aerial vehicles (UAVs) within a non-terrestrial network (NTN), reconfigurable intelligent surfaces (RIS), multi-agent double deep Q-network (MADDQN)

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Authors: Jesus Kombaya, Nadia Hamani, Lyes Kermad

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The preservation of a company’s place on the market in such aggressive competition is becoming a survival challenge for manufacturers. In this context, survivors are only those who succeed to satisfy their customers’ needs as quickly as possible. The production system should be endowed with a certain level of flexibility to eliminate or reduce the rigidity of the production systems in order to facilitate the conversion and/or the change of system’s features to produce different products. Therefore, it is essential to guarantee the quality, the speed and the flexibility to survive in this competition. According to literature, this adaptability is referred to as the notion of "change". Indeed, companies are trying to establish a more flexible and agile manufacturing system through several reconfiguration actions. Reconfiguration contributes to the extension of the manufacturing system life cycle by modifying its physical, organizational and computer characteristics according to the changing market conditions. Reconfigurability is characterized by six key elements that are: modularity, integrability, diagnosability, convertibility, scalability and customization. In order to control the production systems, it is essential for manufacturers to make good use of this capability in order to be sure that the system has an optimal and adapted level of reconfigurability that allows it to produce in accordance with the set requirements. This document develops a measure of customization of reconfigurable production systems. These measures do not only impact the production system but also impact the product design and the process design, which can therefore serve as a guide for the customization of manufactured product. A case study is presented to show the use of the proposed approach.

Keywords: reconfigurable manufacturing systems, customization, measure, flexibility

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Authors: Nassim Ourabia, Malika Ourabia

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A new and efficient method is presented for the analysis of arbitrarily shaped discontinuities. The technique obtains closed form expressions for the equivalent circuits which are used to model these discontinuities. Then it would be easy to handle and to characterize complicated structures like T and Y junctions, truncated junctions, arbitrarily shaped junctions, cascading junctions, and more generally planar multiport junctions. Another advantage of this method is that the edge line concept for arbitrary shape junctions operates with real parameters circuits. The validity of the method was further confirmed by comparing our results for various discontinuities (bend, filters) with those from HFSS as well as from other published sources.

Keywords: CAD analysis, contour integral approach, microwave circuits, s-parameters

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Authors: B. Manikandan, A. Vijayaprabhu

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The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area.

Keywords: DET, QCA, reversible logic gates, POS, SOP, latches, flip flops

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Authors: G. N. Srinivas, K. Raju

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This paper presents Markov processes for determining the reliability indices of distribution system. The continuous Markov modeling is applied to a complex radial distribution system and electrical equivalent circuits are developed for the modeling. In general PSPICE is being used for electrical and electronic circuits and various applications of power system like fault analysis, transient analysis etc. In this paper, the SPICE modeling equivalent circuits which are developed are applied in a novel way to Distribution System reliability analysis. These circuits are simulated using PSPICE software to obtain the state probabilities, the basic and performance indices. Thus the basic indices and the performance indices obtained by this method are compared with those obtained by FMEA technique. The application of the concepts presented in this paper are illustrated and analyzed for IEEE-Roy Billinton Test System (RBTS).

Keywords: distribution system, Markov Model, reliability indices, spice simulation

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Authors: Abdollah Kavousi Fard

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This paper addresses the optimal scheduling of hybrid reconfigurable microgrids considering hybrid electric vehicle charging demands. A stochastic framework based on unscented transform to model the high uncertainties of renewable energy sources including wind turbine and photovoltaic panels, as well as the hybrid electric vehicles’ charging demand. In order to get to the optimal scheduling, the network reconfiguration is employed as an effective tool for changing the power supply path and avoiding possible congestions. The simulation results are analyzed and discussed in three different scenarios including coordinated, uncoordinated and smart charging demand of hybrid electric vehicles. A typical grid-connected microgrid is employed to show the satisfying performance of the proposed method.

Keywords: microgrid, renewable energy sources, reconfiguration, optimization

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Authors: Abdelghani Alidra, Mohamed Tahar Kimour

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Genetic algorithm must adapt themselves at design time to cope with the search problem specific requirements and at runtime to balance exploration and convergence objectives. In a previous article, we have shown that modeling and implementing Genetic Algorithms (GA) using the software product line (SPL) paradigm is very appreciable because they constitute a product family sharing a common base of code. In the present article we propose to extend the use of the feature model of the genetic algorithms family to model the potential states of the GA in what is called a Dynamic Software Product Line. The objective of this paper is the systematic generation of a reconfigurable architecture that supports the dynamic of the GA and which is easily deduced from the feature model. The resultant GA is able to perform dynamic reconfiguration autonomously to fasten the convergence process while producing better solutions. Another important advantage of our approach is the exploitation of recent advances in the domain of dynamic SPLs to enhance the performance of the GAs.

Keywords: self-adaptive genetic algorithms, software engineering, dynamic software product lines, reconfigurable architecture

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Authors: Lakhdar Zaid, Albane Sangiovanni

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A reconfigurable microstrip patch antenna with polyphase filter for polarization diversity and cross polarization filtering operation is presented in this paper. In our approach, a polyphase filter is used to obtain the four 90° phase shift outputs to feed a square microstrip patch antenna. The antenna can be switched between four states of polarization in transmission as well as in receiving mode. Switches are interconnected with the polyphase filter network to produce left-hand circular polarization, right-hand circular polarization, horizontal linear polarization, and vertical linear polarization. Additional advantage of using polyphase filter is its filtering capability for cross polarization filtering in right-hand circular polarization and left-hand circular polarization operation. The theoretical and simulated results demonstrated that polyphase filter is a good candidate to drive microstrip patch antenna to accomplish polarization diversity and cross polarization filtering operation.

Keywords: active antenna, polarization diversity, patch antenna, polyphase filter

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Authors: Getaneh Berie Tarekegn

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Wireless communication via unmanned aerial vehicles (UAVs) has drawn a great deal of attention due to its flexibility in establishing line-of-sight (LoS) communications. However, in complex urban and dynamic environments, the movement of UAVs can be blocked by trees and high-rise buildings that obstruct directional paths. With reconfigurable intelligent surfaces (RIS), this problem can be effectively addressed. To achieve this goal, accurate channel estimation in RIS-assisted UAV-enabled wireless communications is crucial. This paper proposes an accurate channel estimation model using long short-term memory (LSTM) for a multi-user RIS-assisted UAV-enabled wireless communication system. According to simulation results, LSTM can improve the channel estimation performance of RIS-assisted UAV-enabled wireless communication.

Keywords: channel estimation, reconfigurable intelligent surfaces, long short-term memory, unmanned aerial vehicles

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Salleh, Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics

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Authors: Muhammad Haitham Albahnassi, Adnan Malki, Shokri Almekdad

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In this paper, a method for reconfiguring bandwidth in a circular dual-mode resonator is presented. The method concerns the optimized geometry of a structure that may be used to host the tuning elements, which are typically RF (Radio Frequency) switches. The tuning elements themselves, and their performance during tuning, are not the focus of this paper. The designed resonator is able to reconfigure its fractional bandwidth by adjusting the inter-coupling level between the degenerate modes, while at the same time improving its response by adjusting the external-coupling level and keeping the center frequency fixed. The inter-coupling level has been adjusted by changing the dimensions of the perturbation element, while the external-coupling level has been adjusted by changing one of the feeder dimensions. The design was arrived at via optimization. Agreeing simulation and measurement results of the designed and implemented filters showed good improvements in return loss values and the stability of the center frequency.

Keywords: dual-mode resonators, perturbation theory, reconfigurable filters, software defined radio, cognitine radio

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Authors: M. Abou Al-alaa, H. A. Elsadek, E. A. Abdallah, E. A. Hashish

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A square patch antenna with both frequency and polarization reconfigurability is presented. The antenna consists of a square patch with coplanar feed on the ground plane. On the patch side, there is a parasitic square ring that is responsible for changing the antenna polarization. On the ground plane, there is a rectangular slot. By changing of length of this slot, the antenna resonance frequency can be changed. The antenna operates at 1.57 and 2.45 GHz that used in GPS and Bluetooth applications, respectively. The length of the slot in the proposed antenna is 40 mm, and the antenna operates at the lower frequency (1.57 GHz). By using switches in the ground plane the slot length can be adjust to 24 mm, so the antenna operates at upper frequency (2.45 GHz). Two switches are mounted on the parasitic ring at optimized positions. By switching between the different states of these two switches, the proposed antenna operates with linear polarization (LP) and circular polarization (CP) at each operating frequency. The antenna gain at 1.57 and 2.45 GHz are 5.9 and 7.64 dBi, respectively. The antenna is analyzed using the CST Microwave Studio. The proposed antenna was fabricated and measured. Results comparison shows good agreement. The antenna has applications in several wireless communication systems.

Keywords: microstrip patch antenna, reconfigurable antenna, frequency reconfigurability, polarization reconfigurability, parasitic square ring, linear polarization, circular polarization

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Authors: Lokes Parvatha Kumaran S., Sakthi Jay Mahenthar C., Sathyaprakash P., Jayakumar V., Shobanadevi A.

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With the evolution of technology, the need to solve complex computational problems like machine learning and deep learning has shot up. But even the most powerful classical supercomputers find it difficult to execute these tasks. With the recent development of quantum computing, researchers and tech-giants strive for new quantum circuits for machine learning tasks, as present works on Quantum Machine Learning (QML) ensure less memory consumption and reduced model parameters. But it is strenuous to simulate classical deep learning models on existing quantum computing platforms due to the inflexibility of deep quantum circuits. As a consequence, it is essential to design viable quantum algorithms for QML for noisy intermediate-scale quantum (NISQ) devices. The proposed work aims to explore Variational Quantum Circuits (VQC) for Deep Reinforcement Learning by remodeling the experience replay and target network into a representation of VQC. In addition, to reduce the number of model parameters, quantum information encoding schemes are used to achieve better results than the classical neural networks. VQCs are employed to approximate the deep Q-value function for decision-making and policy-selection reinforcement learning with experience replay and the target network.

Keywords: quantum computing, quantum machine learning, variational quantum circuit, deep reinforcement learning, quantum information encoding scheme

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Authors: F. Amirarfaei, K. Khorasani

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In this paper, reconfigurable consensus achievement of a team of agents with marginally stable linear dynamics and single input channel has been considered. The control algorithm is based on a first order linear protocol. After occurrence of a LOE fault in one of the actuators, using the imperfect information of the effectiveness of the actuators from fault detection and identification module, the control gain is redesigned in a way to still reach consensus. The idea is based on the modeling of change in effectiveness as change of Laplacian matrix. Then as special cases of this class of systems, a team of single integrators as well as double integrators are considered and their behavior subject to a LOE fault is considered. The well-known relative measurements consensus protocol is applied to a leaderless team of single integrator as well as double integrator systems, and Gersgorin disk theorem is employed to determine whether fault occurrence has an effect on system stability and team consensus achievement or not. The analyses show that loss of effectiveness fault in actuator(s) of integrator systems affects neither system stability nor consensus achievement.

Keywords: multi-agent system, actuator fault, stability analysis, consensus achievement

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Authors: Zhangquan Zhou, Guilin Qi

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Materialization is an important reasoning service for applications built on the Web Ontology Language (OWL). To make materialization efficient in practice, current research focuses on deciding tractability of an ontology language and designing parallel reasoning algorithms. However, some well-known large-scale ontologies, such as YAGO, have been shown to have good performance for parallel reasoning, but they are expressed in ontology languages that are not parallelly tractable, i.e., the reasoning is inherently sequential in the worst case. This motivates us to study the problem of parallel tractability of ontology materialization from a theoretical perspective. That is we aim to identify the ontologies for which materialization is parallelly tractable, i.e., in the NC complexity. Since the NC complexity is defined based on Boolean circuit that is widely used to investigate parallel computing problems, we first transform the problem of materialization to evaluation of Boolean circuits, and then study the problem of parallel tractability based on circuits. In this work, we focus on datalog rewritable ontology languages. We use Boolean circuits to identify two classes of datalog rewritable ontologies (called parallelly tractable classes) such that materialization over them is parallelly tractable. We further investigate the parallel tractability of materialization of a datalog rewritable OWL fragment DHL (Description Horn Logic). Based on the above results, we analyze real-world datasets and show that many ontologies expressed in DHL belong to the parallelly tractable classes.

Keywords: ontology materialization, parallel reasoning, datalog, Boolean circuit

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Jalal M. Abdallah

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This paper presents experimental studies carried out on a three phase transformer to investigate and develop the transformer models, which help in testing procedures, describing and evaluating the transformer dielectric conditions process and methods such as: the partial discharge (PD) localization in windings. The measurements are based on the transfer function methods in transformer windings by frequency response analysis (FRA). Numbers of tests conditions were applied to obtain the sensitivity frequency responses of a transformer for different type of faults simulated in a particular phase. The frequency responses were analyzed for the sensitivity of different test conditions to detect and identify the starting of small faults, which are sources of PD. In more detail, the aim is to explain applicability and sensitivity of advanced PD measurements for small short circuits and its localization. The experimental results presented in the paper will help in understanding the sensitivity of FRA measurements in detecting various types of internal winding short circuits in the transformer.

Keywords: frequency response analysis (FRA), measurements, transfer function, transformer

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Authors: Kaiwen Zheng, Wanting Zhou, Nan Tang, Lei Li, Yuanhang He

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The integrated circuit industry has become a cornerstone of the information society, finding widespread application in areas such as industry, communication, medicine, and aerospace. However, with the increasing complexity of integrated circuits, Hardware Trojans (HTs) implanted by attackers have become a significant threat to their security. In this paper, we proposed a hardware trojan detection method for large-scale circuits. As HTs introduce physical characteristic changes such as structure, area, and power consumption as additional redundant circuits, we proposed a machine-learning-based hardware trojan detection method based on the physical characteristics of gate-level netlists. This method transforms the hardware trojan detection problem into a machine-learning binary classification problem based on physical characteristics, greatly improving detection speed. To address the problem of imbalanced data, where the number of pure circuit samples is far less than that of HTs circuit samples, we used the SMOTETomek algorithm to expand the dataset and further improve the performance of the classifier. We used three machine learning algorithms, K-Nearest Neighbors, Random Forest, and Support Vector Machine, to train and validate benchmark circuits on Trust-Hub, and all achieved good results. In our case studies based on AES encryption circuits provided by trust-hub, the test results showed the effectiveness of the proposed method. To further validate the method’s effectiveness for detecting variant HTs, we designed variant HTs using open-source HTs. The proposed method can guarantee robust detection accuracy in the millisecond level detection time for IC, and FPGA design flows and has good detection performance for library variant HTs.

Keywords: hardware trojans, physical properties, machine learning, hardware security

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Authors: Arabi Abderrazak, Bourouba Nacerdine, Ayad Mouloud, Belaout Abdeslam

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In this paper, a new test technique of analog circuits using time mode simulation is proposed for the single catastrophic faults detection in analog circuits. This test process is performed to overcome the problem of catastrophic faults being escaped in a DC mode test applied to the inverter amplifier in previous research works. The circuit under test is a second-order low pass filter constructed around this type of amplifier but performing a function that differs from that of the previous test. The test approach performed in this work is based on two key- elements where the first one concerns the unique square pulse signal selected as an input vector test signal to stimulate the fault effect at the circuit output response. The second element is the filter response conversion to a square pulses sequence obtained from an analog comparator. This signal conversion is achieved through a fixed reference threshold voltage of this comparison circuit. The measurement of the three first response signal pulses durations is regarded as fault effect detection parameter on one hand, and as a fault signature helping to hence fully establish an analog circuit fault diagnosis on another hand. The results obtained so far are very promising since the approach has lifted up the fault coverage ratio in both modes to over 90% and has revealed the harmful side of faults that has been masked in a DC mode test.

Keywords: analog circuits, analog faults diagnosis, catastrophic faults, fault detection

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Authors: Azizi Cherifa, O. Benzaoui

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The thermal aspects in the design of power circuits often deserve as much attention as pure electric components aspects as the operating temperature has a direct influence on their static and dynamic characteristics. MOSFET is fundamental in the circuits, it is the most widely used device in the current production of semiconductor components using their honorable performance. The aim of this contribution is devoted to the effect of the temperature on the properties of MOSFETs. The study enables us to calculate the drain current as function of bias in both linear and saturated modes. The effect of temperature is evaluated using a numerical simulation, using the laws of mobility and saturation velocity of carriers as a function of temperature.

Keywords: temperature, MOSFET, mobility, transistor

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Authors: Nahla Elazab, Mohamed Aboudina, Ghada Ibrahim, Hossam Fahmy, Ahmed Khalil

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This paper presents the developed memristor based demodulators for eight circular Quadrature Amplitude Modulation (QAM) and Binary Frequency Shift Keying (BFSK) operating at relatively high frequency. In our implementations, the experimental-based ‘nonlinear’ dopant drift model is adopted along with the proposed circuits providing incorporation of all known non-idealities of practically realized memristor and gaining high operation frequency. The suggested designs leverage the distinctive characteristics of the memristor device, definitely, its changeable average memristance versus the frequency, phase and amplitude of the periodic excitation input. The proposed demodulators feature small integration area, low power consumption, and easy implementation. Moreover, the proposed QAM demodulator precludes the requirement for the carrier recovery circuits. In doing so, the designs were validated by transient simulations using the nonlinear dopant drift memristor model. The simulations results show high agreement with the theory presented.

Keywords: BFSK, demodulator, high frequency memristor applications, memristor based analog circuits, nonlinear dopant drift model, QAM

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Authors: Suleiman Babani, Jazuli Sanusi Kazaure

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In this paper, two coupled-line couplers are designed and simulated using stripline technology. The coupled-line couplers (A and B) are designed with different values of coupling coefficient 6dB and 10dB respectively. Both of circuits have a coupled output port, a through output port and an isolated output port. Moreover, both circuits are tuned to function around 2.45 GHz. The design results are presented by simulation results obtained using ADS 2012.08 (Advanced Design System) software.

Keywords: ADS, coupled-line coupler, directional coupler, stripline

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Authors: Patikineti Sreenivasulu, K. srinivasa Rao, A. Vinaya Babu

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The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits.

Keywords: power consumption, ultra-low power, leakage, sub threshold, MTCMOS

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Authors: Jun-Geol Park, Kyoung-Il Do, Min-Ju Kwon, Kyung-Hyun Park, Yong-Seo Koo

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This paper analyzed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuits with the turn-on time characteristics. The structures are the LVTSCR (Low Voltage Triggered SCR), the ZTSCR (Zener Triggered SCR) and the PTSCR (P-Substrate Triggered SCR). The three structures are for the 5V power clamp. In general, the structures with the low trigger voltage structure can have the fast turn-on characteristics than other structures. All the ESD protection circuits have the low trigger voltage by using the N+ bridge region of LVTSCR, by using the zener diode structure of ZTSCR, by increasing the trigger current of PTSCR. The simulation for the comparison with the turn-on time was conducted by the Synopsys TCAD simulator. As the simulation results, the LVTSCR has the turn-on time of 2.8 ns, ZTSCR of 2.1 ns and the PTSCR of 2.4 ns. The HBM simulation results, however, show that the PTSCR is the more robust structure of 430K in HBM 8kV standard than 450K of LVTSCR and 495K of ZTSCR. Therefore the PTSCR is the most effective ESD protection circuit for the 5V power clamp.

Keywords: ESD, SCR, turn-on time, trigger voltage, power clamp

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Authors: Sangguk Ahn, Youngyu Kim, Jaheon Gu, Gyoutae Park

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In this paper, we developed a dual gas leak instrument to detect Hydrocarbon (HC) and Monoxide (CO) gases. To two kinds of gases, it is necessary to design compact structure for sensors. And then it is important to draw sensing circuits such as measuring, amplifying and filtering. After that, it should be well programmed with robust, systematic and module coding methods. In center of them, improvement of accuracy and initial response time are a matter of vital importance. To manufacture distinguished gas leak detector, we applied intrinsically safe explosion-proof structure to lithium ion battery, main circuits, a pump with motor, color LCD interfaces and sensing circuits. On software, to enhance measuring accuracy we used numerical analysis such as Lagrange and Neville interpolation. Performance test result is conducted by using standard Methane with seven different concentrations with three other products. We want raise risk prevention and efficiency of gas safe management through distributing to the field of gas safety. Acknowledgment: This study was supported by Small and Medium Business Administration under the research theme of ‘Commercialized Development of a portable intrinsically safe explosion-proof type dual gas leak detector’, (task number S2456036).

Keywords: gas leak, dual gas detector, intrinsically safe, explosion proof

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Authors: Biswarup Mukherjee, Aniruddha Ghosal

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In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Fawzia Al-Sakeer, Hassan Aldeeb

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Development in the communications field is proceeding at an amazing speed, which has led researchers to improve and develop electronic circuits by increasing their efficiency and reducing their size to reduce the weight of electronic devices. One of the most important of these circuits is the band-pass filter, which is what made us carry out this research, which aims to use an alternate technology to design a dual band-pass filter by using a stepped impedance microstrip transmission line. We designed a filter that works at two center frequency bands by designing with the ADS program, and the results were excellent, as we obtained the two design frequencies, which are 1 and 3GHz, and the values of insertion loss S11, which was more than 21dB with a small area.

Keywords: band pass filter, dual band band-pass filter, ADS, microstrip filter, stepped impedance

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Authors: Ali Mashayekh, Mahdiye Khorasani, Thomas weyh

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The demand for battery electric vehicles (BEV) is steadily increasing, and it can be assumed that electric mobility will dominate the market for individual transportation in the future. Regarding BEVs, the focus of state-of-the-art research and development is on vehicle batteries since their properties primarily determine vehicles' characteristic parameters, such as price, driving range, charging time, and lifetime. State-of-the-art battery packs consist of invariable configurations of battery cells, connected in series and parallel. A promising alternative is battery systems based on multilevel inverters, which can alter the configuration of the battery cells during operation via semiconductor switches. The main benefit of such topologies is that a three-phase AC voltage can be directly generated from the battery pack, and no separate power inverters are required. Therefore, modular battery systems based on different multilevel inverter topologies and reconfigurable battery systems are currently under investigation. Another advantage of the multilevel concept is that the possibility to reconfigure the battery pack allows battery cells with different states of charge (SoC) to be connected in parallel, and thus low-loss balancing can take place between such cells. In contrast, in conventional battery systems, parallel connected (hard-wired) battery cells are discharged via bleeder resistors to keep the individual SoCs of the parallel battery strands balanced, ultimately reducing the vehicle range. Different multilevel inverter topologies and reconfigurable batteries have been described in the available literature that makes the before-mentioned advantages possible. However, what has not yet been described is how an intelligent operating algorithm needs to look like to keep the SoCs of the individual battery strands of a modular battery system with integrated power electronics balanced. Therefore, this paper suggests an SoC balancing approach for Battery Modular Multilevel Management (BM3) converter systems, which can be similarly used for reconfigurable battery systems or other multilevel inverter topologies with parallel connectivity. The here suggested approach attempts to simultaneously utilize all converter modules (bypassing individual modules should be avoided) because the parallel connection of adjacent modules reduces the phase-strand's battery impedance. Furthermore, the presented approach tries to reduce the number of switching events when changing the switching state combination. Thereby, the ohmic battery losses and switching losses are kept as low as possible. Since no power is dissipated in any designated bleeder resistors and no designated active balancing circuitry is required, the suggested approach can be categorized as a proactive balancing approach. To verify the algorithm's validity, simulations are used.

Keywords: battery management system, BEV, battery modular multilevel management (BM3), SoC balancing

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Authors: Mohamed Mahmoud

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This paper has developed an effect-cause analysis technique for fault diagnosis in digital circuits. The main algorithm of our technique is based on the Enhanced Deduction Algorithm, which processes the real response of the CUT to the applied test T to deduce the values of the internal lines. An experimental version of the algorithm has been implemented in C++. The code takes about 7592 lines. The internal values are determined based on the logic values under the permanent stuck-fault model. Using a backtracking strategy guarantees that the actual values are covered by at least one solution, or no solution is found.

Keywords: enhanced deduction algorithm, backtracking strategy, automatic test equipment, verfication

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