Search results for: open circuit test

Authors: Amit Kumar Sinha

Abstract:

A coal preparation plant typically operates with multiple beneficiation circuits to process individual size fractions of coal obtained from mine so that the targeted overall plant efficiency in terms of yield and ash is achieved. Conventional coal beneficiation plant in India or overseas operates generally in two methods of processing; coarse beneficiation with treatment in dense medium cyclones or in baths and fines beneficiation with treatment in flotation cell. This paper seeks to address the proven application of intermediate circuit along with coarse and fines circuit in Jamadoba New Coal Preparation Plant of capacity 2 Mt/y to treat -0.5 mm+0.25 mm size particles in reflux classifier. Previously this size of particles was treated directly in Flotation cell which had operational and metallurgical limitations which will be discussed in brief in this paper. The paper also details test work results performed on the representative samples of TSL coal washeries to determine the top size of intermediate and fines circuit and discusses about the overlapping process of intermediate circuit and how it is process wise suitable to beneficiate misplaced particles from coarse circuit and fines circuit. This paper also compares the separation efficiency (Ep) of various intermediate circuit process equipment and tries to validate the use of reflux classifier over fine coal DMC or spirals. An overview of Modern coal preparation plant treating Indian coal especially Washery Grade IV coal with reference to Jamadoba New Coal Preparation Plant which was commissioned in 2018 with basis of selection of equipment and plant profile, application of reflux classifier in intermediate circuit and process design criteria is also outlined in this paper.

Keywords: intermediate circuit, overlapping process, reflux classifier

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Authors: Razieh Teimouri

Abstract:

Electrical modelling of Cu (In,Ga)Se₂ thin film solar cells is carried out with compositionally graded absorber and CdS buffer layer. Simulation results are compared with experimental data. Surface defect layers (SDL) are located in CdS/CIGS interface for improving open circuit voltage simulated structure through the analysis of the interface is investigated with or without this layer. When SDL removed, by optimizing the conduction band offset (CBO) position of the buffer/absorber layers with its recombination mechanisms and also shallow donor density in the CdS, the open circuit voltage increased significantly. As a result of simulation, excellent performance can be obtained when the conduction band of window layer positions higher by 0.2 eV than that of CIGS and shallow donor density in the CdS was found about 1×10¹⁸ (cm⁻³).

Keywords: CIGS solar cells, thin film, SCAPS, buffer layer, conduction band offset

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Authors: Moustafa Osman Mohammed

Abstract:

The photocurrent generations are influencing ultra-high efficiency solar cells based on self-assembled quantum dot (QD) nanostructures. Nanocrystal quantum dots (QD) provide a great enhancement toward solar cell efficiencies through the use of quantum confinement to tune absorbance across the solar spectrum enabled multi-exciton generation. Based on theoretical predictions, QDs have potential to improve systems efficiency in approximate regular electrons excitation intensity greater than 50%. In solar cell devices, an intermediate band formed by the electron levels in quantum dot systems. The spatial architecture is exploring how can solar cell integrate and produce not only high open circuit voltage (> 1.7 eV) but also large short-circuit currents due to the efficient absorption of sub-bandgap photons. In the proposed QD system, the structure allows barrier material to absorb wavelengths below 700 nm while multi-photon processes in the used quantum dots to absorb wavelengths up to 2 µm. The assembly of the electronic model is flexible to demonstrate the atoms and molecules structure and material properties to tune control energy bandgap of the barrier quantum dot to their respective optimum values. In terms of energy virtual conversion, the efficiency and cost of the electronic structure are unified outperform a pair of multi-junction solar cell that obtained in the rigorous test to quantify the errors. The milestone toward achieving the claimed high-efficiency solar cell device is controlling the edge causes of energy bandgap between the barrier material and quantum dot systems according to the media design limits. Despite this remarkable potential for high photocurrent generation, the achievable open-circuit voltage (Voc) is fundamentally limited due to non-radiative recombination processes in QD solar cells. The orientation of voltage recovery system is compared theoretically with experimental Voc variation in mediation upper–limit obtained one diode modeling form at the cells with different bandgap (Eg) as classified in the proposed spatial architecture. The opportunity for improvement Voc is valued approximately greater than 1V by using smaller QDs through QD solar cell recovery systems as confined to other micro and nano operations states.

Keywords: nanotechnology, photovoltaic solar cell, quantum systems, renewable energy, environmental modeling

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Authors: Davit Mirzoyan, Ararat Khachatryan

Abstract:

A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: detection, monitoring, process corner, process variation

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Authors: Nor Zaidi Haron, Fauziyah Salehuddin, Norsuhaidah Arshad, Sani Irwan Salim

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Resistive random access memories (RRAMs) are one of the main candidates for future computer memories. However, due to their tiny size and immature device technology, the quality of the outgoing RRAM chips is seen as a serious issue. Defective RRAM cells might behave differently than existing semiconductor memories (Dynamic RAM, Static RAM, and Flash), meaning that they are difficult to be detected using existing test schemes. This paper presents an enhanced test scheme, referred to as Programmable Short Write Time (PSWT) that is able to improve the detection of faulty RRAM cells. It is developed by applying multiple weak write operations, each with different time durations. The test circuit embedded in the RRAM chip is made programmable in order to supply different weak write times during testing. The RRAM electrical model is described using Verilog-AMS language and is simulated using HSPICE simulation tools. Simulation results show that the proposed test scheme offers better open-resistive fault detection compared to existing test schemes.

Keywords: memory fault, memory test, design-for-testability, resistive random access memory

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Authors: Benmoussa Dennai, H. Benslimane, A. Helmaoui

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Photo voltaic conversion is the direct conversion of electromagnetic energy into electrical energy continuously. This electromagnetic energy is the most solar radiation. In this work we performed a computer modelling using AMPS 1D optimization of hetero-junction solar cells GaInP/GaAs configuration for p/ n. We studied the influence of the thickness the base layer in the cell offers on the open circuit voltage, the short circuit current and efficiency.

Keywords: optimization, photovoltaic cell, GaInP / GaAs AMPS-1D, hetetro-junction

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Authors: N. H. S. Mustafa, N. M. Yatim

Abstract:

Thermoelectric materials arrange in segmented design could increase the conversion of heat to electricity performance. This is due to the properties of materials that perform peak at narrow temperature range. Performance of the materials determines by dimensionless figure-of-merit, ZT which consist of thermoelectric properties namely Seebeck coefficient, electrical resistivity, and thermal conductivity. Since different materials were arrange in segmented, determination of ZT cannot be measured using the conventional approach. Therefore, this research used 'open-short circuit' technique to measure the segmented performance. Segmented thermoelectric materials consist of bismuth telluride, and lead telluride was segmented together under cold press technique. The results show thermoelectric properties measured is comparable with calculated based on commercially available of individual material. Performances of segmented sample under different polarity also indicate dependability of material with position and temperature. Segmented materials successfully measured under real condition and optimization of the segmented can be designed from the study of polarity change.

Keywords: thermoelectric, segmented, ZT, polarity, performance

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Authors: Benmoussa Dennai, H. Benslimane, A. Helmaoui

Abstract:

Photovoltaic conversion is the direct conversion of electromagnetic energy into electrical energy continuously. This electromagnetic energy is the most solar radiation. In this work we performed a computer modelling using AMPS 1D optimization of hetero-junction solar cells GaInP / GaAs configuration for p / n. We studied the influence of the thickness the base layer in the cell offers on the open circuit voltage, the short circuit current and efficiency.

Keywords: optimization, photovoltaic cell, GaInP / GaAs AMPS-1D, hetetro-junction

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Authors: Moustapha H. Ibrahim, Dahir Abdourahman

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This document presents a short-circuit fault detection process in a photovoltaic (PV) system. The proposed method is developed in MATLAB/Simulink. It determines whatever the size of the installation number of the short circuit module. The proposed algorithm indicates the presence or absence of an abnormality on the power of the PV system through measures of hourly global irradiation, power output, and ambient temperature. In case a fault is detected, it displays the number of modules in a short circuit. This fault detection method has been successfully tested on two different PV installations.

Keywords: PV system, short-circuit, fault detection, modelling, MATLAB-Simulink

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Authors: Po-Hui Yang, Jing-Min Chen, Po-Yu Kuo, Chia-Chun Wu

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This paper proposed a high resolution Vernier Delay Line (VDL) measurement circuit with coarse and fine detection mechanism, which improved the trade-off problem between high resolution and less delay cells in traditional VDL circuits. And the measuring time of proposed measurement circuit is also under the high resolution requests. At first, the testing range of input signal which proposed high resolution delay line is detected by coarse detection VDL. Moreover, the delayed input signal is transmitted to fine detection VDL for measuring value with better accuracy. This paper is implemented at 0.18μm process, operating frequency is 100 MHz, and the resolution achieved 2.0 ps with only 16-stage delay cells. The test range is 170ps wide, and 17% stages saved compare with traditional single delay line circuit.

Keywords: vernier delay line, D-type flip-flop, DFF, metastable phenomenon

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Authors: Mohsen Bagheri, Ahmad Afifi

Abstract:

This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on instrumentation amplifier and it is useful for reducing offset in Wheatstone bridge. The obtained gain is 645 with 1 μv/°c equivalent drift and 1.58 mw power consumption. A Schmitt trigger and multiplexer circuit control output node. A high speed counter is designed in this work. The proposed circuit is designed and simulated in 0.18 μm CMOS technology with 1.8 v power supply.

Keywords: piezoresistive accelerometer, zero offset, Schmitt trigger, bidirectional reversible counter

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Authors: M. Y. Ismail, M. Inam

Abstract:

This paper presents equivalent circuit modeling of active planar reflectors which can be used for the detailed analysis and characterization of reflector performance in terms of lumped components. Equivalent circuit representation has been proposed for PIN diodes and liquid crystal based active planar reflectors designed within X-band frequency range. A very close agreement has been demonstrated between equivalent circuit results, 3D EM simulated results as well as measured scattering parameter results. In the case of measured results, a maximum discrepancy of 1.05dB was observed in the reflection loss performance, which can be attributed to the losses occurred during measurement process.

Keywords: Equivalent circuit modelling, planar reflectors, reflectarray antenna, PIN diode, liquid crystal

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Authors: Ararat Khachatryan, Davit Mirzoyan

Abstract:

In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: aging effect, HCI, NBTI, nanoscale

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Authors: Mahawish Masud, Muhammad Iqbal, M. U. Khan, Farooque Azam

Abstract:

Manual writing of test cases from functional requirements is a time-consuming task. Such test cases are not only difficult to write but are also challenging to maintain. Test cases can be drawn from the functional requirements that are expressed in natural language. However, manual test case generation is inefficient and subject to errors.  In this paper, we have presented a systematic procedure that could automatically derive test cases from user stories. The user stories are specified in a restricted natural language using a well-defined template.  We have also presented a detailed methodology for writing our test ready user stories. Our tool “Test-o-Matic” automatically generates the test cases by processing the restricted user stories. The generated test cases are executed by using open source Selenium IDE.  We evaluate our approach on a case study, which is an open source web based application. Effectiveness of our approach is evaluated by seeding faults in the open source case study using known mutation operators.  Results show that the test case generation from restricted user stories is a viable approach for automated testing of web applications.

Keywords: automated testing, natural language, restricted user story modeling, software engineering, software testing, test case specification, transformation and automation, user story, web application testing

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Authors: Hussein Al-bayaty

Abstract:

This paper presents a novel idea to show the ability to benefit of the harmonic currents which are produced on the load side of the power grid. The proposed circuit contributes in reduction of the total harmonic distortion (THD) percentage through adding a high pass filter to draw harmonic currents with 150 Hz and multiple frequencies a and convert them to DC current and then reconvert it to AC current with 50 Hz frequency in order to feed different loads. The circuit has been designed, investigated and simulated in the MATLAB, Simulink program; the results will be assessed and compared the two cases: firstly, the system without adding the new circuit. Secondly, with adding the high pas filter circuit to the power system.

Keywords: harmonics elimination, passive filters, Total Harmonic Distortion (THD), filter circuit

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Authors: Patel Himeshkumar Ashokbhai, Suchit Sharma, Arvind Kumar Garg

Abstract:

The purpose of this paper is to study the effect of change in feed rate on grinding circuit and cyclone efficiency in case of lead-zinc ore. The following experiments and analysis were conducted on beneficiation circuit of Sindesar Khurd (SK) mines under Hindustan Zinc Ltd. subsidiary of Vedanta Group of Companies, a leading producer of lead-Zinc, silver and cadmium (as by products) in India. Feed rate is an important variable in beneficiation circuit operation. Optimizing feed rate is indispensable for any grinding circuit and directly effects cyclone efficiency. The size analysis of ore in grinding circuit along with cyclone efficiency on varying feed rates establishes their interdependence. Feed rate determines retention time ore gets within grinding circuit. Retention time in turn determines degree of liberation of mineral. Inadequate liberation causes decreased circuit efficiency. In this paper we have studied the effect of varying feed rate on (1) D80 particle size of different sections of different streams of grinding circuit (2) Re-circulating load (3) Cyclone efficiency. As a conclusion, this study gives some clues to operate grinding circuits and hydro-cyclones in more efficient way regarding beneficiation of Lead-zinc ore.

Keywords: cyclone efficiency, feed rate, grinding circuit, re-circulating load

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Authors: Duanlei Yuan, Guangchao Yan, Zhanqing Chen, Xian Cheng

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This paper mainly focuses on the problem that high voltage circuit breaker’s closing and opening operation at random phase brings harmful electromagnetic transient effects on the power system. To repress the negative transient effects, a 35 kV SF6 phase-control circuit breaker equipped with electromagnetic force driving actuator is designed in this paper. Based on the constructed mathematical and structural models, the static magnetic field distribution and dynamic properties of the under loading actuator are simulated. The prototype of 35 kV SF6 phase-control circuit breaker is developed based on theories analysis and simulation. Tests are carried on to verify the operating reliability of the prototype. The developed circuit breaker can control its operating speed intelligently and switches with phase selection. Results of the tests and simulation prove that the phase-control circuit breaker is feasible for industrial applications.

Keywords: phase-control, circuit breaker, electromagnetic force driving actuator, tests and simulation

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Authors: Mohammed Panthakkal Abdul Muthalif, Shanmugasundaram Kanagaraj, Jumi Park, Hangyu Park, Youngson Choe

Abstract:

The present study reports the incorporation of calcium ions into the CuS counter electrodes (CEs) in order to modify the photovoltaic performance of quantum dot-sensitized solar cells (QDSSCs). Metal ion-doped CuS thin film was prepared by the chemical bath deposition (CBD) method on FTO substrate and used directly as counter electrodes for TiO₂/CdS/CdSe/ZnS photoanodes based QDSSCs. For the Ca-doped CuS thin films, copper nitrate and thioacetamide were used as anionic and cationic precursors. Calcium nitrate tetrahydrate was used as doping material. The surface morphology of Ca-doped CuS CEs indicates that the fragments are uniformly distributed, and the structure is densely packed with high crystallinity. The changes observed in the diffraction patterns suggest that Ca dopant can introduce increased disorder into CuS material structure. EDX analysis was employed to determine the elemental identification, and the results confirmed the presence of Cu, S, and Ca on the FTO glass substrate. The photovoltaic current density – voltage characteristics of Ca-doped CuS CEs shows the specific improvements in open circuit voltage decay (Voc) and short-circuit current density (Jsc). Electrochemical impedance spectroscopy results display that Ca-doped CuS CEs have greater electrocatalytic activity and charge transport capacity than bare CuS. All the experimental results indicate that 20% Ca-doped CuS CE based QDSSCs exhibit high power conversion efficiency (η) of 4.92%, short circuit current density of 15.47 mA cm⁻², open circuit photovoltage of 0.611 V, and fill factor (FF) of 0.521 under illumination of one sun.

Keywords: Ca-doped CuS counter electrodes, surface morphology, chemical bath deposition method, electrocatalytic activity

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Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

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In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Milad Kaboli

Abstract:

A new CMOS low voltage current-mode four-quadrant analog multiplier based on the squarer circuit with voltage output is presented. The proposed circuit is composed of a pair of current subtractors, a pair differential-input V-I converters and a pair of voltage squarers. The circuit was simulated using HSPICE simulator in standard 0.18 μm CMOS level 49 MOSIS (BSIM3 V3.2 SPICE-based). Simulation results show the performance of the proposed circuit and experimental results are given to confirm the operation. This topology of multiplier results in a high-frequency capability with low power consumption. The multiplier operates for a power supply ±1.2V. The simulation results of analog multiplier demonstrate a THD of 0.65% in 10MHz, a −3dB bandwidth of 1.39GHz, and a maximum power consumption of 7.1mW.

Keywords: analog processing circuit, WTA, LTA, low voltage

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Authors: Jeonghwan Jeon

Abstract:

Technology planning with both internal capacity and external resource is necessary for successful open innovation. Until now, many types of research have been conducted for this issue. However, technology planning for open innovation at the national level has not been researched sufficiently. This study proposes Open roadmap for open innovation at the national level. The proposed open roadmap can manage the inflow & outflow open innovation systematically. Six types of open roadmap are classified with respect to the innovation direction and characteristics. The proposed open roadmap is applied to the open innovation cases of the Roman period. The proposed open roadmap is expected to be helpful tool for technology policy planning at the national level.

Keywords: technology planning, open innovation, internal resource, external resource, technology management

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Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

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This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (V_th) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS process sensor, PVT sensor, threshold extractor circuit, Vth extractor circuit

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Authors: Bin-Wen Lan, Ying-Xin Chen, Hsueh-Cheng Yang

Abstract:

Liquefied petroleum gas is a fuel that has high octane number and low carbon number. This paper uses MSC-51 controller to investigate the effect of liquefied petroleum gas (LPG) on exhaust emissions for different engine speeds in a single cylinder, four-stroke and spark ignition engine. The results indicate that CO, CO2 and NOX exhaust emissions are lower with the use of LPG compared to the use of unleaded gasoline by using the developed controller. The open-loop in the LPG injection system was controlled by MCS-51 single chip. The results show that if a SI engine is operated with LPG fuel rather than gasoline fuel under the same conditions, significant reduction in exhaust emissions can be achieved. In summary, LPG has positive effects on main exhaust emissions such as CO, CO2 and NOX.

Keywords: LPG, control circuit, emission, MCS-51

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Authors: S. Masoud Barakati, Mohsen Rahmani Haredasht

Abstract:

Recently, the use of T-type nested neutral point clamped (T-NNPC) converter has increased in medium voltage applications. However, the T-NNPC converter architecture's reliability and continuous operation are at risk by including semiconductor switches. Semiconductor switches are a prone option for open-circuit faults. As a result, fault-tolerant converters are required to improve the system's reliability and continuous functioning. This study's primary goal is to provide a fault-tolerant T-NNPC converter configuration. In the proposed design utilizing the cold reservation approach, a redundant phase is considered, which replaces the faulty phase once the fault is diagnosed in each phase. The suggested fault-tolerant configuration can be easily implemented in practical applications due to the use of a simple PWM control mechanism. The performance evaluation of the proposed configuration under different scenarios in the MATLAB-Simulink environment proves its efficiency.

Keywords: T-type nested neutral point clamped converter, reliability, continuous operation, open-circuit faults, fault-tolerant converters

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Authors: Sun-Ki Hong, Nam-HeeByeon, Jung-Seop Lee, Tae-Sam Kang

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For Common R or R-L load to apply arbitrary voltage, the bridge traditional inverters don’t have any difficulties by PWM method. However for driving some piezoelectric actuator, arbitrary voltage not a pulse but a steady voltage should be applied. Piezoelectric load is considered as R-C load and its voltage does not decrease even though the applied voltage decreases. Therefore it needs some special inverter with circuit that can discharge the capacitive energy. Especially for unidirectional arbitrary voltage driving like as sine wave, it becomes more difficult problem. In this paper, a charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator is proposed. The circuit has charging and discharging switches for increasing and decreasing output voltage. With the proposed simple circuit, the load voltage can have any unidirectional level with tens of bandwidth because the load voltage can be adjusted by switching the charging and discharging switch appropriately. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: DC-DC converter, analog output voltage, sinusoidal drive, piezoelectric load, discharging circuit

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Authors: Peng Lu, Branimir Radisavljevic, Martin Seeger, Daniel Over, Torsten Votteler, Bernardo Galletti

Abstract:

CO₂-based gas mixtures exhibit huge potential as the interruption medium for replacing SF₆ in high voltage switchgears. In this paper, the recovery characteristics of dielectric strength of CO₂-O₂ mixture in the post arc phase after the current zero are presented. As representative examples, the dielectric recovery curves under conditions of different gas filling pressures and short-circuit current amplitudes are presented. A series of dielectric recovery measurements suggests that the dielectric recovery rate is proportional to the mass flux of the blowing gas, and the dielectric strength recovers faster in the case of lower short circuit currents.

Keywords: CO₂ mixture, high voltage circuit breakers, dielectric recovery rate, short-circuit current, mass flux

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Authors: Man Li, Wanting Zhou, Lei Li

Abstract:

Communication stability is the primary concern of communication satellites. Communication satellites are easily affected by particle radiation to generate single event effects (SEE), which leads to soft errors (SE) of the combinational logic circuit. The existing research on soft error rates (SER) of the combined logic circuit is mostly based on the assumption that the logic gates being bombarded have the same pulse width. However, in the actual radiation environment, the pulse widths of the logic gates being bombarded are different due to different linear energy transfers (LET). In order to improve the accuracy of SER evaluation model, this paper proposes a soft error rate evaluation method based on LET. In this paper, the authors analyze the influence of LET on the pulse width of combinational logic and establish the pulse width model based on the LET. Based on this model, the error rate of test circuit ISCAS'85 is calculated. The effectiveness of the model is proved by comparing it with previous experiments.

Keywords: communication satellite, pulse width, soft error rates, LET

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Authors: R. K. Saket, K. S. Anand Kumar

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This paper presents an innovative 3-wire capacitor circuit system used to increase the efficiency and comfort improvement of permanent split-capacitor ceiling fan. In this innovative circuit, current has been reduced to save electrical power. The system could be used to replace standard single phase motor 2-wire capacitor configuration by cost effective split value X rated of optimized AC capacitors with the auxiliary winding to provide reliable ceiling fan operation and improved machine performance to save power. In basic system operations, comparisons with conventional ceiling fan are described.

Keywords: permanent split-capacitor motor, innovative 3-wire capacitor circuit system, standard 2-wire capacitor circuit system, metalized film X-rated capacitor

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Authors: J. O. Akinyele, R. W. Salim, K. O. Oikelome, O. T. Olateju

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Rice Husk (RH) is the major byproduct in the processing of paddy rice. The management of this waste has become a big challenge to some of the rice producers, some of these wastes are left in open dumps while some are burn in the open space, and these two actions have been contributing to environmental pollution. This study evaluates an alternative waste management of this agricultural product for use as a civil engineering material. The RH was burn in a controlled environment to form Rice Husk Ash (RHA). The RHA was mix with lateritic clay at 0, 2, 4, 6, 8, and 10% proportion by weight. Chemical test was conducted on the open burn and controlled burn RHA with the lateritic clay. Physical test such as particle size distribution, Atterberg limits test, and density test were carried out on the mix material. The chemical composition obtained for the RHA showed that the total percentage compositions of Fe2O3, SiO2 and Al2O3 were found to be above 70% (class “F” pozzolan) which qualifies it as a very good pozzolan. The coefficient of uniformity (Cu) was 8 and coefficient of curvature (Cc) was 2 for the soil sample. The Plasticity Index (PI) for the 0, 2, 4, 6, 8. 10% was 21.0, 18.8, 16.7, 14.4, 12.4 and 10.7 respectively. The work concluded that RHA can be effectively used in hydraulic barriers and as a stabilizing agent in soil stabilization.

Keywords: rice husk ash, pozzolans, paddy rice, lateritic clay

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Authors: Cheng Zhang, James Marco, Walid Allafi, Truong Q. Dinh, W. D. Widanage

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Equivalent circuit models (ECMs) are widely used in battery management systems in electric vehicles and other battery energy storage systems. The battery dynamics and the model parameters vary under different working conditions, such as different temperature and state of charge (SOC) levels, and therefore online parameter identification can improve the modelling accuracy. This paper presents a way of online ECM parameter identification using a continuous time (CT) estimation method. The CT estimation method has several advantages over discrete time (DT) estimation methods for ECM parameter identification due to the widely separated battery dynamic modes and fast sampling. The presented method can be used for online SOC estimation. Test data are collected using a lithium ion cell, and the experimental results show that the presented CT method achieves better modelling accuracy compared with the conventional DT recursive least square method. The effectiveness of the presented method for online SOC estimation is also verified on test data.

Keywords: electric circuit model, continuous time domain estimation, linear integral filter method, parameter and SOC estimation, recursive least square

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