Search results for: high-k gate dielectrics
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 282

Search results for: high-k gate dielectrics

162 Dielectric Properties of Mineral Oil Blended with Soyabean Oil for Power Transformers: A Laboratory Investigation

Authors: Deepa S N, Srinivasan a D, Veeramanju K T

Abstract:

The power transformer is a critical equipment in the transmission and distribution network that must be managed to ensure uninterrupted power service. The liquid insulation is essential for the proper functioning of the transformer, as it serves as both coolant and insulating medium, which influences the transformer’s durability. Further, the insulating state of a power transformer has a significant impact on its reliability. Mineral oil derived from petroleum crude oil has been employed as liquid dielectrics for decades due to its superior functional characteristics, however as a resource for the same are getting depleted over the years. Research is undertaken across the globe to identify a viable substitute for mineral oil. Further, alternate insulating oils are being investigated for better environmental impact, biodegradability and economics. Several combinations of vegetable oil derived natural esters are being inspected by researchers across the globe in these domains. In this work, mineral oil is blended with soyabean oil with various proportions and dielectric properties such as dielectric breakdown voltage, relative permittivity, dissipation factor, viscosity, flash and fire point have been investigated according to international standards. A quantitative comparison is made among various samples and is observed that the blended oil sample of equal proportion of mineral oil and soyabean oil, MO50+SO50 exhibits superior dielectric properties such as breakdown voltage of 65kV, dissipation factor of 0.0044, relative permittivity of 3.1680 that are closer to the range of values recommended for power transformer applications. Also, Breakdown voltage values of all the investigated oil samples obeyed the Weibull and Normal probability distribution.

Keywords: blended oil, dielectric breakdown, liquid insulation, power transformer

Procedia PDF Downloads 58
161 Numerical Study of Two Mechanical Stirring Systems for Yield Stress Fluid

Authors: Amine Benmoussa, Mebrouk Rebhi, Rahmani Lakhdar

Abstract:

Mechanically agitated vessels are commonly used for various operations within a wide range process in chemical, pharmaceutical, polymer, biochemical, mineral, petroleum industries. Depending on the purpose of the operation carried out in mixer, the best choice for geometry of the tank and agitator type can vary widely. In this paper, the laminar 2D agitation flow and power consumption of viscoplastic fluids with straight and circular gate impellers in a stirring tank is studied by using computational fluid dynamics (CFD), where the velocity profile, the velocity fields and power consumption was analyzed.

Keywords: CFD, mechanical stirring, power consumption, yield stress fluid

Procedia PDF Downloads 316
160 Nanocomposites Based Micro/Nano Electro-Mechanical Systems for Energy Harvesters and Photodetectors

Authors: Radhamanohar Aepuru, R. V. Mangalaraja

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Flexible electronic devices have drawn potential interest and provide significant new insights to develop energy conversion and storage devices such as photodetectors and nanogenerators. Recently, self-powered electronic systems have captivated huge attention for next generation MEMS/NEMS devices that can operate independently by generating built-in field without any need of external bias voltage and have wide variety of applications in telecommunication, imaging, environmental and defence sectors. The basic physical process involved in these devices are charge generation, separation, and charge flow across the electrodes. Many inorganic nanostructures have been exploring to fabricate various optoelectronic and electromechanical devices. However, the interaction of nanostructures and their excited charge carrier dynamics, photoinduced charge separation, and fast carrier mobility are yet to be studied. The proposed research is to address one such area and to realize the self-powered electronic devices. In the present work, nanocomposites of inorganic nanostructures based on ZnO, metal halide perovskites; and polyvinylidene fluoride (PVDF) based nanocomposites are realized for photodetectors and nanogenerators. The characterization of the inorganic nanostructures is carried out through steady state optical absorption and luminescence spectroscopies as well as X-ray diffraction and high-resolution transmission electron microscopy (TEM) studies. The detailed carrier dynamics is investigated using various spectroscopic techniques. The developed composite nanostructures exhibit significant optical and electrical properties, which have wide potential applications in various MEMS/NEMS devices such as photodetectors and nanogenerators.

Keywords: dielectrics, nanocomposites, nanogenerators, photodetectors

Procedia PDF Downloads 95
159 Characteristics of Silicon Integrated Vertical Carbon Nanotube Field-Effect Transistors

Authors: Jingqi Li

Abstract:

A new vertical carbon nanotube field effect transistor (CNTFET) has been developed. The source, drain and gate are vertically stacked in this structure. The carbon nanotubes are put on the side wall of the vertical stack. Unique transfer characteristics which depend on both silicon type and the sign of drain voltage have been observed in silicon integrated CNTFETs. The significant advantage of this CNTFET is that the short channel of the transistor can be fabricated without using complicate lithography technique.

Keywords: carbon nanotubes, field-effect transistors, electrical property, short channel fabrication

Procedia PDF Downloads 325
158 Ferrites of the MeFe2O4 System (Me – Zn, Cu, Cd) and Their Two Faces

Authors: B. S. Boyanov, A. B. Peltekov, K. I. Ivanov

Abstract:

The ferrites of Zn, Cd, Cu, and mixed ferrites with NiO, MnO, MgO, CoO, ZnO, BaO combine the properties of dielectrics, semiconductors, ferro-magnets, catalysts, etc. The ferrites are used in an impressive range of applications due to their remarkable properties. A specific disadvantage of ferrites is that they are undesirably obtained in a lot of processes connected with metal production. They are very stable and poorly soluble compounds. The obtained ZnFe2O4 in zinc production connecting about 15% of the total zinc remains practically insoluble in dilute solutions of sulfuric acid. This decreases the degree of recovery of zinc and necessitates to further process the zinc-containing cake. In this context, the ferrites; ZnFe2O4, CdFe2O4, and CuFe2O4 are synthesized in laboratory conditions using ceramic technology. Their homogeneity and structure are proven by X-Ray diffraction analysis and Mössbauer spectroscopy. The synthesized ferrites are subjected to strong acid and high temperature leaching with solutions of H2SO4, HCl, and HNO3 (7, 10 and 15 %). The results indicate that the highest degree of leaching of Zn, Cd, and Cu from the ferrites is achieved by use of HCl. The resulting values for the degree of leaching of metals using H2SO4 are lower, but still remain significantly higher for all of the experimental conditions compared to the values obtained using HNO3. Five zinc sulfide concentrates are characterized for iron content by chemical analysis, Web-based Information System, and iron phases by Mössbauer spectroscopy. The charging was optimized using the criterion of minimal amount of zinc ferrite produced when roasting the concentrates in a fluidized bed. The results obtained are interpreted in terms of the hydrometallurgical zinc production and maximum recovery of zinc, copper and cadmium from initial zinc sulfide concentrates after their roasting.

Keywords: hydrometallurgy, inorganic acids, solubility, zinc ferrite

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157 Implementation of Iterative Algorithm for Earthquake Location

Authors: Hussain K. Chaiel

Abstract:

The development in the field of the digital signal processing (DSP) and the microelectronics technology reduces the complexity of the iterative algorithms that need large number of arithmetic operations. Virtex-Field Programmable Gate Arrays (FPGAs) are programmable silicon foundations which offer an important solution for addressing the needs of high performance DSP designer. In this work, Virtex-7 FPGA technology is used to implement an iterative algorithm to estimate the earthquake location. Simulation results show that an implementation based on block RAMB36E1 and DSP48E1 slices of Virtex-7 type reduces the number of cycles of the clock frequency. This enables the algorithm to be used for earthquake prediction.

Keywords: DSP, earthquake, FPGA, iterative algorithm

Procedia PDF Downloads 357
156 Thermal Effect in Power Electrical for HEMTs Devices with InAlN/GaN

Authors: Zakarya Kourdi, Mohammed Khaouani, Benyounes Bouazza, Ahlam Guen-Bouazza, Amine Boursali

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In this paper, we have evaluated the thermal effect for high electron mobility transistors (HEMTs) heterostructure InAlN/GaN with a gate length 30nm high-performance. It also shows the analysis and simulated these devices, and how can be used in different application. The simulator Tcad-Silvaco software has used for predictive results good for the DC, AC and RF characteristic, Devices offered max drain current 0.67A; transconductance is 720 mS/mm the unilateral power gain of 180 dB. A cutoff frequency of 385 GHz, and max frequency 810 GHz These results confirm the feasibility of using HEMTs with InAlN/GaN in high power amplifiers, as well as thermal places.

Keywords: HEMT, Thermal Effect, Silvaco, InAlN/GaN

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155 Design and Implementation of Wave-Pipelined Circuit Using Reconfigurable Technique

Authors: Adhinarayanan Venkatasubramanian

Abstract:

For design of high speed digital circuit wave pipeline is the best approach this can be operated at higher operating frequencies by adjusting clock periods and skews so as latch the o/p of combinational logic circuit at the stable period. In this paper, there are two methods are proposed in automation task one is BIST (Built in self test) and second method is Reconfigurable technique. For the above two approaches dedicated AND gate (multiplier) by applying wave pipeline technique. BIST approach is implemented by Xilinx Spartan-II device. In reconfigurable technique done by ASIC. From the results, wave pipeline circuits are faster than nonpipeline circuit and area, power dissipation are reduced by reconfigurable technique.

Keywords: SOC, wave-pipelining, FPGA, self-testing, reconfigurable, ASIC

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154 The Influence of Morphology and Interface Treatment on Organic 6,13-bis (triisopropylsilylethynyl)-Pentacene Field-Effect Transistors

Authors: Daniel Bülz, Franziska Lüttich, Sreetama Banerjee, Georgeta Salvan, Dietrich R. T. Zahn

Abstract:

For the development of electronics, organic semiconductors are of great interest due to their adjustable optical and electrical properties. Especially for spintronic applications they are interesting because of their weak spin scattering, which leads to longer spin life times compared to inorganic semiconductors. It was shown that some organic materials change their resistance if an external magnetic field is applied. Pentacene is one of the materials which exhibit the so called photoinduced magnetoresistance which results in a modulation of photocurrent when varying the external magnetic field. Also the soluble derivate of pentacene, the 6,13-bis (triisopropylsilylethynyl)-pentacene (TIPS-pentacene) exhibits the same negative magnetoresistance. Aiming for simpler fabrication processes, in this work, we compare TIPS-pentacene organic field effect transistors (OFETs) made from solution with those fabricated by thermal evaporation. Because of the different processing, the TIPS-pentacene thin films exhibit different morphologies in terms of crystal size and homogeneity of the substrate coverage. On the other hand, the interface treatment is known to have a high influence on the threshold voltage, eliminating trap states of silicon oxide at the gate electrode and thereby changing the electrical switching response of the transistors. Therefore, we investigate the influence of interface treatment using octadecyltrichlorosilane (OTS) or using a simple cleaning procedure with acetone, ethanol, and deionized water. The transistors consist of a prestructured OFET substrates including gate, source, and drain electrodes, on top of which TIPS-pentacene dissolved in a mixture of tetralin and toluene is deposited by drop-, spray-, and spin-coating. Thereafter we keep the sample for one hour at a temperature of 60 °C. For the transistor fabrication by thermal evaporation the prestructured OFET substrates are also kept at a temperature of 60 °C during deposition with a rate of 0.3 nm/min and at a pressure below 10-6 mbar. The OFETs are characterized by means of optical microscopy in order to determine the overall quality of the sample, i.e. crystal size and coverage of the channel region. The output and transfer characteristics are measured in the dark and under illumination provided by a white light LED in the spectral range from 450 nm to 650 nm with a power density of (8±2) mW/cm2.

Keywords: organic field effect transistors, solution processed, surface treatment, TIPS-pentacene

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153 Understand and Redefine Lean Product Development

Authors: Alemu Moges Belay, Torgeir Welo, Jan Ola Strandhagen

Abstract:

Lean has long been linked with manufacturing, but its application claimed also by other functions such as product development and services. However, there is a challenge on understanding and defining lean in each function context. This paper aims to investigate the literature that focus mainly on PD process improvement, obtain better understanding and redefine LPD in systematic way. In addition to that, the paper attempts to summarize various proposed transformation strategies, definitions, identifying features of manufacturing and product development that would help to redefining lean in product development context. Finally we redefine LPD in organized way that encompasses different steps such as stage gate, communication and information, events, learning, innovation, knowledge and value creation.

Keywords: lean, lean manufacturing, lean product development, transformation, strategies

Procedia PDF Downloads 448
152 Simulation of High Performance Nanoscale Partially Depleted SOI n-MOSFET Transistors

Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, kink effect

Procedia PDF Downloads 229
151 PSRR Enhanced LDO Regulator Using Noise Sensing Circuit

Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

Abstract:

In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor

Procedia PDF Downloads 254
150 Three Phase PWM Inverter for Low Rating Energy Efficient Systems

Authors: Nelson Lujara

Abstract:

The paper presents a practical three-phase PWM inverter suitable for low voltage, low rating energy efficient systems. The work in the paper is conducted with the view to establishing the significance of the loss contribution from the PWM inverter in the determination of the complete losses of a photovoltaic (PV) array-powered induction motor drive water pumping system. Losses investigated include; conduction and switching loss of the devices and gate drive losses. It is found that the PWM inverter operates at a reasonable variable efficiency that does not fall below 92% depending on the load. The results between the simulated and experimental results for the system with or without a maximum power tracker (MPT) compares very well, within an acceptable range of 2% margin.

Keywords: energy, inverter, losses, photovoltaic

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149 Effects of Vertimax Training on Agility, Quickness and Acceleration

Authors: Dede Basturk, Metin Kaya, Halil Taskin, Nurtekin Erkmen

Abstract:

In total, 29 students studying in Selçuk University Physical Training and Sports School who are recreationally active participated voluntarilyin this study which was carried out in order to examine effects of Vertimax trainings on agility, quickness and acceleration. 3 groups took their parts in this study as Vertimax training group (N=10), Ordinary training group (N=10) and Control group (N=9). Measurements were carried out in performance laboratory of Selçuk University Physical Training and Sports School. A training program for quickness and agility was followed up for subjects 3 days a week (Monday, Wednesday, Friday) for 8 weeks. Subjects taking their parts in vertimax training group and ordinary training group participated in the training program for quickness and agility. Measurements were applied as pre-test and post-test. Subjects of vertimax training group followed the training program with vertimax device and subjects of ordinary training group followed the training program without vertimax device. As to control group who are recreationally active, they did not participate in any program. 4 gate photocells were used for measuring and measurement of distances was carried out in m. Furthermore, single gate photocell and honi were used for agility test. Measurements started with 15 minutes of warm-up. Acceleration, quickness and agility tests were applied on subjects. 3 measurements were made for each subject at 3 minutes resting intervals. The best rating of three measurements was recorded. 5 m quickness pre-test value of vertimax training groups has been determined as 1,11±0,06 s and post-test value has been determined as 1,06 ± 0,08 s (P<0,05). 5 m quickness pre-test value of ordinary training group has been determined as 1,11±0,06 s and post-test value has been determined as 1,07±0,07 s (P<0,05).5 m quickness pre-test value of control group has been determined as 1,13±0,08 s and post-test value has been determined as 1,10 ± 0,07 s (P>0,05). Upon examination of 10 m acceleration value before and after the training, 10 m acceleration pre-test value of vertimax training group has been determined as 1,82 ± 0,07 s and post-test value has been determined as 1,76±0,83 s (P>0,05). 10 m acceleration pre-test value of ordinary training group has been determined as 1,83±0,05 s and post-test value has been determined as 1,78 ± 0,08 s (P>0,05).10 m acceleration pre-test value of control group has been determined as 1,87±0,11 s and post-test value has been determined as 1,83 ± 0,09 s (P>0,05). Upon examination of 15 m acceleration value before and after the training, 15 m acceleration pre-test value of vertimax training group has been determined as 2,52±0,10 s and post-test value has been determined as 2,46 ± 0,11 s (P>0,05).15 m acceleration pre-test value of ordinary training group has been determined as 2,52±0,05 s and post-test value has been determined as 2,48 ± 0,06 s (P>0,05). 15 m acceleration pre-test value of control group has been determined as 2,55 ± 0,11 s and post-test value has been determined as 2,54 ± 0,08 s (P>0,05).Upon examination of agility performance before and after the training, agility pre-test value of vertimax training group has been determined as 9,50±0,47 s and post-test value has been determined as 9,66 ± 0,47 s (P>0,05). Agility pre-test value of ordinary training group has been determined as 9,99 ± 0,05 s and post-test value has been determined as 9,86 ± 0,40 s (P>0,05). Agility pre-test value of control group has been determined as 9,74 ± 0,45 s and post-test value has been determined as 9,92 ± 0,49 s (P>0,05). Consequently, it has been observed that quickness and acceleration features were developed significantly following 8 weeks of vertimax training program and agility features were not developed significantly. It is suggested that training practices used for the study may be used for situations which may require sudden moves and in order to attain the maximum speed in a short time. Nevertheless, it is also suggested that this training practice does not make contribution in development of moves which may require sudden direction changes. It is suggested that productiveness and innovation may come off in terms of training by using various practices of vertimax trainings.

Keywords: vertimax, training, quickness, agility, acceleration

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148 Case Study of Mechanised Shea Butter Production in South-Western Nigeria Using the LCA Approach from Gate-to-Gate

Authors: Temitayo Abayomi Ewemoje, Oluwamayowa Oluwafemi Oluwaniyi

Abstract:

Agriculture and food processing, industry are among the largest industrial sectors that uses large amount of energy. Thus, a larger amount of gases from their fuel combustion technologies is being released into the environment. The choice of input energy supply not only directly having affects the environment, but also poses a threat to human health. The study was therefore designed to assess each unit production processes in order to identify hotspots using life cycle assessments (LCA) approach in South-western Nigeria. Data such as machine power rating, operation duration, inputs and outputs of shea butter materials for unit processes obtained at site were used to modelled Life Cycle Impact Analysis on GaBi6 (Holistic Balancing) software. Four scenarios were drawn for the impact assessments. Material sourcing from Kaiama, Scenarios 1, 3 and Minna Scenarios 2, 4 but different heat supply sources (Liquefied Petroleum Gas ‘LPG’ Scenarios 1, 2 and 10.8 kW Diesel Heater, scenarios 3, 4). Modelling of shea butter production on GaBi6 was for 1kg functional unit of shea butter produced and the Tool for the Reduction and Assessment of Chemical and other Environmental Impacts (TRACI) midpoint assessment was tool used to was analyse the life cycle inventories of the four scenarios. Eight categories in all four Scenarios were observed out of which three impact categories; Global Warming Potential (GWP) (0.613, 0.751, 0.661, 0.799) kg CO2¬-Equiv., Acidification Potential (AP) (0.112, 0.132, 0.129, 0.149) kg H+ moles-Equiv., and Smog (0.044, 0.059, 0.049, 0.063) kg O3-Equiv., categories had the greater impacts on the environment in Scenarios 1-4 respectively. Impacts from transportation activities was also seen to contribute more to these environmental impact categories due to large volume of petrol combusted leading to releases of gases such as CO2, CH4, N2O, SO2, and NOx into the environment during the transportation of raw shea kernel purchased. The ratio of transportation distance from Minna and Kaiama to production site was approximately 3.5. Shea butter unit processes with greater impacts in all categories was the packaging, milling and with the churning processes in ascending order of magnitude was identified as hotspots that may require attention. From the 1kg shea butter functional unit, it was inferred that locating production site at the shortest travelling distance to raw material sourcing and combustion of LPG for heating would reduce all the impact categories assessed on the environment.

Keywords: GaBi6, Life cycle assessment, shea butter production, TRACI

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147 Power MOSFET Models Including Quasi-Saturation Effect

Authors: Abdelghafour Galadi

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In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.

Keywords: power MOSFET, drift layer, quasi-saturation effect, SPICE model

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146 Effect of Inductance Ratio on Operating Frequencies of a Hybrid Resonant Inverter

Authors: Mojtaba Ghodsi, Hamidreza Ziaifar, Morteza Mohammadzaheri, Payam Soltani

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In this paper, the performance of a medium power (25 kW/25 kHz) hybrid inverter with a reactive transformer is investigated. To analyze the sensitivity of the inverster, the RSM technique is employed to manifest the effective factors in the inverter to minimize current passing through the Insulated Bipolar Gate Transistors (IGBTs) (current stress). It is revealed that the ratio of the axillary inductor to the effective inductance of resonant inverter (N), is the most effective parameter to minimize the current stress in this type of inverter. In practice, proper selection of N mitigates the current stress over IGBTs by five times. This reduction is very helpful to keep the IGBTs at normal temperatures.

Keywords: analytical analysis, hybrid resonant inverter, reactive transformer, response surface method

Procedia PDF Downloads 182
145 Failure Localization of Bipolar Integrated Circuits by Implementing Active Voltage Contrast

Authors: Yiqiang Ni, Xuanlong Chen, Enliang Li, Linting Zheng, Shizheng Yang

Abstract:

Bipolar ICs are playing an important role in military applications, mainly used in logic gates, such as inverter and NAND gate. The defect of metal break located on the step is one of the main failure mechanisms of bipolar ICs, resulting in open-circuit or functional failure. In this situation, general failure localization methods like optical beam-induced resistance change (OBIRCH) and photon emission microscopy (PEM) might not be fully effective. However, active voltage contrast (AVC) can be used as a voltage probe, which may pinpoint the incorrect potential and thus locate the failure position. Two case studies will be present in this paper on how to implement AVC for failure localization, and the detailed failure mechanism will be discussed.

Keywords: bipolar IC, failure localization, metal break, open failure, voltage contrast

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144 AC Voltage Regulators Using Single Phase Matrix Converter

Authors: Nagaraju Jarugu, B. R. Narendra

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This paper focused on boost rectification by Single Phase Matrix Converter with fewer numbers of switches. The conventional matrix converter consists of 4 bidirectional switches, i.e. 8 set of IGBT/MOSFET with anti-parallel diodes. In this proposed matrix converter, only six switches are used. The switch commutation arrangements are also carried out in this work. The SPMC topology has many advantages as a minimal passive device use. It is very flexible and it can be used as a lot of converters. The gate pulses to the switches are provided by the PWM techniques. The duty ratio of the switches based on Pulse Width Modulation (PWM) technique was used to produce the output waveform of the circuit, simply by turning ON and OFF the switches. The simulation results using MATLAB/Simulink were provided to validate the feasibility of this proposed method.

Keywords: single phase matrix converter, reduced switches, AC voltage regulators, boost rectifier operation

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143 Current of Drain for Various Values of Mobility in the Gaas Mesfet

Authors: S. Belhour, A. K. Ferouani, C. Azizi

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In recent years, a considerable effort (experience, numerical simulation, and theoretical prediction models) has characterised by high efficiency and low cost. Then an improved physics analytical model for simulating is proposed. The performance of GaAs MESFETs has been developed for use in device design for high frequency. This model is based on mathematical analysis, and a new approach for the standard model is proposed, this approach allowed to conceive applicable model for MESFET’s operating in the turn-one or pinch-off region and valid for the short-channel and the long channel MESFET’s in which the two dimensional potential distribution contributed by the depletion layer under the gate is obtained by conventional approximation. More ever, comparisons between the analytical models with different values of mobility are proposed, and a good agreement is obtained.

Keywords: analytical, gallium arsenide, MESFET, mobility, models

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142 Exploration of Various Metrics for Partitioning of Cellular Automata Units for Efficient Reconfiguration of Field Programmable Gate Arrays (FPGAs)

Authors: Peter Tabatt, Christian Siemers

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Using FPGA devices to improve the behavior of time-critical parts of embedded systems is a proven concept for years. With reconfigurable FPGA devices, the logical blocks can be partitioned and grouped into static and dynamic parts. The dynamic parts can be reloaded 'on demand' at runtime. This work uses cellular automata, which are constructed through compilation from (partially restricted) ANSI-C sources, to determine the suitability of various metrics for optimal partitioning. Significant metrics, in this case, are for example the area on the FPGA device for the partition, the pass count for loop constructs and communication characteristics to other partitions. With successful partitioning, it is possible to use smaller FPGA devices for the same requirements as with not reconfigurable FPGA devices or – vice versa – to use the same FPGAs for larger programs.

Keywords: reconfigurable FPGA, cellular automata, partitioning, metrics, parallel computing

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141 Extended Arithmetic Precision in Meshfree Calculations

Authors: Edward J. Kansa, Pavel Holoborodko

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Continuously differentiable radial basis functions (RBFs) are meshfree, converge faster as the dimensionality increases, and is theoretically spectrally convergent. When implemented on current single and double precision computers, such RBFs can suffer from ill-conditioning because the systems of equations needed to be solved to find the expansion coefficients are full. However, the Advanpix extended precision software package allows computer mathematics to resemble asymptotically ideal Platonic mathematics. Additionally, full systems with extended precision execute faster graphical processors units and field-programmable gate arrays because no branching is needed. Sparse equation systems are fast for iterative solvers in a very limited number of cases.

Keywords: partial differential equations, Meshfree radial basis functions, , no restrictions on spatial dimensions, Extended arithmetic precision.

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140 FPGA Implementation of Adaptive Clock Recovery for TDMoIP Systems

Authors: Semih Demir, Anil Celebi

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Circuit switched networks widely used until the end of the 20th century have been transformed into packages switched networks. Time Division Multiplexing over Internet Protocol (TDMoIP) is a system that enables Time Division Multiplexing (TDM) traffic to be carried over packet switched networks (PSN). In TDMoIP systems, devices that send TDM data to the PSN and receive it from the network must operate with the same clock frequency. In this study, it was aimed to implement clock synchronization process in Field Programmable Gate Array (FPGA) chips using time information attached to the packages received from PSN. The designed hardware is verified using the datasets obtained for the different carrier types and comparing the results with the software model. Field tests are also performed by using the real time TDMoIP system.

Keywords: clock recovery on TDMoIP, FPGA, MATLAB reference model, clock synchronization

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139 Multi Agent System Architecture Oriented Prometheus Methodology Design for Reverse Logistics

Authors: F. Lhafiane, A. Elbyed, M. Bouchoum

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The design of Reverse logistics Network has attracted growing attention with the stringent pressures from both environmental awareness and business sustainability. Reverse logistical activities include return, remanufacture, disassemble and dispose of products can be quite complex to manage. In addition, demand can be difficult to predict, and decision making is one of the challenges tasks. This complexity has amplified the need to develop an integrated architecture for product return as an enterprise system. The main purpose of this paper is to design Multi agent system (MAS) architecture using the Prometheus methodology to efficiently manage reverse logistics processes. The proposed MAS architecture includes five types of agents: Gate keeping Agent, Collection Agent, Sorting Agent, Processing Agent and Disposal Agent which act respectively during the five steps of reverse logistics Network.

Keywords: reverse logistics, multi agent system, prometheus methodology

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138 Reduction in the Metabolic Cost of Human Walking Gaits Using Quasi-Passive Upper Body Exoskeleton

Authors: Nafiseh Ebrahimi, Gautham Muthukumaran, Amir Jafari

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Human walking gait is considered to be the most efficient biped walking gait. There are various types of gait human follows during locomotion and arm swing is one of the most important factors which controls and differentiates human gaits. Earlier studies declared a 7% reduction in the metabolic cost due to the arm swing. In this research, we compared different types of arm swings in terms of metabolic cost reduction and then suggested, designed, fabricated and tested a quasi-passive upper body exoskeleton to study the metabolic cost reduction in the folded arm walking gate scenarios. Our experimental results validate a 10% reduction in the metabolic cost of walking aided by the application of the proposed exoskeleton.

Keywords: arm swing, MET (metabolic equivalent of a task), calorimeter, oxygen consumption, upper body quasi-passive exoskeleton

Procedia PDF Downloads 131
137 Numerical Solution Speedup of the Laplace Equation Using FPGA Hardware

Authors: Abbas Ebrahimi, Mohammad Zandsalimy

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The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results.

Keywords: accelerating numerical solutions, CFD, FPGA, hardware definition language, numerical solutions, reconfigurable hardware

Procedia PDF Downloads 358
136 Computational Analysis on Thermal Performance of Chip Package in Electro-Optical Device

Authors: Long Kim Vu

Abstract:

The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method.

Keywords: CFD, FPGA, heat transfer, thermal analysis

Procedia PDF Downloads 163
135 Design of Speedy, Scanty Adder for Lossy Application Using QCA

Authors: T. Angeline Priyanka, R. Ganesan

Abstract:

Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described.

Keywords: quantum cellular automata, carry look ahead adder, ripple carry adder, lossy application, majority gate, crossover

Procedia PDF Downloads 528
134 Transit Network Design Problem Issues and Challenges

Authors: Mahmoud Owais

Abstract:

Public Transit (P.T) is very important means to reduce traffic congestion, to improve urban environmental conditions and consequently affects people social lives. Planning, designing and management of P.T are the key issues for offering a competitive mode that can compete with the private transportation. These transportation planning, designing and management issues are addressed in the Transit Network Design Problem (TNDP). It deals with a complete hierarchy of decision making process. It includes strategic, tactical and operational decisions. The main body of TNDP is two stages, namely; route design stage and frequency setting. The TNDP is extensively studied in the last five decades; however the research gate is still widely open due to its many practical and modeling challenges. In this paper, a comprehensive background is given to illustrate the issues and challenges related to the TNDP to help in directing the incoming researches towards the untouched areas of the problem.

Keywords: frequency setting, network design, transit planning, urban planning

Procedia PDF Downloads 350
133 A New Full Adder Cell for High Performance Low Power Applications

Authors: Mahdiar Hosseighadiry, Farnaz Fotovatikhah, Razali Ismail, Mohsen Khaledian, Mehdi Saeidemanesh

Abstract:

In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles.

Keywords: full adders, low-power, high-performance, VLSI design

Procedia PDF Downloads 358