Search results for: buffer amplifier

Authors: Maryam Abata, Moulhime El Bekkali, Said Mazer, Catherine Algani, Mahmoud Mehdi

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One major problem of most electronic systems operating in the millimeter wave band is the signal generation with a high purity and a stable carrier frequency. This problem is overcome by using the combination of a signal with a low frequency local oscillator (LO) and several stages of frequency multipliers. The use of these frequency multipliers to create millimeter-wave signals is an attractive alternative to direct generation signal. Therefore, the isolation problem of the local oscillator from the other stages is always present, which leads to have various mechanisms that can disturb the oscillator performance, thus a buffer amplifier is often included in oscillator outputs. In this paper, we present the study and design of a buffer amplifier in the mm-wave band using a 0.15μm pHEMT from UMS foundry. This amplifier will be used as a part of a frequency quadrupler at 60 GHz.

Keywords: Mm-wave band, local oscillator, frequency quadrupler, buffer amplifier

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Authors: Karandeep Kaur

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This paper presents the design of power amplifier (PA) for mmWave communication systems. The designed amplifier uses GlobalFoundries 22 FDX technology and works at an operational frequency of 140 GHz in the D-Band. With a supply voltage of 0.8V for the super low threshold voltage transistors, the amplifier is biased in class AB and has a total current consumption of 50 mA. The measured saturated output power from the power amplifier is 5.6 dBm with an output-referred 1dB-compression point of 1.6dBm. The measured gain of PA is 19 dB with 3 dB-bandwidth ranging from 120 GHz to 140 GHz. The chip occupies an area of 795µm × 410µm.

Keywords: mmWave communication system, power amplifiers, 22FDX, D-Band, cross-coupled capacitive neutralization

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Authors: Jan Doutreloigne

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The main goal of this paper is to develop a switching amplifier with optimized power efficiency for analog signals with a very high crest factor such as audio or DSL signals. Theoretical calculations show that a switching amplifier architecture based on multi-level pulse width modulation outperforms all other types of linear or switching amplifiers in that respect. Simulations on a 2 W multi-level switching audio amplifier, designed in a 50 V 0.35 mm IC technology, confirm its superior performance in terms of power efficiency. A real silicon implementation of this audio amplifier design is currently underway to provide experimental validation.

Keywords: audio amplifier, multi-level switching amplifier, power efficiency, pulse width modulation, PWM, self-oscillating amplifier

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Authors: M. H. Al-Mansoori, W. S. Al-Ghaithi, F. N. Hasoon

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In this paper, we experimentally investigate the performance of an efficient high gain triple-pass L-band Erbium-Doped Fiber (EDF) amplifier structure with a single pump source. The amplifier gain and noise figure variation with EDF pump power, input signal power and wavelengths have been investigated. The generated backward Amplified Spontaneous Emission (ASE) noise of the first amplifier stage is suppressed by using a tunable band-pass filter. The amplifier achieves a signal gain of 55 dB with low noise figure of 3.8 dB at -50 dBm input signal power. The amplifier gain shows significant improvement of 12.8 dB compared to amplifier structure without ASE suppression.

Keywords: optical amplifiers, EDFA, L-band, optical networks

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Authors: Sina Mahdavi, Faeze Noruzpur, Aysuda Noruzpur

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This paper proposes a high linear, low power and wideband Variable Gain Amplifier (VGA) with a direct current (DC) gain range of -10.2dB to 60.7dB. By applying the proposed idea to the folded cascade amplifier, it is possible to achieve a 71dB DC gain, 35MHz (-3dB) bandwidth, accompanied by high linearity and low sensitivity as well. It is noteworthy that the proposed idea can be able to apply on every differential amplifier, too. Moreover, the total power consumption and unity gain bandwidth of the proposed VGA is 1.41mW with a power supply of 1.8 volts and 4.37GHz, respectively, and 0.8pF capacitor load is applied at the output nodes of the amplifier. Furthermore, the proposed structure is simulated in whole process corners and different temperatures in the region of -60 to +90 ºC. Simulations are performed for all corner conditions by HSPICE using the BSIM3 model of the 180nm CMOS technology and MATLAB software.

Keywords: variable gain amplifier, low power, low voltage, folded cascade, amplifier, DC gain

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Authors: Yo-Sheng Lin, Run-Chi Liu, Chien-Chu Ji, Chih-Chung Chen, Chien-Chin Wang

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A W-band double-balanced mixer for direct up-conversion using standard 90 nm CMOS technology is reported. The mixer comprises an enhanced double-balanced Gilbert cell with PMOS negative resistance compensation for conversion gain (CG) enhancement and current injection for power consumption reduction and linearity improvement, a Marchand balun for converting the single LO input signal to differential signal, another Marchand balun for converting the differential RF output signal to single signal, and an output buffer amplifier for loading effect suppression, power consumption reduction and CG enhancement. The mixer consumes low power of 6.9 mW and achieves LO-port input reflection coefficient of -17.8~ -38.7 dB and RF-port input reflection coefficient of -16.8~ -27.9 dB for frequencies of 90~100 GHz. The mixer achieves maximum CG of 3.6 dB at 95 GHz, and CG of 2.1±1.5 dB for frequencies of 91.9~99.4 GHz. That is, the corresponding 3 dB CG bandwidth is 7.5 GHz. In addition, the mixer achieves LO-RF isolation of 36.8 dB at 94 GHz. To the authors’ knowledge, the CG, LO-RF isolation and power dissipation results are the best data ever reported for a 94 GHz CMOS/BiCMOS up-conversion mixer.

Keywords: CMOS, W-band, up-conversion mixer, conversion gain, negative resistance compensation, output buffer amplifier

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Authors: Alpana Agarwal, Akhil Sharma

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This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter

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Authors: Divya Pradip Roy, Md. Zahirul Alam Chowdhury

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Electromyography (EMG) sensors are generally used to record the electrical activity produced by skeletal muscles. The conventional EMG sensors available in the market are expensive. This research suggests a low cost EMG sensor design which can be built with simple devices within our reach. In this research, one instrumentation amplifier, two high pass filters, two low pass filters and an inverting amplifier is connected sequentially. The output from the circuit exhibits electrical potential generated by the muscle cells when they are neurologically activated. This electromyography signal is used to control prosthetic devices, identifying neuromuscular diseases and for various other purposes.

Keywords: EMG, high pass filter, instrumentation amplifier, inverting amplifier, low pass filter, neuromuscular

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Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption whivh has a very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to symmetrical input stage. P-Spice simulation results using 0.18µm MIETEC CMOS process parameters using supply voltage of ±1.2V and 50μA biasing current. The P-Spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, open-loop gain-bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/µS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA

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Authors: Mr. P. Suryaprasad, R. Lalitha

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This paper presents an efficient area and delay architectures for the implementation of one dimensional and two dimensional discrete cosine transform (DCT). These are supported to different lengths (4, 8, 16, and 32). DCT blocks are used in the different video coding standards for the image compression. The 2D- DCT calculation is made using the 2D-DCT separability property, such that the whole architecture is divided into two 1D-DCT calculations by using a transpose buffer. Based on the existing 1D-DCT architecture two different types of 2D-DCT architectures, folded and parallel types are implemented. Both of these two structures use the same transpose buffer. Proposed transpose buffer occupies less area and high speed than existing transpose buffer. Hence the area, low power and delay of both the 2D-DCT architectures are reduced.

Keywords: transposition buffer, video compression, discrete cosine transform, high efficiency video coding, two dimensional picture

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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This paper proposes one stage and two stage CMOS Complementary Regulated Cascode Distributed Amplifier (CRCDA) design based on Inductive and Transformer coupling techniques. Usually, Distributed amplifier is based on inductor coupling between gate and gate of MOSFET and between drain and drain of MOSFET. But this paper propose some new idea, by coupling with differential primary windings of transformer between gate and gate of MOSFET first stage and second stage of regulated cascade amplifier and by coupling with differential secondary windings transformer of MOSFET between drain and drain of MOSFET first stage and second stage of regulated cascade amplifier. This paper also proposes polynomial modeling of Silicon Transformer passive equivalent circuit from Nanyang Technological University which is used to extract frequency response of transformer. Cadence simulation results are used to verify validity of transformer polynomial modeling which can be used to design distributed amplifier without Cadence. 4 parameters of scattering matrix of 2 port of the propose circuit is derived as a function of 4 parameters of impedance matrix.

Keywords: CMOS regulated cascode distributed amplifier, silicon transformer modeling with polynomial, low power consumption, distribute amplification technique

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Authors: Moez ul Hassan, Bushra Noman, Sarmad Hameed, Shahab Mehmood, Asma Bashir

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The importance of Noble prize winning “Patch Clamp Technique” is well documented. However, Patch Clamp Technique is very expensive and hence hinders research in developing countries. In this paper, detection, processing and recording of ultra low current from induced cells by using transimpedence amplifier is described. The sensitivity of the proposed amplifier is in the range of femto amperes (fA). Capacitive-feedback is used with active load to obtain a 20MΩ transimpedance gain. The challenging task in designing includes achieving adequate performance in gain, noise immunity and stability. The circuit designed by the authors was able to measure current in the rangeof 300fA to 100pA. Adequate performance shown by the amplifier with different input current and outcome result was found to be within the acceptable error range. Results were recorded using LabVIEW 8.5®for further research.

Keywords: drug discovery, ionic current, operational amplifier, patch clamp

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Authors: Abdalla Mohamed Eblabla

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Due to the high increase and demand for a wide assortment of applications that require low-cost, high-efficiency, and compact systems, RF power amplifiers are considered the most critical design blocks and power consuming components in wireless communication, TV transmission, radar, and RF heating. Therefore, much research has been carried out in order to improve the performance of power amplifiers. Classes-A, B, C, D, E, and F are the main techniques for realizing power amplifiers. An implementation of high efficiency class-F power amplifier with Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) was realized in this paper. The simulation and optimization of the class-F power amplifier circuit model was undertaken using Agilent’s Advanced Design system (ADS). The circuit was designed using lumped elements.

Keywords: Power Amplifier (PA), gallium nitride (GaN), Agilent’s Advanced Design System (ADS), lumped elements

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Authors: Zhixiang Li, Shuguang Yao, Wen Ma

Abstract:

Coupler rubber buffer has been widely applied on the high-speed trains and the main function of the rubber buffer is dissipating the impact energy between vehicles. The rubber buffer consists of two groups of rubbers, which are both pre-compressed and then installed into the frame body. This paper focuses on the energy absorption characteristics of the rubber buffers particularly. Firstly, the quasi-static compression tests were carried out for 1 and 3 pairs of rubber sheets and some energy absorption responses relationship, i.e. Eabn = n×Eab1, Edissn = n×Ediss1, and Ean = Ea1, were obtained. Next, a series of quasi-static tests were performed for 1 pair of rubber sheet to investigate the energy absorption performance with different compression ratio of the rubber buffers. Then the impact tests with five impact velocities were conducted and the coupler knuckle was destroyed when the impact velocity was 10.807 km/h. The impact tests results showed that with the increase of impact velocity, the Eab, Ediss and Ea of rear buffer increased a lot, but the three responses of front buffer had not much increase. Finally, the results of impact tests and quasi-static tests were contrastively analysed and the results showed that with the increase of the stroke, the values of Eab, Ediss, and Ea were all increase. However, the increasing rates of impact tests were all larger than that of quasi-static tests. The maximum value of Ea was 68.76% in impact tests, it was a relatively high value for vehicle coupler buffer. The energy capacity of the rear buffer was determined for dynamic loading, it was 22.98 kJ.

Keywords: rubber buffer, coupler, energy absorption, impact tests

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Authors: Ali M. Elgerbi, Obied A. Alwan, Al-Taher O. Alzwei, Abdurrahim A. Elouzi

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The binding of AFM1 to bacteria in phosphate buffer solution depended on many factors such as: availability of energy, incubation period, species and strain of bacteria. Increase in concentration of sugar showed higher removal of AFM1 and faster than in phosphate buffer alone. With 1.0% glucose lactic acid bacteria and bifidobacteria showed toxin removal ranging from 7.7 to 39.7% whereas with 10.0% glucose the percentage removal was 21.8 to 45.4% at 96 hours of incubation.

Keywords: aflatoxin M1, lactic acid bacteria, bifidobacteria , binding, phosphate buffer

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Authors: Sabry Shaaban, Tom McNamara, Sarah Hudson

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This article studies the performance of unpaced serial production lines that are subject to breakdown and are imbalanced in terms of both of their processing time means (MTs) and buffer storage capacities (BCs). Simulation results show that the best pattern in terms of throughput is a balanced line with respect to average buffer level; the best configuration is a monotone decreasing MT order, together with an ascending BC arrangement. Statistical analysis shows that BC, patterns of MT and BC imbalance, line length and degree of imbalance all contribute significantly to performance. Results show that unbalanced lines cope well with unreliability.

Keywords: unreliable unpaced serial lines, simulation, unequal mean operation times, uneven buffer capacities, patterns of imbalance, throughput, average buffer level

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Authors: Somya Ranjan Patro, Abhigna Bhatt, Arnab Banerjee

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Inertial amplifier has recently gained increasing attention as a new mechanism for vibration control of structures. Currently, theoretical investigations are undertaken by researchers to reveal its fundamentals and to understand its underline principles in altering the structural response of structures against dynamic loadings. This paper investigates experimental and analytical studies on the dynamic characteristics of hybrid beam inertial amplifier (HBIA). The analytical formulation of the HBIA has been derived by implementing the spectral element method and rigid body dynamics. This formulation gives the relation between dynamic force and the response of the structure in the frequency domain. Further, for validation of the proposed HBIA, the experiments have been performed. The experimental setup consists of a 3D printed HBIA of polylactic acid (PLA) material screwed at the base plate of the shaker system. Two numbers of accelerometers are used to study the response, one at the base plate of the shaker second one placed at the top of the inertial amplifier. A force transducer is also placed in between the base plate and the inertial amplifier to calculate the total amount of load transferred from the base plate to the inertial amplifier. The obtained time domain response from the accelerometers have been converted into the frequency domain using the Fast Fourier Transform (FFT) algorithm. The experimental transmittance values are successfully validated with the analytical results, providing us essential confidence in our proposed methodology.

Keywords: inertial amplifier, fast fourier transform, natural frequencies, polylactic acid, transmittance, vibration absorbers

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Authors: Maninder Kaur Gill, Alpana Agarwal

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It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values.

Keywords: Device Under Test (DUT), open loop voltage gain, operational amplifier, test circuit

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Authors: Udayan Patankar, Shashwati Bhagat, Vilas Nitneware, Ants Koel

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An ISM band power amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically used for driving the antenna of a transmitter. Due to drastic changes in telecommunication generations may lead to the requirements of improvements. Rapid changes in communication lead to the wide implementation of WLAN technology for its excellent characteristics, such as high transmission speed, long communication distance, and high reliability. Many applications such as WLAN, Bluetooth, and ZigBee, etc. were evolved with 2.4GHz to 5 GHz ISM Band, in which the power amplifier (PA) is a key building block of RF transmitters. There are many manufacturing processes available to manufacture a power amplifier for desired power output, but the major problem they have faced is about the power it consumed for its proper working, as many of them are fabricated on the GaN HEMT, Bi COMS process. In this paper we present a CMOS Base two stage cascode design of power amplifier working on 2.4GHz ISM frequency band. To lower the costs and allow full integration of a complete System-on-Chip (SoC) we have chosen 0.13µm low power CMOS technology for design. While designing a power amplifier, it is a real task to achieve higher power efficiency with minimum resources. This design showcase the Multi biased Cascode methodology to implement a two-stage CMOS power amplifier using ADS and LTSpice simulating tool. Main source is maximum of 2.4V which is internally distributed into different biasing point VB driving and VB driven as required for distinct stages of two stage RF power amplifier. It shows maximum power added efficiency near about 70.195% whereas its Power added efficiency calculated at 1 dB compression point is 44.669 %. Biased MOSFET is used to reduce total dc current as this circuit is designed for different wireless applications comes under 2.4GHz ISM Band.

Keywords: RFIC, PAE, RF CMOS, impedance matching

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Authors: Helen Sanders, Joshua Cousins

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The purpose of this study is to ascertain whether riparian buffer strips could be used to reduce Escherichia Coli (E. coli) runoff into streams in Central New York. Mainstream methods currently utilized to reduce E. coli runoff include fencing and staggered fertilizing plans for agriculture. These methods still do not significantly limit E. coli and thus, pose a serious health risk to individuals who swim in contaminated waters or consume contaminated produce. One additional method still in research development involves the planting of vegetated riparian buffers along waterways. Currently, riparian buffer strips are primarily used for filtration of nitrate and phosphate runoff to slow erosion, regulate pH and, improve biodiversity within waterways. For my research, four different stream sites were selected for the study, in which rainwater runoff was collected at both the riparian buffer and the E. coli sourced runoff upstream. Preliminary results indicate that there is an average 70% decrease in E. coli content in streams at the riparian buffer strips compared to upstream runoff. This research could be utilized to include vegetated buffer planting as a method to decrease manure runoff into essential waterways.

Keywords: Escherichia coli, riparian buffer strips, vegetated riparian buffers, runoff, filtration

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Authors: Tian-Wei Huang, Wei-Ting Bai, Yu-Tung Cheng, Jeng-Han Tsai

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In this paper, a 1-stage 6-section conventional distributed amplifier (CDA) structure distributed power amplifier (DPA) fabricated in a 28-nm HPC+ 1P9M CMOS process is proposed. The transistor size selection is introduced to achieve broadband power matching and thus remains a high flatness output power and power added efficiency (PAE) within the bandwidth. With the inductive peaking technique, the high-frequency pole appears and the high-frequency gain is increased; the gain flatness becomes better as well. The inductive elements used to form an artificial transmission line are built up with a floating ground coplanar waveguide plane (CPWFG) rather than a microstrip line, coplanar waveguide (CPW), or spiral inductor to get better performance. The DPA achieves 12.6 dB peak gain at 52.5 GHz with 2.9 to 64.9 GHz 3-dB bandwidth. The Psat is 11.4 dBm with PAEMAX of 10.6 % at 25 GHz. The output 1-dB compression point power is 9.8 dBm.

Keywords: distributed power amplifier (DPA), gain bandwidth (GBW), floating ground CPW, inductive peaking, 28-nm, CMOS, 5G.

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Authors: Guo-Ming Sung, Ramavath Naga Raju Naik

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This paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Mohiuddin Sakib, Fatin Nihal, Anisul Haque, Munsur Rahman, Mansur Ali

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Sundarban, the largest mangrove forest in the world, is known to act as a buffer against the cyclone and storm surge. Theoretically, Sundarban absorbs the initial thrust of the wind and acts to ‘resist’ the storm surge flooding. The role of Sundarban was evident during the cyclone Sidr when the Sundarban solely defended the initial thrust of the cyclonic wind and the resulting storm surge inundation. In doing this, Sundarban sacrificed 30% of its plant habitats. Although no scientific study has yet been conducted, it is generally believed that Sundarban will continuously play its role as a buffer against the cyclone when landfall of the cyclone is at or close to the Sundarban. Considering these facts, the present study mainly focused on a scientific insight into the role of Sundarban as a buffer against the present-day cyclone and storm surge and also its probable role on the impacts of future storms of similar nature but with different landfall locations. The Delft 3D dashboard and flow model are applied to compute the resulting inundation due to cyclone induced storm surge. The results show that Sundarban indeed acts as a buffer against the storm surge inundation when cyclone landfall is at or close to Sundarban.

Keywords: buffer, Mangrove forest, Sidr, landfall, roughness

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Authors: S. Shaaban, T. McNamara, S. Hudson

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This paper reports on the performance of deliberately unbalanced, reliable, non-automated and assembly lines that merge, whose workstations differ in terms of their mean operation times. Simulations are carried out on 5- and 8-station lines with 1, 2 and 4 buffer capacity units, % degrees of line imbalance of 2, 5 and 12, and 24 different patterns of means imbalance. Data on two performance measures, namely throughput and average buffer level were gathered, statistically analysed and compared to a merging balanced line counterpart. It was found that the best configurations are a balanced line arrangement and a monotone decreasing order for each of the parallel merging lines, with the first generally resulting in a lower throughput and the second leading to a lower average buffer level than those of a balanced line.

Keywords: average buffer level, merging lines, simulation, throughput, unbalanced

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Authors: Radia Kamel

Abstract:

Considerable progress has been made in the development of bulk-heterojunction organic solar cells (OSCs) based on a blend of p-type and n-type organic semiconductors. To optimize the interfacial properties between the active layer and the electrode, a cathode buffer layer (CBL) is introduced. This layer can reduce the leakage current, increasing the open-circuit voltage and the fill factor while improving the OSC stability. In this work, the performance of PM6:Y6 OSC with 1-Chloronaphthalene as an additive is examined. To accomplish this, three CBLs PNDIT-F3N-Br, ZrAcac, and PDINO, are compared using the conventional configuration. The device with PNDIT-F3N-Br as CBL exhibits the highest power conversion efficiency of 16.04%. The results demonstrate that modifying the cathode buffer layer is crucial for achieving high-performance OSCs.

Keywords: bulk heterojunction, cathode buffer layer, efficiency, organic solar cells

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Authors: Zhixiang Li, Shuguang Yao, Wen Ma

Abstract:

Coupler rubber buffer has been widely applied on the high-speed trains and the main function of the rubber buffer is dissipating the impact energy between vehicles. The rubber buffer consists of two groups of rubbers, which are both pre-compressed and then installed into the frame body. This work focuses on the energy absorption capacity of each group of buffers particularly. The quasi-static compression tests were carried out to obtain the pre-compression force and the load-defection response of the buffers. Then a finite element (FE) model was constructed using Ls_dyna program. The rubber material was modeled with a tabulated method easily, in which no more material constants need to be fitted. The simulation results agreed with the experimental results well. Numerical study of the buffers was performed using the validated FE model and the influence of the initial pressure on the buffers was obtained. In addition, the interaction between the two groups of buffers was also investigated and the optimum distribution of the two was found.

Keywords: initial pressure, rubber buffer, simulation, tabulated method

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

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This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

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Authors: Keshav Raj Acharya, Thakur Silwal, Neelam C. Poudyal

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Buffer zones, the peripheral areas around the national parks and wildlife reserves, are available for the purpose of benefitting the local inhabitants by providing forest products for subsistence needs of basic forest products outside the protected areas. The forest area within the buffer zone has been managed as a buffer zone community forest (BZCF) for the last 25 years after the approval of the buffer zone management regulation 1996. With a case study of select BZCF in Bardia National Park, this study aims to analyze whether the benefit provided by BZCF is equally available to poor users among other socioeconomic classes of the users. The findings are based on the analysis of cross-sectional data involving household surveys (n=305) and key informants’ interviews (n=10) as well as office records available at different 5 buffer zone community forest user groups offices. Results indicate that despite the provisions of subsidized rates for poor; poor households were more deprived due to higher forest products price particularly, the timber price in buffer zone. Evidence also indicate that due to the increased forest coverage, the incidence of wildlife damage has also increased and impacted the poor more due to lack of land ownership as well as limited alternatives. Clear community forest management guidelines with equitable benefit sharing and compensatory mechanisms to the users of poor socioeconomic class have been identified as a solution to increase the benefit to poor users in BZCFUGs.

Keywords: crop depredation, forest products, users, wellbeing ranking

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Authors: Joselito Medina-Marin, Alexandr Karelin, Ana Tarasenko, Juan Carlos Seck-Tuoh-Mora, Norberto Hernandez-Romero, Eva Selene Hernandez-Gress

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A production line designer faces with several challenges in manufacturing system design. One of them is the assignment of buffer slots in between every machine of the production line in order to maximize the throughput of the whole line, which is known as the Buffer Allocation Problem (BAP). The BAP is a combinatorial problem that depends on the number of machines and the total number of slots to be distributed on the production line. In this paper, we are proposing a Petri Net (PN) Model to obtain the throughput in unreliable production lines, based on PN mathematical tools and the decomposition method. The results obtained by this methodology are similar to those presented in previous works, and the number of machines is not a hard restriction.

Keywords: buffer allocation problem, Petri Nets, throughput, production lines

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Authors: Gunasekaran Raja, Ramkumar Jayaraman, Rajakumar Arul, Kottilingam Kottursamy

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Broadband Wireless Network (BWN) is the promising technology nowadays due to the increased number of smartphones. Buffering scheme using network coding considers the reliability and proper degree distribution in Worldwide interoperability for Microwave Access (WiMAX) multi-hop network. Using network coding, a secure way of transmission is performed which helps in improving throughput and reduces the packet loss in the multicast network. At the outset, improved network coding is proposed in multicast wireless mesh network. Considering the problem of performance overhead, degree distribution makes a decision while performing buffer in the encoding / decoding process. Consequently, BuS (Buffer Scheme) based on network coding is proposed in the multi-hop network. Here the encoding process introduces buffer for temporary storage to transmit packets with proper degree distribution. The simulation results depend on the number of packets received in the encoding/decoding with proper degree distribution using buffering scheme.

Keywords: encoding and decoding, buffer, network coding, degree distribution, broadband wireless networks, multicast

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