Search results for: HEMT transistor

Authors: A.N. Moulay Khatir, A. Guen-Bouazza, B. Bouazza

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SOI-Multifin-FET shows excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency. In this work, we analyzed this combination by a three-dimensional numerical device simulator to investigate the influence of fins number on corner effect by analyzing its electrical characteristics and potential distribution in the oxide and the silicon in the section perpendicular to the flow of the current for SOI-single-fin FET, three-fin and five-fin, and we provide a comparison with a Trigate SOI Multi-FinFET structure.

Keywords: SOI, FinFET, corner effect, dual-gate, tri-gate, Multi-Fin FET

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Authors: Azizi Cherifa, O. Benzaoui

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The thermal aspects in the design of power circuits often deserve as much attention as pure electric components aspects as the operating temperature has a direct influence on their static and dynamic characteristics. MOSFET is fundamental in the circuits, it is the most widely used device in the current production of semiconductor components using their honorable performance. The aim of this contribution is devoted to the effect of the temperature on the properties of MOSFETs. The study enables us to calculate the drain current as function of bias in both linear and saturated modes. The effect of temperature is evaluated using a numerical simulation, using the laws of mobility and saturation velocity of carriers as a function of temperature.

Keywords: temperature, MOSFET, mobility, transistor

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Authors: Samaniego Campoverde José Enrique, Rosero Muñoz Jorge Enrique, Luzcando Narea Lorena Elizabeth

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This paper presents a practical and theoretical model for the operation of the Tesla coil using digital signal processing. The research is based on the analysis of ten scientific papers exploring the development and operation of the Tesla coil. Starting from the Testa coil, several modifications were carried out on the Tesla coil, with the aim of amplifying the digital signal by making use of digital signal processing. To achieve this, an amplifier with a transistor and digital filters provided by MATLAB software were used, which were chosen according to the characteristics of the signals in question.

Keywords: tesla coil, digital signal process, equalizer, graphical environment

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Authors: Mourad Hrizi

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In this paper, we study the inverse problem of reconstructing an interior interface D appearing in the elliptic partial differential equation: Δu+χ(D)u=0 from the knowledge of the boundary measurements. This problem arises from a semiconductor transistor model. We propose a new shape reconstruction procedure that is based on the Kohn-Vogelius formulation and the topological sensitivity method. The inverse problem is formulated as a topology optimization one. A topological sensitivity analysis is derived from a function. The unknown subdomain D is reconstructed using a level-set curve of the topological gradient. Finally, we give several examples to show the viability of our proposed method.

Keywords: inverse problem, topological optimization, topological gradient, Kohn-Vogelius formulation

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Authors: Mehdi Saeidmanesh, Razali Ismail

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Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: graphene nanoribbon, field effect transistors, short channel effects, channel length modulation

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Authors: N. Massoum, B. Bouazza

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In this paper, we have developed a numerical simulation model to describe the electrical properties of GaInP MESFET with submicron gate (Lg = 0.5 µm). This model takes into account the three-dimensional (3D) distribution of the load in the short channel and the law effect of mobility as a function of electric field. Simulation software based on a stochastic method such as Monte Carlo has been established. The results are discussed and compared with those of the experiment. The result suggests experimentally that, in a very small gate length in our devices (smaller than 40 nm), short-channel tunneling explains the degradation of transistor performance, which was previously enhanced by velocity overshoot.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, simulation software

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Authors: Jiajia Yao, Guanlin Wu, Fang Liu, Junshuai Xue, Yue Hao

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As the production process of self-standing GaN substrates evolves, the commercialization of low dislocation density, large-scale, semi-insulating self-standing GaN substrates is gradually becoming a reality. This advancement has given rise to increased interest in GaN materials' homoepitaxial technology. However, at the homoepitaxial interface, there are considerable concentrations of impurity elements, including C, Si, and O, which generate parasitic leakage channels at the re-growth junction. This phenomenon results in leaked HEMTs that prove difficult to switch off, rendering them effectively non-functional. The emergence of leakage channels can also degrade the high-frequency properties and lower the power devices' breakdown voltage. In this study, the uniform epitaxy of AlGaN/GaN heterojunction with high electron mobility was accomplished through the surface treatment of the GaN substrates prior to growth and the design of the AlN isolation layer structure. By employing a procedure combining gallium atom in-situ cleaning and plasma nitridation, the C and O impurity concentrations at the homoepitaxial interface were diminished to the scale of 10¹⁷ cm-³. Additionally, the 1.5 nm nitrogen-rich AlN isolation layer successfully prevented the diffusion of Si impurities into the GaN channel layer. The result was an AlGaN/GaN heterojunction with an electron mobility of 1552 cm²/Vs and an electron density of 1.1 × 10¹³ cm-² at room temperature, obtained on a Fe-doped semi-insulating GaN substrate.

Keywords: MBE, AlGaN/GaN, homogenerous epitaxy, HEMT

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Authors: A. N. Moulai Khatir

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SOI-Multifin-FETs are placed to be the workhorse of the industry for the coming few generations, and thus, in a few years because their excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation, and negligible body bias dependency. The corner effect may also exist in the two lower corners; this effect is called the BOX effect, which can also occur in the direction X-Z. The electric field lines from the source and drain cross the bottom oxide and arrive in the silicon. This effect is also called DIVSB (Drain Induced Virtual Substrate Basing). The potential in the silicon film in particular near the drain is increased by the drain bias. It is similar to DIBL and result in a decrease of the threshold voltage. This work provides an understanding of the limitation of this effect by reducing the fin width for components with increased fin number.

Keywords: SOI, finFET, corner effect, dual-gate, tri-gate, BOX, multi-finFET

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Authors: Mohsen Khaledian, Razali Ismail, Mehdi Saeidmanesh, Mahdiar Hosseinghadiry

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A semi-analytical model for impact ionization coefficient of graphene nanoribbon (GNR) is presented. The model is derived by calculating probability of electrons reaching ionization threshold energy Et and the distance traveled by electron gaining Et. In addition, ionization threshold energy is semi-analytically modeled for GNR. We justify our assumptions using analytic modeling and comparison with simulation results. Gaussian simulator together with analytical modeling is used in order to calculate ionization threshold energy and Kinetic Monte Carlo is employed to calculate ionization coefficient and verify the analytical results. Finally, the profile of ionization is presented using the proposed models and simulation and the results are compared with that of silicon.

Keywords: nanostructures, electronic transport, semiconductor modeling, systems engineering

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

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In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET

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Authors: Kiran Jose, Anjana J. G., Venu Anand, Aswathi R. Nair

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This work investigates the change in structural, optical, and electrical properties of Zinc Oxynitride (ZnON) thin film when annealed in different atmospheres. ZnON film is prepared by reactively sputtering the Zinc target using argon, oxygen, and nitrogen. The deposited film is annealed for one hour at 3250C in the Vaccum condition and Nitrogen and oxygen atmospheres. XRD and Raman spectroscopy is used to study the structural properties of samples. The current conduction mechanism is examined by extracting voltage versus current characteristics on a logarithmic scale, and the optical response is quantified by analyzing persistent photoconductivity (PPC) behavior. This study proposes the optimum annealing atmosphere for ZnON thin film for a better transistor and photosensor application.

Keywords: Zinc oxynitride, thin film, annealing, DC sputtering

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Authors: Yu-Hsien Lin, Yu-Ru Lin, Yung-Chun Wu

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This work demonstrates the ultra-thin poly-Si (polycrystalline Silicon) nanowire junctionless thin film transistors (NWs JL-TFT) with nickel silicide contact. For nickel silicide film, this work designs to use two-step annealing to form ultra-thin, uniform and low sheet resistance (Rs) Ni silicide film. The NWs JL-TFT with nickel silicide contact exhibits the good electrical properties, including high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this work also compares the electrical characteristics of NWs JL-TFT with nickel silicide and non-silicide contact. Nickel silicide techniques are widely used for high-performance devices as the device scaling due to the source/drain sheet resistance issue. Therefore, the self-aligned silicide (salicide) technique is presented to reduce the series resistance of the device. Nickel silicide has several advantages including low-temperature process, low silicon consumption, no bridging failure property, smaller mechanical stress, and smaller contact resistance. The junctionless thin-film transistor (JL-TFT) is fabricated simply by heavily doping the channel and source/drain (S/D) regions simultaneously. Owing to the special doping profile, JL-TFT has some advantages such as lower thermal the budget which can integrate with high-k/metal-gate easier than conventional MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), longer effective channel length than conventional MOSFETs, and avoidance of complicated source/drain engineering. To solve JL-TFT has turn-off problem, JL-TFT needs ultra-thin body (UTB) structure to reach fully depleted channel region in off-state. On the other hand, the drive current (Iᴅ) is declined as transistor features are scaled. Therefore, this work demonstrates ultra thin poly-Si nanowire junctionless thin film transistors with nickel silicide contact. This work investigates the low-temperature formation of nickel silicide layer by physical-chemical deposition (PVD) of a 15nm Ni layer on the poly-Si substrate. Notably, this work designs to use two-step annealing to form ultrathin, uniform and low sheet resistance (Rs) Ni silicide film. The first step was promoted Ni diffusion through a thin interfacial amorphous layer. Then, the unreacted metal was lifted off after the first step. The second step was annealing for lower sheet resistance and firmly merged the phase.The ultra-thin poly-Si nanowire junctionless thin film transistors NWs JL-TFT with nickel silicide contact is demonstrated, which reveals high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In silicide film analysis, the second step of annealing was applied to form lower sheet resistance and firmly merge the phase silicide film. In short, the NWs JL-TFT with nickel silicide contact has exhibited a competitive short-channel behavior and improved drive current.

Keywords: poly-Si, nanowire, junctionless, thin-film transistors, nickel silicide

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Authors: T. Bielewicz, S. Dogan, C. Klinke

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Two-dimensional, solution-processable semiconductor materials are interesting for low-cost electronic applications [1]. We demonstrate the synthesis of lead sulfide nanosheets and how their size, shape and height can be tuned by varying concentrations of pre-cursors, ligands and by varying the reaction temperature. Especially, the charge carrier confinement in the nanosheets’ height adjustable from 2 to 20 nm has a decisive impact on their electronic properties. This is demonstrated by their use as conduction channel in a field effect transistor [2]. Recently we also showed that especially thin nanosheets show a high carrier multiplication (CM) efficiency [3] which could make them, through the confinement induced band gap and high photoconductivity, very attractive for application in photovoltaic devices. We are already able to manufacture photovoltaic devices out of single nanosheets which show promising results.

Keywords: physical sciences, chemistry, materials, chemistry, colloids, physics, condensed-matter physics, semiconductors, two-dimensional materials

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Authors: Sonia Vanessa Campos Moreira

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The aim of this research is the production and mechanical properties of Alkali-Activated Inorganic Binders (AAIB) made from The Basic Oxygen Furnace Slag (BOF Slag) and Thin Film Transistor Liquid Crystal Display (TFT-LCD), glass powder (waste and industrial by-products). Many factors have an influence on the production of AAIB like the glass powder finesses, the alkaline equivalent content (AE %), water binder ratios (w/b ratios) and the differences curing process. The findings show different behavior in the AAIB related to the factors mentioned, the best results are given with a glass powder fineness of 4,500 cm²/g, w/b=0.30, a curing temperature of 70 ℃, curing duration of 4 days and an aging duration of 14 days results in the highest compressive strength of 18.51 MPa.

Keywords: alkaline activators, BOF slag, glass powder fineness, TFT-LCD, w/b ratios

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

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The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, GaInP

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Authors: Kala Bharathan, R. Seshasayanan

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In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

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The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity, and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.

Keywords: LDMOS, amplifier, back-off, bias circuit

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Authors: Tian-Wei Huang, Wei-Ting Bai, Yu-Tung Cheng, Jeng-Han Tsai

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In this paper, a 1-stage 6-section conventional distributed amplifier (CDA) structure distributed power amplifier (DPA) fabricated in a 28-nm HPC+ 1P9M CMOS process is proposed. The transistor size selection is introduced to achieve broadband power matching and thus remains a high flatness output power and power added efficiency (PAE) within the bandwidth. With the inductive peaking technique, the high-frequency pole appears and the high-frequency gain is increased; the gain flatness becomes better as well. The inductive elements used to form an artificial transmission line are built up with a floating ground coplanar waveguide plane (CPWFG) rather than a microstrip line, coplanar waveguide (CPW), or spiral inductor to get better performance. The DPA achieves 12.6 dB peak gain at 52.5 GHz with 2.9 to 64.9 GHz 3-dB bandwidth. The Psat is 11.4 dBm with PAEMAX of 10.6 % at 25 GHz. The output 1-dB compression point power is 9.8 dBm.

Keywords: distributed power amplifier (DPA), gain bandwidth (GBW), floating ground CPW, inductive peaking, 28-nm, CMOS, 5G.

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Authors: Khaled A. Madi, Abdulalhakim O. Naji, Hassouna A. Aalaoh, Elmahdi Eldeeb

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Solar energy is one of the cleanest energy sources with no environmental impact. Due to rapid increase in industrial as well as domestic needs, solar energy becomes a good candidate for safe and easy to handle energy source, especially after it becomes available due to reduction of manufacturing price. The main part of the solar inverter system is the inverter where the DC is inverted to AC, where we try to minimize the loss of power to the minimum possible level by the use of microcontroller. In this work, a deep investigation is made experimentally as well as theoretically for a microcontroller based variable frequency power inverter. The microcontroller will provide the variable frequency Pulse Width Modulation (PWM) signal that will control the switching of the gate of the Insulating Gate Bipolar Transistor (IGBT) with less harmonics at the output of power inverter which can be fed to the public grid at high quality. The proposed work for single phase as well as three phases is also simulated using Matlab/Simulink where we found a good agreement between the simulated and the practical results, even though the experimental work were done in the laboratory of the academy.

Keywords: solar, inverter, PV, solar inverter system

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Authors: F. Z. Mahi, H. Marinchio, C. Palermo, L. Varani

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We propose an analytical approach for the admittance response calculation of the high mobility InGaAs channel transistors. The development of the small-signal admittance takes into account the longitudinal and transverse electric fields through a pseudo two-dimensional approximation of the Poisson equation. The total currents and the potentials matrix relation between the gate and the drain terminals determine the frequency-dependent small-signal admittance response. The analytical results show that the admittance spectrum exhibits a series of resonant peaks corresponding to the excitation of plasma waves. The appearance of the resonance is discussed and analyzed as functions of the channel length and the temperature. The model can be used, on one hand, to control the appearance of plasma resonances, and on the other hand, can give significant information about the admittance phase frequency dependence.

Keywords: small-signal admittance, Poisson equation, currents and potentials matrix, the drain and the gate terminals, analytical model

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Authors: Jiajia Yao, GuanLin Wu, Fang liu, JunShuai Xue, JinCheng Zhang, Yue Hao

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Due to its outstanding material properties like high thermal conductivity and ultra-wide bandgap, Aluminum nitride (AlN) has the promising potential to provide high breakdown voltage and high output power among III-nitrides for various applications in electronics and optoelectronics. This work presents material growth and characterization of strained channel Aluminum nitride/Gallium nitride (AlN/GaN) heterostructures grown by plasma-assisted molecular beam epitaxy (PA-MBE) on AlN-on-sapphire templates. To improve the crystal quality and manifest the ability of the PA-MBE approach, a thick AlN buffer with a thickness of 180 nm is first grown on AlN template, which acts as a back-barrier to enhance the breakdown characteristic and isolates the leakage path existing in the interface between AlN epilayer and AlN template, as well as improve the heat dissipation. The grown AlN buffer features a root-mean-square roughness of 0.2 nm over a scanned area of 2×2 µm2 measured by atomic force microscopy (AFM), and exhibits full-width at half-maximum of 95 and 407 arcsec for the (002) and (102) plane the X-ray rocking curve, respectively, tested by high resolution x-ray diffraction (HR-XRD). With a thin and strained GaN channel, the electron mobility of 294 cm2 /Vs. with a carrier concentration of 2.82×1013 cm-2 at room temperature is achieved in AlN/GaN double-channel heterostructures, and the depletion capacitance is as low as 14 pF resolved by the capacitance-voltage, which indicates the promising opportunities for future applications in next-generation high temperature, high-frequency and high-power electronics with a further increased electron mobility by optimization of heterointerface quality.

Keywords: AlN/GaN, HEMT, MBE, homoepitaxy

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

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The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: low-frequency noise, random telegraph noise, dynamic variation, SRRV

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Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

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Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: fast vs slow BTI, fast wafer level reliability (FWLR), negative bias temperature instability (NBTI), NBTI measurement system, metal-oxide-semiconductor field-effect transistor (MOSFET), NBTI recovery, reliability

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: floating active resistor, complementary common gate, complementary regulated cascode, current mirror

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Authors: Mantas Sakalas, Paulius Sakalas

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This paper presents an analysis and design of a ultrawideband 1.8GHz to 43GHz Low Noise Amplifier (LNA) in 0.1 μm Galium Arsenide (GaAs) pseudomorphic High Electron Mobility Transistor (pHEMT) technology. The feedback based bandwidth extension techniques is analyzed and based on the outcome, a two stage LNA is designed. The impedance fine tuning is implemented by using Transmission Line (TL) structures. The measured performance shows a good agreement with simulation results and an outstanding wideband noise matching. The measured small signal gain was 12 dB, whereas a 3 dB gain flatness in range from 1.8 - 43 GHz was reached. The noise figure was below 4 dB almost all over the entire frequency band of 1.8GHz to 43GHz, the output power at 1 dB compression point was 6 dBm and the DC power consumption was 95 mW. To the best knowledge of the authors the designed LNA outperforms the State of the Art (SotA) reported LNA designs in terms of combined parameters of noise figure within the addressed ultra-wide 3 dB bandwidth, linearity and DC power consumption.

Keywords: feedback amplifiers, GaAs pHEMT, monolithic microwave integrated circuit, LNA, noise matching

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Authors: Nikhil Jain, Bin Yu

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We explore the potential of using ultra-thin hexagonal boron nitride (h-BN) as both supporting substrate and gate dielectric for graphene-channel field effect transistors (GFETs). Different from commonly used oxide-based dielectric materials which are typically amorphous, very rough in surface, and rich with surface traps, h-BN is layered insulator free of dangling bonds and surface states, featuring atomically smooth surface. In a graphene-channel-last device structure with local buried metal gate electrode (TiN), thin h-BN multilayer is employed as both supporting “substrate” and gate dielectric for graphene active channel. We observed superior carrier mobility and electrical conduction, significantly improved from that in GFETs with SiO2 as substrate/gate insulator. In addition, we report excellent dielectric behavior of layered h-BN, including ultra-low leakage current and high critical electric field for breakdown.

Keywords: graphene, field-effect transistors, hexagonal boron nitride, dielectric strength, tunneling

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Authors: Udayan Patankar, Shashwati Bhagat, Vilas Nitneware, Ants Koel

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An ISM band power amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically used for driving the antenna of a transmitter. Due to drastic changes in telecommunication generations may lead to the requirements of improvements. Rapid changes in communication lead to the wide implementation of WLAN technology for its excellent characteristics, such as high transmission speed, long communication distance, and high reliability. Many applications such as WLAN, Bluetooth, and ZigBee, etc. were evolved with 2.4GHz to 5 GHz ISM Band, in which the power amplifier (PA) is a key building block of RF transmitters. There are many manufacturing processes available to manufacture a power amplifier for desired power output, but the major problem they have faced is about the power it consumed for its proper working, as many of them are fabricated on the GaN HEMT, Bi COMS process. In this paper we present a CMOS Base two stage cascode design of power amplifier working on 2.4GHz ISM frequency band. To lower the costs and allow full integration of a complete System-on-Chip (SoC) we have chosen 0.13µm low power CMOS technology for design. While designing a power amplifier, it is a real task to achieve higher power efficiency with minimum resources. This design showcase the Multi biased Cascode methodology to implement a two-stage CMOS power amplifier using ADS and LTSpice simulating tool. Main source is maximum of 2.4V which is internally distributed into different biasing point VB driving and VB driven as required for distinct stages of two stage RF power amplifier. It shows maximum power added efficiency near about 70.195% whereas its Power added efficiency calculated at 1 dB compression point is 44.669 %. Biased MOSFET is used to reduce total dc current as this circuit is designed for different wireless applications comes under 2.4GHz ISM Band.

Keywords: RFIC, PAE, RF CMOS, impedance matching

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Authors: V. S. Klimash, Ye Min Thu

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Thyristor rectifiers, inverters grid-tied, and AC voltage regulators are widely used in industry, and on electrified transport, they have a lot in common both in the power circuit and in the control system. They have a common mathematical structure and switching processes. At the same time, the rectifier, but the inverter units and thyristor regulators of alternating voltage are considered separately both theoretically and practically. They are written about in different books as completely different devices. The aim of this work is to combine them into one class based on the unity of the equations describing electromagnetic processes, and then, to show this unity on the mathematical model and experimental setup. Based on research from mathematics to the product, a conclusion is made about the methodology for the rapid conduct of research and experimental design work, preparation for production and serial production of converters with a unified bundle. In recent years, there has been a transition from thyristor circuits and transistor in modular design. Showing the example of thyristor rectifiers and AC voltage regulators, we can conclude that there is a unity of mathematical structures and grid-tied thyristor converters.

Keywords: direct current, alternating current, rectifier, AC voltage regulator, generalized mathematical model

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Authors: S. Forel, F. Bouanis, L. Catala, I. Florea, V. Huc, F. Fossard, A. Loiseau, C. Cojocaru

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Single wall carbon nanotubes are seen as excellent candidate for application on nanoelectronic devices because of their remarkable electronic and mechanical properties. These unique properties are highly dependent on their chiral structures and the diameter. Therefore, structure controlled growth of SWNTs, especially directly on final device’s substrate surface, are highly desired for the fabrication of SWNT-based electronics. In this work, we present a new approach to control the diameter of SWNTs and eventually their chirality. Because of their potential to control the SWNT’s chirality, bi-metalics nanoparticles are used to prepare alloy nanoclusters with specific structure. The catalyst nanoparticles are pre-formed following a previously described process. Briefly, the oxide surface is first covered with a SAM (self-assembled monolayer) of a pyridine-functionalized silane. Then, bi-metallic (Fe-Ru, Co-Ru and Ni-Ru) complexes are assembled by coordination bonds on the pre-formed organic SAM. The resultant alloy nanoclusters were then used to catalyze SWNTs growth on SiO2/Si substrates via CH4/H2 double hot-filament chemical vapor deposition (d-HFCVD). The microscopy and spectroscopy analysis demonstrate the high quality of SWNTs that were furthermore integrated into high-quality SWNT-FET.

Keywords: nanotube, CVD, device, transistor

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Authors: Yu-Ting Chen, Shiao-Shing Chen, Hung-Te Hsu, Saikat Sinha Ray

Abstract:

Forward osmosis (FO) is a crucial technology with low operating pressure and cost for water reuse and reclamation. In Taiwan, with the advance of science and technology, thin film transistor liquid crystal displays (TFT-LCD) based industries are growing exponentially. In the optoelectronic industry wastewater, the iodide is one of the valuable element; it is also used in the medical industry. In this study, it was intended to concentrate iodide by utilizing FO system and can be reused for TFT-LCD production. Cellulose triacetate (CTA) membranes were used for all these FO experiments, and potassium iodide solution was used as the feed solution. It has been found that EDTA-2Na as draw solution at pH 8 produced high water flux and minimized salt leakage. The result also demonstrated that EDTA-2Na of concentration 0.6M could achieve the highest water flux (6.69L/m2 h). Additionally, from the recovered iodide ion from pH 3-8, the I- species was found to be more than 99%, whereas I2 was measured to be less than 1%. When potassium iodide solution was used from low to high concentration (1000 ppm to 10000 ppm), the iodide rejection was found to be than more 90%. Since, CTA membrane is negatively charged and I- is anionic in nature, so it will from electrostatic repulsion and hence there will be higher rejection. The overall performance demonstrates that recovery of concentrated iodide using FO system is a promising technology.

Keywords: draw solution, EDTA-2Na, forward osmosis, potassium iodide

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