Search results for: gate capacitance

Authors: Le Chen

Abstract:

This paper presents an efficient tool platform scheme to ensure quality protection throughout the software development process. The main principle is to manage the information of requirements, design, development, testing, operation and maintenance process with proper tools, and to set up the quality standards of each process. Through the tools’ display and summary of quality standards, the quality standards can be visualizad and ready for policy decision, which is called Quality Gate in this paper. In addition, the tools are also integrated to achieve the exchange and relation of information which highly improving operational efficiency. In this paper, the feasibility of the scheme is verified by practical application of development projects, and the overall information display and data mining are proposed to be further improved.

Keywords: efficiency, quality gate, software process, tools

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Authors: Kunal Das, Priya Sengupta, Abhishek K. Singh

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Pin assignment, scheduling, routing and error detection for arbitrary biochemical protocols in Digital Microfluidic Biochip have been reported in this paper. The research work is concentrating on pin assignment for 2 or 3 droplets routing in the arbitrary biochemical protocol, scheduling and routing in m × n biochip. The volumetric error arises due to droplet split in the biochip. The volumetric error detection is also addressed using biochip AND logic gate which is known as microfluidic AND or mAND gate. The algorithm for pin assignment for m × n biochip required m+n-1 numbers of pins. The basic principle of this algorithm is that no same pin will be allowed to be placed in the same column, same row and diagonal and adjacent cells. The same pin should be placed a distance apart such that interference becomes less. A case study also reported in this paper.

Keywords: digital microfludic biochip, cross-contamination, pin assignment, microfluidic AND gate

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Authors: C. S Lee, W. C. Hsu, H. Y. Liu, C. J. Lin, S. C. Yao, Y. T. Shen, Y. C. Lin

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In₀.₁₈Al₀.₈₂N/AlN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) having Al₂O₃ gate-dielectric and backside metal-trench structure are investigated. The Al₂O₃ gate oxide was formed by using a cost-effective non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. In order to enhance the heat dissipation efficiency, metal trenches were etched 3-µm deep and evaporated with a 150-nm thick Ni film on the backside of the Si substrate. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET (Schottky-gate HFET) has demonstrated improved maximum drain-source current density (IDS, max) of 1.08 (0.86) A/mm at VDS = 8 V, gate-voltage swing (GVS) of 4 (2) V, on/off-current ratio (Ion/Ioff) of 8.9 × 10⁸ (7.4 × 10⁴), subthreshold swing (SS) of 140 (244) mV/dec, two-terminal off-state gate-drain breakdown voltage (BVGD) of -191.1 (-173.8) V, turn-on voltage (Von) of 4.2 (1.2) V, and three-terminal on-state drain-source breakdown voltage (BVDS) of 155.9 (98.5) V. Enhanced power performances, including saturated output power (Pout) of 27.9 (21.5) dBm, power gain (Gₐ) of 20.3 (15.5) dB, and power-added efficiency (PAE) of 44.3% (34.8%), are obtained. Superior breakdown and RF power performances are achieved. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET design with backside metal-trench is advantageous for high-power circuit applications.

Keywords: backside metal-trench, InAlN/AlN/GaN, MOS-HFET, non-vacuum ultrasonic spray pyrolysis deposition

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Authors: Jhen-Ting Huang, Chia-Chia Chang, Hu-Cheng Weng, An-Ya Lo

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In this study, Co3O4-CNT-Graphene composite electrode was deposited by electrophoretic deposition (EPD) method, where micro polystyrene spheres (PSs) were added for co-deposition. Applied with heat treatment, a hierarchical porosity is left in the electrode which is beneficial for supercapacitor application. In terms of charge and discharge performance, we discussed the optimal CNT/Graphene ratio, macroporous ratio, and the effect of Co3O4 addition on electrode capacitance. For materials characterization, scanning electron microscope (SEM), X-ray diffraction, and BET were applied, while cyclic voltammetry (CV) and chronopotentiometry (CP) measurements, and Ragone plot were applied as in-situ analyses. Based on this, the effects of PS amount on the structure, porosity and their effect on capacitance of the electrodes were investigated. Finally, the full device performance was examined with charge-discharge and electron impedance spectrum (EIS) methods. The results show that the EPD coating with hierarchical porosity was successfully demonstrated in this study. As a result, the capacitance was greatly enhanced by 2.6 times with the hierarchical structure.

Keywords: supercapacitor, nanocarbon tub, graphene, metal oxide

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Authors: Sidi M. A. Ghaly, Mohammad O. Khan, Mohammed Shalaby, Khaled A. Al-Snaie

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Electrical capacitance tomography (ECT) is a valuable, non-invasive technique used to monitor multiphase flow processes, especially within industrial pipelines. This study focuses on the design, testing, and performance comparison of ECT sensors configured with 8, 12, and 16 electrodes, aiming to evaluate their effectiveness in imaging accuracy, resolution, and sensitivity. Each sensor configuration was designed to capture the spatial permittivity distribution within a pipeline cross-section, enabling visualization of phase distribution and flow characteristics such as oil and water interactions. The sensor designs were implemented and tested in closed pipes to assess their response to varying flow regimes. Capacitance data collected from each electrode configuration were reconstructed into cross-sectional images, enabling a comparison of image resolution, noise levels, and computational demands. Results indicate that the 16-electrode configuration yields higher image resolution and sensitivity to phase boundaries compared to the 8- and 12-electrode setups, making it more suitable for complex flow visualization. However, the 8 and 12-electrode sensors demonstrated advantages in processing speed and lower computational requirements. This comparative analysis provides critical insights into optimizing ECT sensor design based on specific industrial requirements, from high-resolution imaging to real-time monitoring needs.

Keywords: capacitance tomography, modeling, simulation, electrode, permittivity, fluid dynamics, imaging sensitivity measurement

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Authors: Yadollah Hezarjaribi, Mahdie Yari Esboi

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In this paper, a novel MEMS capacitive pressure sensor with small size and high sensitivity is presented. This sensor has the separated clamped square diaphragm and the movable plate. The diaphragm material is polysilicon. The movable and fixed plates and mechanical coupling are gold. The substrate and diaphragm are pyrex glass and polysilicon, respectively. In capacitive sensor the sensitivity is proportional to deflection and capacitance changes with pressure for this reason with this design is improved the capacitance and sensitivity with small size. This sensor is designed for low pressure between 0-60 mmHg that is used for medical application such as treatment of an incurable disease called glaucoma. The size of this sensor is 350×350 µm2 and the thickness of the diaphragm is 2µm with 1μ air gap. This structure is designed by intellisuite software. In this MEMS capacitive pressure sensor the sensor sensitivity, diaphragm mechanical sensitivity for polysilicon diaphragm are 0.0469Pf/mmHg, 0.011 μm/mmHg, respectively. According to the simulating results for low pressure, the structure with polysilicon diaphragm has more change of the displacement and capacitance, this leads to high sensitivity than other diaphragms.

Keywords: glaucoma, MEMS capacitive pressure sensor, square clamped diaphragm, polysilicon

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Authors: Aleksey Fedorov

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Building a scalable platform for quantum computing remains one of the most challenging tasks in quantum science and technologies. However, the implementation of most important quantum operations with qubits (quantum analogues of classical bits), such as multiqubit Toffoli gate, requires either a polynomial number of operation or a linear number of operations with the use of ancilla qubits. Therefore, the reduction of the number of operations in the presence of scalability is a crucial goal in quantum information processing. One of the most elegant ideas in this direction is to use qudits (multilevel systems) instead of qubits and rely on additional levels of qudits instead of ancillas. Although some of the already obtained results demonstrate a reduction of the number of operation, they suffer from high complexity and/or of the absence of scalability. We show a strong reduction of the number of operations for the realization of the Toffoli gate by using qudits for a scalable multi-qudit processor. This is done on the basis of a general relation between the dimensionality of qudits and their topology of connections, that we derived.

Keywords: quantum computing, qudits, Toffoli gates, gate decomposition

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Authors: D. Habibinia, M. R. Feyzi

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Nowadays, specialized software is vastly used to verify the performance of an electric machine prototype by evaluating a model of the system. These models mainly consist of electrical parameters such as inductances and resistances. However, when the operating frequency of the device is above one kHz, the effect of parasitic capacitances grows significantly. In this paper, a software-based procedure is introduced to model these capacitances within the electromagnetic simulation of the device. The case study is a high-frequency high-voltage pulse transformer. The Finite Element Analysis (FEA) software with coupled field analysis is used in this method.

Keywords: finite element analysis, parasitic capacitance, pulse transformer, high frequency

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Authors: Mahdiar Hosseighadiry, Farnaz Fotovatikhah, Razali Ismail, Mohsen Khaledian, Mehdi Saeidemanesh

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In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles.

Keywords: full adders, low-power, high-performance, VLSI design

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Authors: A. Ardianto, M. A. Putera Agung, S. Pramusandi

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Power waterway is one of dam structures and as an intake vertical tunnel or well function for hydroelectric power plants in Jatigede area, Sumedang, West Java. Gate shaft is also one of parts the power waterway system. The paper concerns some consideration in determining a critical state parameter on the back stability analysis of gate shaft or excavation wall stability during excavation. Study analysis was carried out using without and with reinforcement system. Results study showed that reinforcement shaft could reduce the total displacement and safety factor could increases significantly. Based on the back calculation results, it was recommended to install some reinforcement materials and drainage system to reduce pore water pressure.

Keywords: power waterway, reinforcement, displacement, safety

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Authors: Poonam A. Trambadia, Ashish V. Trambadia

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The architecture of sultanate period of Ahmedabad had evolved just before the establishment of Mughal rule in North India. After shifting the capital of the kingdom from Patan to Ahmedabad, when the buildings and structures were being built, an interesting cultural blend happened in architecture. Many sultanate buildings in Ahmedabad historic city have resemblance with Patan including the names. Outer fortification walls and Gates were built during the rule of the third ruler in the late 15th century. All the gates had sandstone slabs supported by three arched entrance in sandstone with wooden shutter. A restoration project of Khanpur Gate was initiated in 2016. The paper identifies some evidences and some hidden layers of structures as important elements of cultural interchange while some were just forgotten in the process. The recycling of pre-existing elements of structures are examined and compared. There were layers uncovered that were hidden behind later repairs using traditional brick arch, which was taken out in the process. As the gate had partially collapsed, the restoration included piece by piece dismantling and restoring in the same sequence wherever required. The recycled materials found in the process were recorded and provided the basis for this study. The gate after this discovery sets a new example of fortification Gate built in Sultanate era. The comparison excludes Maratha and British Period Gates to avoid further confusion and focuses on 15th – 16th century sultanate architecture of Ahmedabad.

Keywords: Ahmedabad World Heritage, fortification, Indo-Islamic style, Sultanate architecture, cultural interchange

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Authors: Kianoosh Ahadi, Mustafa Ergil

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In this study, the event of vibrations caused by vortexes and the distribution of induced hydrodynamic forces due to vortexes on the sliding gate valves has been investigated. For this reason, a sliding valve with the help of computational fluid dynamics (CFD) software was simulated in two-dimensional )2D(, where the flow and turbulence equations were solved for three different valve openings (full, half, and 16.7 %) models. The variety of vortexes formed within the vicinity of the valve structure was investigated based on time where the trend of fluctuations and their occurrence regions have been detected. From the gathered solution dataset of the numerical simulations, the pressure coefficient (CP), the lift force coefficient (CL), the drag force coefficient (CD), and the momentum coefficient due to hydrodynamic forces (CM) were examined, and relevant figures were generated were from these results, the vortex-induced vibrations were analyzed.

Keywords: induced vibrations, computational fluid dynamics, sliding gate valves, vortexes

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Authors: Sung Hyun You, Jeong Hoon Kim, Dae Ki Kim, Choon Ki Ahn

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In this paper, we proposed a new strategy for estimating indoor temperature based on the modified resistance capacitance (R–C) network thermal dynamic model. Using minimum variance finite impulse response (FIR) filter, accurate indoor temperature estimation can be achieved. Our study is clarified by the experimental validation of the proposed indoor temperature estimation method. This experiment scenario environment is composed of a demand response (DR) server and home energy management system (HEMS) in a test bed.

Keywords: energy consumption, resistance-capacitance network model, demand response, finite impulse response filter

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Authors: Nikhil Jain, Yang Xu, Bin Yu

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Hexagonal boron nitride (h-BN) has been used as a substrate and gate dielectric for graphene field effect transistors (GFETs). Using a graphene/h-BN/TiN (channel/dielectric/gate) stack, key material properties of h-BN were investigated i.e. dielectric strength and tunneling behavior. Work function difference between graphene and TiN results in spontaneous p-doping of graphene through a multi-layer h-BN flake. However, at high levels of current stress, n-doping of graphene is observed, possibly due to the charge transfer across the thin h-BN multi layer. Neither Direct Tunneling (DT) nor Fowler-Nordheim Tunneling (FNT) was observed in TiN/h-BN/Au hetero structures with h-BN showing two distinct volatile conduction states before breakdown. Hexagonal boron nitride emerges as a material of choice for gate dielectrics in GFETs because of robust dielectric properties and high tunneling barrier.

Keywords: graphene, transistors, conduction, hexagonal boron nitride, dielectric strength, tunneling

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Authors: J. O. Bodunrin, S. J. Moloi

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This study reports on the x-ray crystallography (XRD) structure of cadmium-implanted p-type silicon, the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of unimplanted and cadmium-implanted silicon-based diodes. Cadmium was implanted at the energy of 160 KeV to the fluence of 10¹⁵ ion/cm². The results obtained indicate that the diodes were well fabricated, and the introduction of cadmium results in a change in behavior of the diodes from normal exponential to ohmic I-V behavior. The C-V measurements, on the other hand, show that the measured capacitance increased after cadmium doping due to the injected charge carriers. The doping density of the p-Si material and the device's Schottky barrier height was extracted, and the doping density of the undoped p-Si material increased after cadmium doping while the Schottky barrier height reduced. In general, the results obtained here are similar to those obtained on the diodes fabricated on radiation-hard material, indicating that cadmium is a promising metal dopant to improve the radiation hardness of silicon. Thus, this study would assist in adding possible options to improve the radiation hardness of silicon to be used in high energy physics experiments.

Keywords: cadmium, capacitance-voltage, current-voltage, high energy physics experiment, x-ray crystallography, XRD

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Authors: Syakirin O. Yong, Nasrudin A. Rahim, Bilal M. Eid, Buray Tankut

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The aim of this paper is to develop an ultra-fast gate driver for Silicon Carbide (SiC) based switching device applications such as AC/DC DC/AC converters. Wide bandgap semiconductors such as SiC switches are growing rapidly nowadays due to their numerous capabilities such as faster switching, higher power density and higher voltage level. Wide band-gap switches can work properly on high frequencies such 50-250 kHz which is very useful for many power electronic applications such as solar inverters. Increasing the frequency minimizes the output filter size and system complexity however, this causes huge spike between MOSFET’s drain and source leg which leads to the failure of MOSFET if the voltage rating is exceeded. This paper investigates and concludes the optimum design for a gate drive board for SiC MOSFET switches without causing spikes and noises.

Keywords: PV system, lithium-ion, charger, constant current, constant voltage, renewable energy

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Authors: Indre Brazauskaite, Vilte Auruskeviciene

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The paper explores the Stage-Gate framework application for innovation maturity among small and medium-sized enterprises (SMEs). Innovation management becomes an essential business survival process for all sizes of organizations that can be evaluated and audited systemically. This research systemically defines and assesses the innovation process from the perspective of the company’s top management. Empirical research explores attitudes and existing practices of innovation management in SMEs in Baltic countries. It structurally investigates the current innovation management practices, level of standardization, and potential challenges in the area. Findings allow to structure of existing practices based on an institutionalized model and contribute to a more advanced understanding of the innovation process among SMEs. Practically, findings contribute to advanced decision-making and business planning in the process.

Keywords: innovation measure, innovation process, SMEs, stage-gate framework

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Authors: G. S. Dangayach, Gaurav Gaurav, Alok Bihari Singh

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The popularity of vehicles in both industrialized and developing economies led to a rise in the production of tyres. People have become increasingly concerned about the tyre industry's possible environmental impact in the last two decades. The life cycle assessment (LCA) methodology was used to assess the environmental impacts of industrial tyres throughout their life cycle, which included four stages: manufacture, transportation, consumption, and end-of-life. The majority of prior studies focused on tyre recycling and disposal. Only a few studies have been conducted on the environmental impact of tyre production process. LCA methodology was employed to determine the environmental impact of tyre manufacture process (gate to gate) at an Indian firm. Comparative analysis was also conducted to identify the environmental hotspots in various stages of tire manufacturing. This study is limited to gate-to-gate analysis of manufacturing processes with the functional unit of a single tyre weighing 50 kg. GaBi software was used to do both qualitative and quantitative analysis. Different environmental impact indicators are measured in terms of CO2, SO2, NOx, GWP (global warming potential), AP (acidification potential), EP (eutrophication potential), POCP (photochemical oxidant formation potential), and HTP (toxic human potential). The results demonstrate that the major contributor to environmental pollution is electricity. The Banbury process has a very high negative environmental impact, which causes respiratory problems to workers and operators.

Keywords: life cycle assessment (LCA), environmental impact indicators, tyre manufacturing process, environmental impact assessment

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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This paper proposes one stage and two stage CMOS Complementary Regulated Cascode Distributed Amplifier (CRCDA) design based on Inductive and Transformer coupling techniques. Usually, Distributed amplifier is based on inductor coupling between gate and gate of MOSFET and between drain and drain of MOSFET. But this paper propose some new idea, by coupling with differential primary windings of transformer between gate and gate of MOSFET first stage and second stage of regulated cascade amplifier and by coupling with differential secondary windings transformer of MOSFET between drain and drain of MOSFET first stage and second stage of regulated cascade amplifier. This paper also proposes polynomial modeling of Silicon Transformer passive equivalent circuit from Nanyang Technological University which is used to extract frequency response of transformer. Cadence simulation results are used to verify validity of transformer polynomial modeling which can be used to design distributed amplifier without Cadence. 4 parameters of scattering matrix of 2 port of the propose circuit is derived as a function of 4 parameters of impedance matrix.

Keywords: CMOS regulated cascode distributed amplifier, silicon transformer modeling with polynomial, low power consumption, distribute amplification technique

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Authors: Muhaned Zaidi, Ian Grout, Abu Khari bin A’ain

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In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process.

Keywords: op-amp, rail-to-rail output, Miller compensation, Negative Miller capacitance

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Authors: Mehdi Moayyedian, Kazem Abhary, Romeo Marian

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This paper presents an evaluation of a plastic defect in injection molding before it occurs in the process; it is known as the short shot defect. The evaluation of different parameters which affect the possibility of short shot defect is the aim of this paper. The analysis of short shot possibility is conducted via SolidWorks Plastics and Taguchi method to determine the most significant parameters. Finite Element Method (FEM) is employed to analyze two circular flat polypropylene plates of 1 mm thickness. Filling time, part cooling time, pressure holding time, melt temperature and gate type are chosen as process and geometric parameters, respectively. A methodology is presented herein to predict the possibility of the short-shot occurrence. The analysis determined melt temperature is the most influential parameter affecting the possibility of short shot defect with a contribution of 74.25%, and filling time with a contribution of 22%, followed by gate type with a contribution of 3.69%. It was also determined the optimum level of each parameter leading to a reduction in the possibility of short shot are gate type at level 1, filling time at level 3 and melt temperature at level 3. Finally, the most significant parameters affecting the possibility of short shot were determined to be melt temperature, filling time, and gate type.

Keywords: injection molding, plastic defects, short shot, Taguchi method

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Authors: Chae Hoon Park, Jong Kang Park, Jong Tae Kim

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Electrical characteristics of capacitive touchscreen need to be accurately analyzed to result in better performance for multi-channel capacitance sensing. In this paper, we extracted the panel resistances and capacitances of the touchscreen by comparing measurement data and model data. By employing a lumped RC model for driver-to-receiver paths in touchscreen, we estimated resistance and capacitance values according to the physical lengths of channel paths which are proportional to the RC model. As a result, we obtained the model having 95.54% accuracy of the measurement data.

Keywords: electrical characteristics of capacitive touchscreen, iterative extraction, lumped RC model, physical lengths of channel paths

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Authors: Lei Hou, Xinli Du, Nikolaos Boulgouris

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A cochlear implant, referred to as a CI, is a small electronic device that can provide direct electrical stimulation to the auditory nerve. During cochlear implant surgery, atraumatic electrode array insertion is considered to be a crucial step. However, during implantation, the mechanical behaviour of an electrode array inside the cochlea is not known. The behaviour of an electrode array inside of the cochlea is hardly identified by regular methods. In this study, a CI electrode array capacitive sensor system is proposed. It is able to automatically determine the array state as a result of the capacitance variations. Instead of applying sensors to the electrode array, the capacitance information from the electrodes will be gathered and analysed. Results reveal that this sensing method is capable of recognising different states when fed into a pre-shaped model.

Keywords: cochlear implant, electrode, hearing preservation, insertion force, capacitive sensing

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Authors: Samson Mil'shtein, Dhawal Asthana, Benjamin Sullivan

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The wide energy gap of GaN is the major parameter justifying the design and fabrication of high-power electronic components made of this material. However, the existence of a piezo-electrics in nature sheet charge at the AlGaN/GaN interface complicates the control of carrier injection into the intrinsic channel of GaN HEMTs (High Electron Mobility Transistors). As a result, most of the transistors created as R&D prototypes and all of the designs used for mass production are D-mode devices which introduce challenges in the design of integrated circuits. This research presents the design and modeling of an E-mode GaN HEMT with a very low turn-on voltage. The proposed device includes two critical elements allowing the transistor to achieve zero conductance across the channel when Vg = 0V. This is accomplished through the inclusion of an extremely thin, 2.5nm intrinsic Ga₀.₇₄Al₀.₂₆N spacer layer. The added spacer layer does not create piezoelectric strain but rather elastically follows the variations of the crystal structure of the adjacent GaN channel. The second important factor is the design of a gate metal with a high work function. The use of a metal gate with a work function (Ni in this research) greater than 5.3eV positioned on top of n-type doped (Nd=10¹⁷cm⁻³) Ga₀.₇₄Al₀.₂₆N creates the necessary built-in potential, which controls the injection of electrons into the intrinsic channel as the gate voltage is increased. The 5µm long transistor with a 0.18µm long gate and a channel width of 30µm operate at Vd=10V. At Vg =1V, the device reaches the maximum drain current of 0.6mA, which indicates a high current density. The presented device is operational at frequencies greater than 10GHz and exhibits a stable transconductance over the full range of operational gate voltages.

Keywords: compound semiconductors, device modeling, enhancement mode HEMT, gallium nitride

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Authors: Loreine Makki, Marc Anthony Mannah, Christophe Batard, Nicolas Ginot, Julien Weckbrodt

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Planar transformers are extensively utilized in high-frequency, high power density power electronic converters. The breakthrough of wide-bandgap technology compelled power electronic system miniaturization while inducing pivotal effects on system modeling and manufacturing within the power electronics industry. A significant consideration to simulate and model the unanticipated parasitic parameters emerges with the requirement to mitigate electromagnetic disturbances. This paper will present an equivalent circuit model of a shielded pulse planar transformer quantifying leakage inductance and resistance in addition to the interwinding capacitance of the primary and secondary windings. ANSYS Q3D Extractor was utilized to model and simulate the transformer, intending to study the immunity of the simulated equivalent model to high dv/dt occurrences. A convenient correlation between simulation and experimental results is presented.

Keywords: Planar transformers, wide-band gap, equivalent circuit model, shielded, ANSYS Q3D Extractor, dv/dt

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Authors: Jong-Bae Lee, Seongsoo Lee

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Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: local interconnect network, controller, transceiver, processor

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Authors: Karan R. Chavan, Paula Saavalainen, Kumudini V. Marathe, Riitta L. Keiski, Ganapati D. Yadav

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Co-contamination of groundwaters by arsenic in different forms is often observed around the globe. Arsenic is introduced into the waters by several mechanisms and different technologies are proposed and practiced for effective removal. The assessment of three prominent technologies, namely, adsorption, ion exchange and nanofiltration was carried out in this study based on lifecycle methodology. The life of the technologies was divided into two stages: cradle to gate (C-G) and gate to gate (G-G), in order to find out the impacts in different categories of environmental burdens, human health and resource consumption. Life cycle inventory was estimated by use of models and design equations concerning with the different technologies. Regeneration was considered for each technology and over the course of its full lifetime. The impact values of adsorption technology for the C-G stage are greater by thousand times (103) and million times (106) compared to ion exchange and nanofiltration technologies, respectively. The impact of G-G stage of the lifecycle is the major contributor of the impact for all the 3 technologies due to electricity consumption during the operation. Overall, the ion Exchange technology fares well in this study of removal of As (V) only.

Keywords: arsenic, nanofiltration, lifecycle assessment, membrane technology

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Authors: Syed Kamran Sami, Saqib Siddiqui

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In recent times, flexible supercapacitors retaining high electrochemical performance and steadiness along with mechanical endurance has developed as a spring of attraction due to the exponential progress and innovations in energy storage devices. To meet the rampant increasing demand of energy storage device with the small form factor, a unique, low cost and high-performance supercapacitor with considerably higher capacitance and mechanical robustness is required to recognize their real-life applications. Here in this report, synthesis route of electrode materials with low rigidity and high charge storage performance is reported using 1D-1D hybrid structure of zinc oxide (ZnO) nanorods, and conductive polymer smeared polyvinylidene fluoride–trifluoroethylene (P(VDF–TrFE)) electrospun nanofibers. The ZnO nanorods were uniformly grown on poly (3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT: PSS) coated P(VDF-TrFE) nanofibers using hydrothermal growth to manufacture light weight, permeable electrodes for supercapacitor. The PEDOT: PSS coated P(VDF-TrFE) porous web of nanofibers act as framework with high surface area. The incorporation of ZnO nanorods further boost the specific capacitance by 59%. The symmetric device using the fabricated 1D-1D hybrid electrodes reveals fairly high areal capacitance of 1.22mF/cm² at a current density of 0.1 mA/cm² with a power density of more than 1600 W/Kg. Moreover, the fabricated electrodes show exceptional flexibility and high endurance with 90% and 76% specific capacitance retention after 1000 and 5000 cycles respectively signifying the astonishing mechanical durability and long-term stability. All the properties exhibited by the fabricated electrode make it convenient for making flexible energy storage devices with the low form factor.

Keywords: ZnO nanorods, electrospinning, mechanical endurance, flexible supercapacitor

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Authors: Seyedmirsajad Mokhtarimousavi, Danial Talebi, Hamidreza Asgari

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Gate Assignment Problem (GAP) is one of the most substantial issues in airport operation. In principle, GAP intends to maintain the maximum capacity of the airport through the best possible allocation of the resources (gates) in order to reach the optimum outcome. The problem involves a wide range of dependent and independent resources and their limitations, which add to the complexity of GAP from both theoretical and practical perspective. In this study, GAP was mathematically formulated as a three-objective problem. The preliminary goal of multi-objective formulation was to address a higher number of objectives that can be simultaneously optimized and therefore increase the practical efficiency of the final solution. The problem is solved by applying the second version of Non-dominated Sorting Genetic Algorithm (NSGA-II). Results showed that the proposed mathematical model could address most of major criteria in the decision-making process in airport management in terms of minimizing both airport/airline cost and passenger walking distance time. Moreover, the proposed approach could properly find acceptable possible answers.

Keywords: airport management, gate assignment problem, mathematical modeling, genetic algorithm, NSGA-II

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Authors: Seyedmirsajad Mokhtarimousavi, Danial Talebi, Hamidreza Asgari

Abstract:

Assigning aircrafts’ activities to appropriate gates is one the most challenging issues in airport authorities’ multiple criteria decision making. The potential financial loss due to imbalances of demand and supply in congested airports, higher occupation rates of gates, and the existing restrictions to expand facilities provide further evidence for the need for an optimal supply allocation. Passengers walking distance, towing movements, extra fuel consumption (as a result of awaiting longer to taxi when taxi conflicts happen at the apron area), etc. are the major traditional components involved in GAP models. In particular, the total cost associated with gate assignment problem highly depends on the airport terminal layout. The study herein presents a well-elaborated literature review on the topic focusing on major concerns, applicable variables and objectives, as well as proposing a three-objective mathematical model for the gate assignment problem. The model has been tested under different concourse layouts in order to check its performance in different scenarios. Results revealed that terminal layout pattern is a significant parameter in airport and that the proposed model is capable of dealing with key constraints and objectives, which supports its practical usability for future decision making tools. Potential solution techniques were also suggested in this study for future works.

Keywords: airport management, terminal layout, gate assignment problem, mathematical modeling

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