Search results for: uncut chip thickness

Authors: T. C. Bera, A. Bansal, D. Nema

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During performing turning operation, cutting force plays a significant role in metal cutting process affecting tool-work piece deflection, vibration and eventually part quality. The present research work aims to develop a mechanistic cutting force model and to study the mechanistic constants used in the force model in case of turning operation. The proposed model can be used for the reliable and accurate estimation of the cutting forces establishing relationship of various force components (cutting force and feed force) with uncut chip thickness. The accurate estimation of cutting force is required to improve thin-walled part accuracy by controlling the tool-work piece deflection induced surface errors and tool-work piece vibration.

Keywords: turning, cutting forces, cutting constants, uncut chip thickness

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Authors: Muthana Saleh Alalaki, Michael Opoku Agyeman

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The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements. As a result, Network-on-Chip (NoC) has emerged as a system architecture to overcome intra-communication issues. This paper presents a study of recent contributions on simulation tools for NoC. Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication.

Keywords: WiNoC, simulation tool, network-on-chip, SoC

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Authors: Wanida Wonsawat

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Bioreduction of silver nanoparticles (AgNPs) from silver ions (Ag+) using water extract of Thai basil leaf was successfully carried out. The basil leaf extract provided a reducing agent and stabilizing agent for a synthesis of metal nanoparticles. Silver nanoparticles received from cut and uncut basil leaf was compared. The resulting silver nanoparticles are characterized by UV-Vis spectroscopy. The maximum intensities of silver nanoparticle from cut and uncut basil leaf were 410 and 420, respectively. The techniques involved are simple, eco-friendly and rapid.

Keywords: basil leaves, silver nanoparticles, green synthesis, plant extract

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Authors: Theena Thayalan, K. N. Ramesh Babu

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Machining induced residual stress (RS) is one of the most important surface integrity parameters that characterize the near surface layer of a mechanical component, which plays a crucial role in controlling the performance, especially its fatigue life. Since experimental determination of RS is expensive and time consuming, it would be of great benefit if they could be predicted. In such case, it would be possible to select the cutting parameters required to produce a favorable RS profile. In the present study, an effort has been made to develop a 'two dimensional finite element model (FEM)' to simulate orthogonal cutting process and to predict surface and sub-surface RS using the commercial FEA software DEFORM-2D. The developed finite element model has been validated through experimental investigation of RS. In the experimentation, the orthogonal cutting tests were carried out on AISI 4340 by varying the cutting speed (VC) and uncut chip thickness (f) at three levels and the surface & sub-surface RS has been measured using XRD and Electro polishing techniques. The comparison showed that the RS obtained using developed numerical model is in reasonable agreement with that of experimental data.

Keywords: FEM, machining, residual stress, XRF

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Authors: Boudjedra Abderrahim, Toumi Salah, Boutalbi Mostefa, Frihi Mohammed

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Nowadays, using the advancement of technology in semiconductor device fabrication, many transistors can be integrated to a single chip (VLSI). Although the growth chip density potentially eases systems-on-chip (SoCs) integrating thousands of processing element (PE) such as memory, processor, interfaces cores, system complexity, high-performance interconnect and scalable on-chip communication architecture become most challenges for many digital and embedded system designers. Networks-on-chip (NoCs) becomes a new paradigm that makes possible integrating heterogeneous devices and allows many communication constraints and performances. In this paper, we are interested for good performance and low area for implementation and a behavioral modeling of network on chip mesh topology design using VHDL hardware description language with performance evaluation and FPGA implementation results.

Keywords: design, implementation, communication system, network on chip, VHDL

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Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, Md Hanif Md Nasir

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This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Keywords: methodology, flip chip, bump cell, LEF, astro, calibre, SCHEME, TCL

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Authors: Long Kim Vu

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The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method.

Keywords: CFD, FPGA, heat transfer, thermal analysis

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Authors: Anil Kawan, Soon Jae Yu, Jong Min Park

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GaN-based 365 nm wavelength ultraviolet (UV) light emitting diodes (LED) have various applications: curing, molding, purification, deodorization, and disinfection etc. However, their usage is limited by very low output power, because of the light absorption in the GaN layers. In this study, we demonstrate a method utilizing removal of 365 nm absorption layer buffer GaN and thinning the n-type GaN so as to improve the light extraction efficiency of the GaN-based 365 nm UV LED. The UV flip chip LEDs of chip size 1.3 mm x 1.3 mm were fabricated using GaN epilayers on a sapphire substrate. Via-hole n-type contacts and highly reflective Ag metal were used for efficient light extraction. LED wafer was aligned and bonded to AlN carrier wafer. To improve the extraction efficiency of the flip chip LED, sapphire substrate and absorption layer buffer GaN were removed by using laser lift-off and dry etching, respectively. To further increase the extraction efficiency of the LED, exposed n-type GaN thickness was reduced by using inductively coupled plasma etching.

Keywords: extraction efficiency, light emitting diodes, n-GaN thinning, ultraviolet

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Authors: Bhuvnesh Narayanan, Bernhard Weiss, Tvrtko Mandic, Adrijan Baric

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This paper discusses a method to reconstruct internal high-frequency signals through subsampling techniques in an IC using an on-chip sensor. Though there are existing methods to internally probe and reconstruct high frequency signals through subsampling techniques; these methods have been applicable mainly for synchronized systems. This paper demonstrates a method for making such non-intrusive on-chip reconstructions possible also in non-synchronized systems. The TLP pulse is used to demonstrate the experimental validation of the concept. The on-chip sensor measures the voltage in an internal node. The jitter in the input pulse causes a varying pulse delay with respect to the on-chip sampling command. By measuring this pulse delay and by correlating it with the measured on-chip voltage, time domain waveforms can be reconstructed, and the influence of the pulse on the internal nodes can be better understood.

Keywords: on-chip sensor, jitter, transmission line pulse, subsampling

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Authors: Rafiqul Tarefder, Mohiuddin Ahmad, Mohammad Hossain

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While milling materials from old pavement surface can be an important component of cost effective maintenance operation, their use in maintenance projects are not uniform and well documented. This study documents the different maintenance practices followed by four transportation districts of New Mexico Department of Transportation (NMDOT) in an attempt to find whether millings are being used in maintenance projects by those districts. Based on existing literature, a questionnaire was developed related to six common maintenance practices. NMDOT district personal were interviewed face to face to discuss and get answers to that questionnaire. It revealed that NMDOT districts mainly use chip seal and patching. Other maintenance procedures such as sand seal, scrub seal, slurry seal, and thin overlay have limited use. Two out of four participating districts do not have any documents on chip sealing; rather they employ the experiences of the chip seal crew. All districts use polymer modified high float emulsion (HFE100P) for chip seal with an application rate ranging from 0.4 to 0.56 gallons per square yard. Chip application rate varies from 15 to 40 lb/ square yard. State wide, the thickness of chip seal varies from 3/8" to 1" and life varies from 3 to 10 years. NMDOT districts mainly use three type of patching: pothole, dig-out and blade patch. Pothole patches are used for small potholes and during emergency, dig-out patches are used for all type of potholes sometimes after pothole patching, and blade patch is used when a significant portion of the pavement is damaged. Pothole patches last as low as three days whereas, blade patch lasts as long as 3 years. It was observed that all participating districts use millings in maintenance projects.

Keywords: chip seal, sand seal, scrub seal, slurry seal, overlay, patching, millings

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Authors: J. Shiue, I. H. Chen, S. W. Y. Chiu, Y. L. Wang

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In this work, we present a nondestructive method to characterize bacteria in a TEM system. Unlike the conventional TEM specimen preparation method, which needs to thin the specimen in a destructive way, or spread the samples on a tiny millimeter sized carbon grid, our method is easy to operate without the need of sample pretreatment. With a specially designed transparent chip that allows the electron beam to pass through, and a custom made chip holder to fit into a standard TEM sample holder, the bacteria specimen can be easily prepared on the chip without any pretreatment, and then be observed under TEM. The centimeter-sized chip is covered with Au nanoparticles in the surface as the markers which allow the bacteria to be observed easily on the chip. We demonstrate the success of our method by using E. coli as an example, and show that high-resolution TEM images of E. coli can be obtained with the method presented. Some E. coli morphology characteristics imaged using this method are also presented.

Keywords: bacteria, chip, nanoparticles, TEM

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Authors: Nesrine Toubaline, Djamel Bennouar, Ali Mahdoum

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3D technology can lead to a significant reduction in power and average hop-count in Networks on Chip (NoCs). It offers short and fast vertical links which copes with the long wire problem in 2D NoCs. This work proposes heuristic-based method to optimize number and placement of vertical links to achieve specified performance goals. Experiments show that significant improvement can be achieved by using a specific number of vertical interconnect.

Keywords: interconnect optimization, monolithic inter-tier vias, network on chip, system on chip, through silicon vias, three dimensional integration circuits

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Authors: Reza Hadjiaghaie Vafaie, Aysan Madanpasandi, Behrooz Zare Desari, Seyedmohammad Mousavi

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High lamination in microchannel is one of the main challenges in on-chip components like micro total analyzer systems and lab-on-a-chips. Electro-osmotic force is highly effective in chip-scale. This research proposes a microfluidic-based micropump for low ionic strength solutions. Narrow microchannels are designed to generate an efficient electroosmotic flow near the walls. Microelectrodes are embedded in the lateral sides and actuated by low electric potential to generate pumping effect inside the channel. Based on the simulation study, the fluid velocity increases by increasing the electric potential amplitude. We achieve a net flow velocity of 100 µm/s, by applying +/- 2 V to the electrode structures. Our proposed low voltage design is of interest in conventional lab-on-a-chip applications.

Keywords: integration, electrokinetic, on-chip, fluid pumping, microfluidic

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Authors: Martin Pumera

Abstract:

Graphene materials are being widely used in electrochemistry due to their versatility and excellent properties as platforms for biosensing. Here we present current trends in the electrochemical biosensing of pesticides and other toxic compounds. We explore two fundamentally different designs, (i) using graphene and other 2-D nanomaterials as an electrochemical platform and (ii) using these nanomaterials in the laboratory on chip design, together with paramagnetic beads. More specifically: (i) We explore graphene as transducer platform with very good conductivity, large surface area, and fast heterogeneous electron transfer for the biosensing. We will present the comparison of these materials and of the immobilization techniques. (ii) We present use of the graphene in the laboratory on chip systems. Laboratory on the chip had a huge advantage due to small footprint, fast analysis times and sample handling. We will show the application of these systems for pesticide detection and detection of other toxic compounds.

Keywords: graphene, 2D nanomaterials, biosensing, chip design

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Authors: Ş. Karabulut, A. Güllü, A. Güldaş, R. Gürbüz

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This study investigates the effects of the lead angle and chip thickness variation on surface roughness during the machining of compacted graphite iron using ceramic cutting tools under dry cutting conditions. Analytical models were developed for predicting the surface roughness values of the specimens after the face milling process. Experimental data was collected and imported to the artificial neural network model. A multilayer perceptron model was used with the back propagation algorithm employing the input parameters of lead angle, cutting speed and feed rate in connection with chip thickness. Furthermore, analysis of variance was employed to determine the effects of the cutting parameters on surface roughness. Artificial neural network and regression analysis were used to predict surface roughness. The values thus predicted were compared with the collected experimental data, and the corresponding percentage error was computed. Analysis results revealed that the lead angle is the dominant factor affecting surface roughness. Experimental results indicated an improvement in the surface roughness value with decreasing lead angle value from 88° to 45°.

Keywords: CGI, milling, surface roughness, ANN, regression, modeling, analysis

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Authors: Mohsen Marani Barzani, Ahmed A. D. Sarhan, Saeed Farahany, Ramesh Singh

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Surface roughness and chip morphology are important output in manufacturing product. In this paper, an experimental investigation was conducted to determine the effects of various cutting speeds and feed rates on surface roughness and chip morphology in turning the Al-Si cast alloy and Sr-containing. Experimental trials carried out using coated carbide inserts. Experiments accomplished under oblique dry cutting when various cutting speeds 70, 130 and 250 m/min and feed rates of 0.05, 0.1 and 0.15 mm/rev were used, whereas depth of cut kept constant at 0.05 mm. The results showed that Sr-containing Al-Si alloy have poor surface roughness in comparison to Al-Si alloy (base alloy). The surface roughness values reduce with cutting speed increment from 70 to 250 m/min. the size of chip changed with changing silicon shape in Al matrix. Also, the surface finish deteriorated with increase in feed rate from 0.5 mm/rev to 0.15 mm/rev.

Keywords: strontium, surface roughness, chip, morphology, turning

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Authors: M. Benghersallah, L. Boulanouar, G. List, G. Sutter

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The present work is an experimental study on the dry high speed turning of Ti-6Al-4V titanium alloy. The objective of this study is to see for high cutting speeds, how wear occurs on the face of insert and how to evolve cutting forces and chip formation. Cutting speeds tested is 600, 800, 1000 and 1200 m / min in orthogonal turning with a carbide insert tool H13A uncoated on a cylindrical titanium alloy part. Investigation on the wear inserts with 3D scanning microscope revered the crater formation is instantaneous and a chip adhesion (welded chip) causes detachment of carbide particles. In these experiments, the chip shape was systematically investigated at each cutting conditions using optical microscopy. The chips produced were collected and polished to measure the thicknesses t2max and t2min, dch the distance between each segments and ɸseg the inclination angle As described in the introduction part, the shear angle f and the inclination angle of a segment ɸseg are differentiated. The angle ɸseg is actually measured on the collected chips while the shear angle f cannot be. The angle ɸ represents the initial shear similar to the one that describes the formation of a continuous chip in the primary shear zone. Cutting forces increase and stabilize before removing the tool. The chip reaches a very high temperature.

Keywords: dry high speed, orthogonal turning, chip formation, cutting speed, cutting forces

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Authors: Zhuohan Li, Jing Yang, Yaoyuan Cui

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The gut-brain axis (GBA), a communication network between gut microbiota and the brain, benefits for investigation of brain diseases. Currently, organ chips are considered one of the potential tools for GBA research. However, most of the available GBA chips have limitations in replicating the three-dimensional (3D) growth environment of cells and lack the required cell types for barrier function. In the present study, a microfluidic chip was developed for GBA interaction. Blood-brain barrier (BBB) module was prepared with HBMEC, HBVP, U87 cells and decellularized matrix (dECM). Intestinal epithelial barrier (IEB) was prepared with Caco-2 and vascular endothelial cells and dECM. GBA microfluidic device was integrated with IEB and BBB modules using 3D printing interconnecting microchannel scaffolds. BBB and IEB interaction on this GBA chip were evaluated with lipopolysaccharide (LPS) exposure. The present GBA chip achieved multicellular three-dimensional cultivation. Compared with the co-culture cell model in the transwell, fluorescein was absorbed more slowly by 5.16-fold (IEB module) and 4.69-fold (BBB module) on the GBA chip. Accumulation of Rhodamine 123 and Hoechst33342 was dramatically decreased. The efflux function of transporters on IEB and BBB was significantly increased on the GBA chip. After lipopolysaccharide (LPS) disrupted the IEB, and then BBB dysfunction was further observed, which confirmed the interaction between IEB and BBB modules. These results demonstrated that this GBA chip may offer a promising tool for gut-brain interaction study.

Keywords: decellularized matrix, gut-brain axis, organ-on-chip, three-dimensional printing.

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Authors: Chien-Ju Chen, Chia-Jui Yu, Jyun-Hao Liao, Chia-Ching Wu, Meng-Chyi Wu

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A 64 × 64 GaN-based micro-light-emitting diode array (μLEDA) with 20 μm in pixel size and 40 μm in pitch by flip-chip bonding (FCB) is demonstrated in this study. Besides, an underfilling (UF) technology is applied to the process for improving the uniformity of device. With those configurations, good characteristics are presented, operation voltage and series resistance of a pixel in the 450 nm flip chip μLEDA are 2.89 V and 1077Ω (4.3 mΩ-cm²) at 25 A/cm², respectively. The μLEDA can sustain higher current density compared to conventional LED, and the power of the device is 9.5 μW at 100 μA and 0.42 mW at 20 mA.

Keywords: GaN, micro-light-emitting diode array(μLEDA), flip-chip bonding, underfilling

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Authors: Longfei Wang, Selçuk Köse

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Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

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Authors: Jana Stucke, Sean Tuling, Chris Toomer

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This study focuses on the numerical investigation of the leading edge vortex (LEV) development over a 65° swept delta wing with varying thickness and maximum thickness location and their impact on its overall performance. The tested configurations are defined by a 6% and 12 % thick biconvex aerofoil with maximum thickness location at 30% and 50% of the root chord. The results are compared to a flat plate delta wing configuration of 3.4% thickness. The largest differences are observed for the aerofoils of 12% thickness and are used to demonstrate the trends and aerodynamic characteristics from here on. It was found that the vortex structure changes with change with maximum thickness and overall thickness. This change leads to not only a reduction in lift but also in drag, especially when the maximum thickness is moved forward. The reduction in drag, however, outweighs the loss in lift thus increasing the overall performance of the configuration.

Keywords: aerodynamics, CFD, delta wing, leading edge vortices

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Authors: Daniel Nieto, Ramiro Couceiro

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Microfluidic chips have demonstrated their significant application potentials in microbiological processing and chemical reactions, with the goal of developing monolithic and compact chip-sized multifunctional systems. Heat generation and thermal control are critical in some of the biochemical processes. The paper presents a laser direct-write technique for rapid prototyping and manufacturing of microheater chips and its applicability for perfusion cell culture outside a cell incubator. The aim of the microheater is to take the role of conventional incubators for cell culture for facilitating microscopic observation or other online monitoring activities during cell culture and provides portability of cell culture operation. Microheaters (5 mm × 5 mm) have been successfully fabricated on soda-lime glass substrates covered with aluminum layer of thickness 120 nm. Experimental results show that the microheaters exhibit good performance in temperature rise and decay characteristics, with localized heating at targeted spatial domains. These microheaters were suitable for a maximum long-term operation temperature of 120ºC and validated for long-time operation at 37ºC. for 24 hours. Results demonstrated that the physiology of the cultured SW480 adenocarcinoma of the colon cell line on the developed microheater chip was consistent with that of an incubator.

Keywords: laser microfabrication, microheater, bioengineering, cell culture

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Authors: M. Benghersallah, G. List, G. Sutter

Abstract:

The present work is an experimental study on the dry high speed turning of Ti-6Al-4V titanium alloy. The objective of this study is to see for high cutting speeds, how wear occurs on the face of insert and how to evolve cutting forces and chip formation. Cutting speeds tested is 600, 800, 1000, and 1200 m/min in orthogonal turning with a carbide insert tool H13A uncoated on a cylindrical titanium alloy part. Investigation on the wear inserts with 3D scanning microscope revered the crater formation is instantaneous and a chip adhesion (welded chip) causes detachment of carbide particles. Cutting forces increase and stabilize before removing the tool. The chip reaches a very high temperature.

Keywords: titanium alloy, dry hjgh speed turning, wear insert, MQL technique

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Authors: Moaz H. Ali, Ahmed H. Al-Saadi

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Most of the materials used in the industry of aero-engine components generally consist of titanium alloys. Advanced materials, because of their excellent combination of high specific strength, lightweight, and general corrosion resistance. In fact, chemical wear resistance of aero-engine alloy provide a serious challenge for cutting tool material during the machining process. The reduction in cutting temperature distributions leads to an increase in tool life and a decrease in wear rate. Hence, the chip morphology and segmentation play a predominant role in determining machinability and tool wear during the machining process. The result of low thermal conductivity and diffusivity of this alloy in the concentration of high temperatures at the tool-work-piece and tool-chip interface. Consequently, the chip morphology is very important in the study of machinability of metals as well as the study of cutting tool wear. Otherwise, the result will be accelerating tool wear, increasing manufacturing cost and time consuming.

Keywords: machinability, titanium alloy (ti-6al-4v), chip formation, milling process

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Authors: D. O. Ramadan, R. S. Dwyer-Joyce

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The measurement of the interface conditions in a cutting tool contact is essential information for performance monitoring and control. This interface provides the path for the heat flux to the cutting tool. This elevate in the cutting tool temperature leads to motivate the mechanism of tool wear, thus affect the life of the cutting tool and the productivity. This zone is representative by the tool-chip interface. Therefore, understanding and monitoring this interface is considered an important issue in machining. In this paper, an acoustic emission (AE) technique was used to find the correlation between AE parameters and the tool-chip interface. For this reason, a response surface design (RSD) has been used to analyse and optimize the machining parameters. The experiment design was based on the face centered, central composite design (CCD) in the Minitab environment. According to this design, a series of orthogonal cutting experiments for different cutting conditions were conducted on a Triumph 2500 lathe machine to study the sensitivity of the acoustic emission (AE) signal to change in tool-chip contact length. The cutting parameters investigated were the cutting speed, depth of cut, and feed and the experiments were performed for 6082-T6 aluminium tube. All the orthogonal cutting experiments were conducted unlubricated. The tool-chip contact area was investigated using a scanning electron microscope (SEM). The results obtained in this paper indicate that there is a strong dependence of the root mean square (RMS) on the cutting speed, where the RMS increases with increasing the cutting speed. A dependence on the tool-chip contact length has been also observed. However there was no effect observed of changing the cutting depth and feed on the RMS. These dependencies have been clarified in terms of the strain and temperature in the primary and secondary shear zones, also the tool-chip sticking and sliding phenomenon and the effect of these mechanical variables on dislocation activity at high strain rates. In conclusion, the acoustic emission technique has the potential to monitor in situ the tool-chip interface in turning and consequently could indicate the approaching end of life of a cutting tool.

Keywords: Acoustic emission, tool-chip interface, orthogonal cutting, monitoring

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Authors: M. Jalali Azizpour, H.Mohammadi Majd

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In this paper, the effect of WC-12Co particle Temperature in HVOF thermal spraying process on the coating thickness has been studied. The statistical results show that the spray distance and oxygen-to-fuel ratio are more effective factors on particle characterization and thickness of HVOF thermal spraying coatings. Spray Watch diagnostic system, scanning electron microscopy (SEM), X-ray diffraction and thickness measuring system were used for this purpose.

Keywords: HVOF, temperature, thickness, velocity, WC-12Co

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Authors: Laura Boschis, Elena D. Ozzello, Enzo Mastromatteo

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Point of care diagnostic finds growing interest in medicine and agri-food because of faster intervention and prevention. EliChip is a microfluidic platform to perform Point of Care immunoenzymatic assay based on ready-to-use kits and a portable instrument to manage fluidics and read reliable quantitative results. Thanks to miniaturization, analyses are faster and more sensible than conventional ELISA. EliChip is one of the crucial assets of the Europen-founded Flamingo project for in-line measuring inflammatory markers.

Keywords: lab on chip, point of care, immunoenzymatic analysis, synovial arthritis

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Authors: M. Jalali Azizpour

Abstract:

In this paper, the effect of WC-12Co particle Temperature in HVOF thermal spraying process on the coating thickness has been studied. The statistical results show that the spray distance and oxygen-to-fuel ratio are more effective factors on particle characterization and thickness of HVOF thermal spraying coatings. Spray Watch diagnostic system, scanning electron microscopy (SEM), X-ray diffraction and thickness measuring system were used for this purpose.

Keywords: HVOF, temperature thickness, velocity, WC-12Co

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Authors: Junior Nomani

Abstract:

This paper presents a novel approach to modelling the metal cutting of duplex stainless steels, a two-phase alloy regarded as a difficult-to-machine material. Calculation and control of shear strain and stresses during cutting are essential to achievement of ideal cutting conditions. Too low or too high leads to higher required cutting force or excessive heat generation causing premature tool wear failure. A 2D finite element cutting model was created based on electron backscatter diffraction (EBSD) data imagery of duplex microstructure. A mesh was generated using ‘object-oriented’ software OOF2 version V2.1.11, converting microstructural images to quadrilateral elements. A virtual workpiece was created on ABAQUS modelling software where a rigid body toolpiece advanced towards workpiece simulating chip formation, generating serrated edge chip formation cutting. Model results found calculated stress strain contour plots correlated well with similar finite element models tied with austenite stainless steel alloys. Virtual chip form profile is also similar compared experimental frozen machining chip samples. The output model data provides new insight description of strain behavior of two phase material on how it transitions from workpiece into the chip.

Keywords: Duplex stainless steel, ABAQUS, OOF2, Chip formation

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Authors: Zhao Bin, Yan Dan Lei

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In this paper, a multi-pattern parallel PRBS generator and a dedicated parallel BER tester is proposed for the 8-Gbps On-chip interconnection testing. A unique full-parallel PRBS checker is also proposed. The proposed design, together with the custom-designed high-speed parallel-to-serial and the serial-to-parallel circuit, will be used to test different on-chip interconnection transceivers. The design is implemented in TSMC 28nm CMOS technology with working voltage at 1.0 V. The serial to parallel ratio is 8:1 so the parallel PRBS generation and BER Tester can be run at lower speed.

Keywords: PRBS, BER, high speed, generator

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