Search results for: triple gate (TG)

Authors: Mohamed I. Mahmoud, Moawad I. M. Dessouky, Salah Deyab, Fatma H. Elfouly

Abstract:

Recently, the Field Programmable Gate Array (FPGA) technology offers the potential of designing high performance systems at low cost. The discrete wavelet transform has gained the reputation of being a very effective signal analysis tool for many practical applications. However, due to its computation-intensive nature, current implementation of the transform falls short of meeting real-time processing requirements of most application. The objectives of this paper are implement the Haar and Daubechies wavelets using FPGA technology. In addition, the comparison between the Haar and Daubechies wavelets is investigated. The Bit Error Rat (BER) between the input audio signal and the reconstructed output signal for each wavelet is calculated. It is seen that the BER using Daubechies wavelet techniques is less than Haar wavelet. The design procedure has been explained and designed using the stat-of-art Electronic Design Automation (EDA) tools for system design on FPGA. Simulation, synthesis and implementation on the FPGA target technology has been carried out.

Keywords: Daubechies wavelet, discrete wavelet transform, Haar wavelet, Xilinx FPGA.

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Authors: H. Fallah, Z. Naddaf Baghdadabadi

Abstract:

Planning of economic activities development has various dimensions one of which determines adequate capacity of economic activities in provinces regarding the government-s goals. Paralleling planning goals of economic activities development including subjects being focused on the view statement is effective to better realize the statement's goals. Current paper presents a native framework for economic activities development in provincial level. Triple steps within the framework are concordant with the view statement-s goals achievement. At first step of the proposed framework, economic activities are being prioritized in terms of employment indices, and secondly economic activities regarding to the province's relative advantages are being recognized. In the third step, desirable capacity of economic activities is determined with regards to the government's goals and effective constraints in economic activities development. Development of economic activities related to the provinces- relative advantages, contributes on regional balance and on equal development of economic activities. Furthermore, results of the framework enable more confident investment, affect employment development and remove unemployment concern as the main goals of the view statement.

Keywords: Development, economic activity, regional planning, view statement.

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Authors: Hossam el-ddin Mostafa, Pavel Čičak

Abstract:

The mobile users with Laptops need to have an efficient access to i.e. their home personal data or to the Internet from any place in the world, regardless of their location or point of attachment, especially while roaming outside the home subnet. An efficient interpretation of packet losses problem that is encountered from this roaming is to the centric of all aspects in this work, to be over-highlighted. The main previous works, such as BER-systems, Amigos, and ns-2 implementation that are considered to be in conjunction with that problem under study are reviewed and discussed. Their drawbacks and limitations, of stopping only at monitoring, and not to provide an actual solution for eliminating or even restricting these losses, are mentioned. Besides that, the framework around which we built a Triple-R sequence as a costeffective solution to eliminate the packet losses and bridge the gap between subnets, an area that until now has been largely neglected, is presented. The results show that, in addition to the high bit error rate of wireless mobile networks, mainly the low efficiency of mobile-IP registration procedure is a direct cause of these packet losses. Furthermore, the output of packet losses interpretation resulted an illustrated triangle of the registration process. This triangle should be further researched and analyzed in our future work.

Keywords: Amigos, BER-systems, ns-2 implementation, packetlosses, registration process, roaming.

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Authors: Cyrille Lambert, Tatiana Kalganova, Emanuele Stomeo

Abstract:

Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.

Keywords: Evolvable hardware, evolutionary computation, FPGA systems.

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Authors: Iqbalur Rahman, Miftahur Rahman, Abul L Haque, Mostafizur Rahman,

Abstract:

In this paper, RSA encryption algorithm and its hardware implementation in Xilinx-s Virtex Field Programmable Gate Arrays (FPGA) is analyzed. The issues of scalability, flexible performance, and silicon efficiency for the hardware acceleration of public key crypto systems are being explored in the present work. Using techniques based on the interleaved math for exponentiation, the proposed RSA calculation architecture is compared to existing FPGA-based solutions for speed, FPGA utilization, and scalability. The paper covers the RSA encryption algorithm, interleaved multiplication, Miller Rabin algorithm for primality test, extended Euclidean math, basic FPGA technology, and the implementation details of the proposed RSA calculation architecture. Performance of several alternative hardware architectures is discussed and compared. Finally, conclusion is drawn, highlighting the advantages of a fully flexible & parameterized design.

Keywords: Crypto Accelerator, FPGA, Public Key Cryptography, RSA.

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Authors: M. Mansouri, P. Jaklitsch, E. Teiniker

Abstract:

SQL injection on web applications is a very popular kind of attack. There are mechanisms such as intrusion detection systems in order to detect this attack. These strategies often rely on techniques implemented at high layers of the application but do not consider the low level of system calls. The problem of only considering the high level perspective is that an attacker can circumvent the detection tools using certain techniques such as URL encoding. One technique currently used for detecting low-level attacks on privileged processes is the tracing of system calls. System calls act as a single gate to the Operating System (OS) kernel; they allow catching the critical data at an appropriate level of detail. Our basic assumption is that any type of application, be it a system service, utility program or Web application, “speaks” the language of system calls when having a conversation with the OS kernel. At this level we can see the actual attack while it is happening. We conduct an experiment in order to demonstrate the suitability of system call analysis for detecting SQL injection. We are able to detect the attack. Therefore we conclude that system calls are not only powerful in detecting low-level attacks but that they also enable us to detect highlevel attacks such as SQL injection.

Keywords: Linux system calls, Web attack detection, Interception.

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Authors: Satoru Kaneko, Takeshi Ito, Kensuke Akiyama, Manabu Yasui, Chihiro Kato, Satomi Tanaka, Yasuo Hirabayashi, Takeshi Ozawa, Akira Matsuno, Takashi Nire, Hiroshi Funakubo, Mamoru Yoshimoto

Abstract:

As application of re-activation of backside on power device Insulated Gate Bipolar Transistor (IGBT), laser annealing was employed to irradiate amorphous silicon substrate, and resistivities were measured using four point probe measurement. For annealing the amorphous silicon two lasers were used at wavelength of visible green (532 nm) together with Infrared (793 nm). While the green laser efficiently increased temperature at top surface the Infrared laser reached more deep inside and was effective for melting the top surface. A finite element method was employed to evaluate time dependent thermal distribution in silicon substrate.

Keywords: laser, annealing, silicon, recrystallization, thermal distribution, resistivity, finite element method, absorption, melting point, latent heat of fusion.

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Authors: Fatma H. Elfouly, Mohamed I. Mahmoud, Moawad I. M. Dessouky, Salah Deyab

Abstract:

Recently, the Field Programmable Gate Array (FPGA) technology offers the potential of designing high performance systems at low cost. The discrete wavelet transform has gained the reputation of being a very effective signal analysis tool for many practical applications. However, due to its computation-intensive nature, current implementation of the transform falls short of meeting real-time processing requirements of most application. The objectives of this paper are implement the Haar and Daubechies wavelets using FPGA technology. In addition, the Bit Error Rate (BER) between the input audio signal and the reconstructed output signal for each wavelet is calculated. From the BER, it is seen that the implementations execute the operation of the wavelet transform correctly and satisfying the perfect reconstruction conditions. The design procedure has been explained and designed using the stat-ofart Electronic Design Automation (EDA) tools for system design on FPGA. Simulation, synthesis and implementation on the FPGA target technology has been carried out.

Keywords: Daubechies wavelet, discrete wavelet transform, Haar wavelet, Xilinx FPGA.

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Authors: Jyoti Chaturvedi Gursaran

Abstract:

Nature conducts its action in a very private manner. To reveal these actions classical science has done a great effort. But classical science can experiment only with the things that can be seen with eyes. Beyond the scope of classical science quantum science works very well. It is based on some postulates like qubit, superposition of two states, entanglement, measurement and evolution of states that are briefly described in the present paper. One of the applications of quantum computing i.e. implementation of a novel quantum evolutionary algorithm(QEA) to automate the time tabling problem of Dayalbagh Educational Institute (Deemed University) is also presented in this paper. Making a good timetable is a scheduling problem. It is NP-hard, multi-constrained, complex and a combinatorial optimization problem. The solution of this problem cannot be obtained in polynomial time. The QEA uses genetic operators on the Q-bit as well as updating operator of quantum gate which is introduced as a variation operator to converge toward better solutions.

Keywords: Quantum computing, qubit, superposition, entanglement, measurement of states, evolution of states, Scheduling problem, hard and soft constraints, evolutionary algorithm, quantum evolutionary algorithm.

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Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani

Abstract:

with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

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Authors: K. Assis, K. P. Chong, A. S. Idris, C. M. Ho

Abstract:

Oil palm or Elaeis guineensis is considered as the golden crop in Malaysia. But oil palm industry in this country is now facing with the most devastating disease called as Ganoderma Basal Stem Rot disease. The objective of this paper is to analyze the economic loss due to this disease. There were three commercial oil palm sites selected for collecting the required data for economic analysis. Yield parameter used to measure the loss was the total weight of fresh fruit bunch in six months. The predictors include disease severity, change in disease severity, number of infected neighbor palms, age of palm, planting generation, topography, and first order interaction variables. The estimation model of yield loss was identified by using backward elimination based regression method. Diagnostic checking was conducted on the residual of the best yield loss model. The value of mean absolute percentage error (MAPE) was used to measure the forecast performance of the model. The best yield loss model was then used to estimate the economic loss by using the current monthly price of fresh fruit bunch at mill gate.

Keywords: Ganoderma, oil palm, regression model, yield loss, economic loss.

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Authors: Mountassar Maamoun, Mehdi Neggazi, Abdelhamid Meraghni, Daoud Berkani

Abstract:

This paper presents a VLSI design approach of a highspeed and real-time 2-D Discrete Wavelet Transform computing. The proposed architecture, based on new and fast convolution approach, reduces the hardware complexity in addition to reduce the critical path to the multiplier delay. Furthermore, an advanced twodimensional (2-D) discrete wavelet transform (DWT) implementation, with an efficient memory area, is designed to produce one output in every clock cycle. As a result, a very highspeed is attained. The system is verified, using JPEG2000 coefficients filters, on Xilinx Virtex-II Field Programmable Gate Array (FPGA) device without accessing any external memory. The resulting computing rate is up to 270 M samples/s and the (9,7) 2-D wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out memory) with 256×256 image size. In this way, the developed design requests reduced memory and provide very high-speed processing as well as high PSNR quality.

Keywords: Discrete Wavelet Transform (DWT), Fast Convolution, FPGA, VLSI.

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Authors: Gizem Kodak

Abstract:

The Strait of Çanakkale (Dardanelles), together with the Strait of Istanbul and the Sea of Marmara, form the Turkish Straits System. In other words, the Strait of Çanakkale is the southern gate of the system that connects the Black Sea countries with the other countries of the world. Due to the heavy maritime traffic, it is important to scientifically examine the accident characteristics in the region. In particular, the results indicated by the descriptive statistics are of critical importance in order to strengthen the safety of navigation. At this point, exploratory data analysis offers strategic outputs in terms of defining the problem and knowing the strengths and weaknesses against possible accident risk. The study aims to determine the accident characteristics in the Strait of Çanakkale with temporal and spatial analysis of historical data, using Exploratory Data Analysis (EDA) as the research method. The study's results will reveal the general characteristics of maritime accidents in the region and form the infrastructure for future studies. Therefore, the text provides a clear description of the research goals and methodology, and the study's contributions are well-defined.

Keywords: Maritime Accidents, EDA, Strait of Çanakkale, navigational safety.

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Authors: Yin Runmin, Song Changfeng

Abstract:

Image-based Rendering(IBR) techniques recently reached in broad fields which leads to a critical challenge to build up IBR-Driven visualization platform where meets requirement of high performance, large bounds of distributed visualization resource aggregation and concentration, multiple operators deploying and CSCW design employing. This paper presents an unique IBR-based visualization dataflow model refer to specific characters of IBR techniques and then discusses prominent feature of IBR-Driven distributed collaborative visualization (DCV) system before finally proposing an novel prototype. The prototype provides a well-defined three level modules especially work as Central Visualization Server, Local Proxy Server and Visualization Aid Environment, by which data and control for collaboration move through them followed the previous dataflow model. With aid of this triple hierarchy architecture of that, IBR oriented application construction turns to be easy. The employed augmented collaboration strategy not only achieve convenient multiple users synchronous control and stable processing management, but also is extendable and scalable.

Keywords: Image-Based Rendering, Distributed CollaborativeVisualization, Computer Supported Cooperative Work, Model andSimulation, Modular Visualization Environment.

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Authors: Shuen-Tai Wang, Ying-Chuan Chen, Yu-Ching Lin

Abstract:

There has been renewal of interest in the relation between Green IT and cloud computing in recent years. Cloud computing has to be a highly elastic environment which provides stable services to users. The growing use of cloud computing facilities has caused marked energy consumption, putting negative pressure on electricity cost of computing center or data center. Each year more and more network devices, storages and computers are purchased and put to use, but it is not just the number of computers that is driving energy consumption upward. We could foresee that the power consumption of cloud computing facilities will double, triple, or even more in the next decade. This paper aims at resource allocation and scheduling technologies that are short of or have not well developed yet to reduce energy utilization in cloud computing platform. In particular, our approach relies on recalling services dynamically onto appropriate amount of the machines according to user’s requirement and temporarily shutting down the machines after finish in order to conserve energy. We present initial work on integration of resource and power management system that focuses on reducing power consumption such that they suffice for meeting the minimizing quality of service required by the cloud computing platform.

Keywords: Cloud computing, energy utilization, power consumption, resource allocation.

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Authors: Muhammad Azam, Micheal Olaolu Arowolo, Fei He, Mihail Popescu, Dong Xu

Abstract:

The number of biological papers is growing quickly, which means that the number of biological pathway figures in those papers is also increasing quickly. Each pathway figure shows extensive biological information, like the names of genes and how the genes are related. However, manually annotating pathway figures takes a lot of time and work. Even though using advanced image understanding models could speed up the process of curation, these models still need to be made more accurate. To improve gene name recognition from pathway figures, we applied a Siamese network to map image segments to a library of pictures containing known genes in a similar way to person recognition from photos in many photo applications. We used a triple loss function and a triplet spatial pyramid pooling network by combining the triplet convolution neural network and the spatial pyramid pooling (TSPP-Net). We compared VGG19 and VGG16 as the Siamese network model. VGG16 achieved better performance with an accuracy of 93%, which is much higher than Optical Character Recognition (OCR) results.

Keywords: Biological pathway, image understanding, gene name recognition, object detection, Siamese network, Visual Geometry Group.

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Authors: A.M. Vural, K.C. Bayindir

Abstract:

Back-to-back static synchronous compensator (BtBSTATCOM) consists of two back-to-back voltage-source converters (VSC) with a common DC link in a substation. This configuration extends the capabilities of conventional STATCOM that bidirectional active power transfer from one bus to another is possible. In this paper, VSCs are designed in quasi multi-pulse form in which GTOs are triggered only once per cycle in PSCAD/EMTDC. The design details of VSCs as well as gate switching circuits and controllers are fully represented. Regulation modes of BtBSTATCOM are verified and tested on a multi-machine power system through different simulation cases. The results presented in the form of typical time responses show that practical PI controllers are almost robust and stable in case of start-up, set-point change, and line faults.

Keywords: Flexible AC Transmission Systems (FACTS), Backto-Back Static Synchronous Compensator (BtB-STATCOM), quasi multi-pulse voltage source converter, active power transfer; voltage control.

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Authors: F. Djaafar, B. Hadri, G. Bachir

Abstract:

This paper presents the design parameters for a thin film 3J InGaP/GaAs/Ge solar cell with a simulated maximum efficiency of 32.11% using Tcad Silvaco. Design parameters include the doping concentration, molar fraction, layers’ thickness and tunnel junction characteristics. An initial dual junction InGaP/GaAs model of a previous published heterojunction cell was simulated in Tcad Silvaco to accurately predict solar cell performance. To improve the solar cell’s performance, we have fixed meshing, material properties, models and numerical methods. However, thickness and layer doping concentration were taken as variables. We, first simulate the InGaP\GaAs dual junction cell by changing the doping concentrations and thicknesses which showed an increase in efficiency. Next, a triple junction InGaP/GaAs/Ge cell was modeled by adding a Ge layer to the previous dual junction InGaP/GaAs model with an InGaP /GaAs tunnel junction.

Keywords: Heterojunction, modeling, simulation, thin film, Tcad Silvaco.

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Authors: B. R. Madushan, S. B. Navaratne, I. Wickramasinghe

Abstract:

Toddy sediment (TS) was cultured in a PDA medium to determine initial yeast load, and also it was undergone sun, shade, solar, dehumidified cold air (DCA) and hot air oven (at 400, 500 and 60oC) drying with a view to preserve viability of yeast. Thereafter, this study was conducted according to two factor factorial design in order to determine best preservation method. Therein the dried TS from the best drying method was taken and divided into two portions. One portion was mixed with 3: 7 ratio of TS: rice flour and the mixture was divided in to two again. While one portion was kept under in house condition the other was in a refrigerator. Same procedure was followed to the rest portion of TS too but it was at the same ratio of corn flour. All treatments were vacuum packed in triple laminate pouches and the best preservation method was determined in terms of leavening index (LI). The TS obtained from the best preservation method was used to make foods (bread and hopper) and organoleptic properties of it were evaluated against same of ordinary foods using sensory panel with a five point hedonic scale. Results revealed that yeast load or fresh TS was 58×106 CFU/g. The best drying method in preserving viability of yeast was DCA because LI of this treatment (96%) is higher than that of other three treatments. Organoleptic properties of foods prepared from best preservation method are as same as ordinary foods according to Duo trio test.

Keywords: Biological leavening agent, coconut toddy, fermentation, yeast.

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Authors: L. B. Gboeloh, K. Elele

Abstract:

Gastrointestinal parasitic infections are common health problems in sub-Saharan Africa. A cross- sectional study was carried out to determine the prevalence of gastrointestinal parasites among workers in major abattoirs in Port Harcourt, Nigeria. These abattoirs are located in Trans-Amadi, Rumuodumaya, Mile III and Easter-by-Pass. Formol-ether concentration technique was used to isolate the ova and cysts from faecal samples. Out of 201 workers (herdsmen, butchers, and cleaners) investigated for the presence of these parasites, 89 (44.2%) were infected with one or more parasites. The prevalence of the parasites among herdsmen and cleaners was significantly (P<0.05) higher. However, there was no significant (P>0.05) difference in the prevalence of gastrointestinal parasites in relation to age. Parasites identified included Ascaris lumbricoide (33.3%), tapeworm (4.97%), Entamoeba histolytica (5.47%), hookworms (13.9%), Trichuris trichiura (9.95%), Gardia lamblia (3.48%), and Schistosoma mansoni (1.9%). The frequency of A. lumbricoide was significantly (P<0.05) higher than other parasites. Many workers (65.2%) had single infection than double (23.6%) and triple infection (11.2%). Sanitary improvements, increased level of personal hygiene, routine surveillance by public health practitioners and veterinary experts as well as hygienic operation using modern technologies to process meat at these abattoirs will go a long way to control occupational gastrointestinal parasites among workers.

Keywords: Abattoirs, Gastrointestinal parasites, Port Harcourt, Workers.

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Authors: S. Raja Ratna, R. Ravi

Abstract:

Securing the confidential data transferred via wireless network remains a challenging problem. It is paramount to ensure that data are accessible only by the legitimate users rather than by the attackers. One of the most serious threats to organization is jamming, which disrupts the communication between any two pairs of nodes. Therefore, designing an attack-defending scheme without any packet loss in data transmission is an important challenge. In this paper, Dependence based Malicious Route Defending DMRD Scheme has been proposed in multi path routing environment to prevent jamming attack. The key idea is to defend the malicious route to ensure perspicuous transmission. This scheme develops a two layered architecture and it operates in two different steps. In the first step, possible routes are captured and their agent dependence values are marked using triple agents. In the second step, the dependence values are compared by performing comparator filtering to detect malicious route as well as to identify a reliable route for secured data transmission. By simulation studies, it is observed that the proposed scheme significantly identifies malicious route by attaining lower delay time and route discovery time; it also achieves higher throughput.

Keywords: Attacker, Dependence, Jamming, Malicious.

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Authors: Shanmuka Naga Raju

Abstract:

This paper  presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.

Keywords: Photovoltaic, PV, pulse width modulation, PWM, perturb and observe, phase locked loop.

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Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

Abstract:

In the current scenario, with the increasing integration densities, most system-on-chip designs are partitioned into multiple clock domains. In this paper, an asynchronous FIFO (First-in First-out pipeline) design is employed as a data transfer interface between two independent clock domains. Since the clocks on the either sides of the FIFO run at a different speed, the task to ensure the correct data transmission through this FIFO is manually performed. Firstly an existing asynchronous FIFO design is discussed and simulated. Gate-level simulation results depicted the flaw in existing design. In order to solve this problem, a novel modified asynchronous FIFO design is proposed. The results obtained from proposed design are in perfect accordance with theoretical expectations. The proposed asynchronous FIFO design outperforms the existing design in terms of accuracy and speed. In order to evaluate the performance of the FIFO designs presented in this paper, the circuits were implemented in 0.24µ TSMC CMOS technology and simulated at 2.5V using HSpice (© Avant! Corporation). The layout design of the proposed FIFO is also presented.

Keywords: Asynchronous, Clock, CMOS, C-element, FIFO, Globally Asynchronous Locally Synchronous (GALS), HSpice.

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Authors: H. Arabi, A.R. Kamali Asl

Abstract:

The purpose of this work is measurement of the system presampling MTF of a variable resolution x-ray (VRX) CT scanner. In this paper, we used the parameters of an actual VRX CT scanner for simulation and study of effect of different focal spot sizes on system presampling MTF by Monte Carlo method (GATE simulation software). Focal spot size of 0.6 mm limited the spatial resolution of the system to 5.5 cy/mm at incident angles of below 17º for cell#1. By focal spot size of 0.3 mm the spatial resolution increased up to 11 cy/mm and the limiting effect of focal spot size appeared at incident angles of below 9º. The focal spot size of 0.3 mm could improve the spatial resolution to some extent but because of magnification non-uniformity, there is a 10 cy/mm difference between spatial resolution of cell#1 and cell#256. The focal spot size of 0.1 mm acted as an ideal point source for this system. The spatial resolution increased to more than 35 cy/mm and at all incident angles the spatial resolution was a function of incident angle. By the way focal spot size of 0.1 mm minimized the effect of magnification nonuniformity.

Keywords: Focal spot, Spatial resolution, Monte Carlosimulation, Variable resolution x-ray (VRX) CT.

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Authors: M. Mohammadi

Abstract:

In order to evaluate the effect of phosphate and Zn bio-fertilizers on the yield, phytic acid (PA), Zn concentration and PA/Zn molar ratio in bean, a field experiment was carried out for two years. The treatments included two cultivars of bean (Talash and Sadri), four levels of P (P₀, P₁: 100 kg ha^-1 triple super phosphate (TSP), P2: 50 kg ha^-1 TSP + phosphate bio-fertilizer, P₃: phosphate bio-fertilizer), three levels of Zn (Zn₀, Zn₁: 50 kg ha^-1 ZnSO4, Zn₂: Zn bio-fertilizer). Phosphate bio-fertilizer consisted of inoculum of mycorrhizal fungus and Azotobacter and Zn bio-fertilizer consisted of Pseudomonas bacteria. The results revealed that there was significant difference between yield and Zn concentration between years. The effect of cultivar was significant on studied parameters. The lowest content of PA and PA/Zn were obtained from Talash. P treatment caused to significant difference on parameters in which P₂ caused to increase yield, P and Zn concentration, and decrease PA and PA/Zn by 21.8%, 38.2%, 33.4%, 17.4% and 38.6% respectively. Zn treatment caused to significant difference on studied parameters. The maximum number of parameters were obtained from Zn₁ and Zn₂. The higher Zn concentration led to lower content of PA and PA/Zn. Using of P and Zn bio–fertilizers were caused to increasing nutrient uptake, improving growth condition and reducing PA and PA/Zn molar ratio.

Keywords: Mycorrhizae, phosphorus, pseudomonas, zinc.

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Authors: P. Subha Karuvelam, M. Rajaram

Abstract:

Brushless DC motors (BLDC) are widely used in industrial areas. The BLDC motors are driven either by indirect ACAC converters or by direct AC-AC converters. Direct AC-AC converters i.e. matrix converters are used in this paper to drive the three phase BLDC motor and it eliminates the bulky DC link energy storage element. A matrix converter converts the AC power supply to an AC voltage of variable amplitude and variable frequency. A control technique is designed to generate the switching pulses for the three phase matrix converter. For the control of speed of the BLDC motor a separate PI controller and Fuzzy Logic Controller (FLC) are designed and a hysteresis current controller is also designed for the control of motor torque. The control schemes are designed and tested separately. The simulation results of both the schemes are compared and contrasted in this paper. The results show that the fuzzy logic control scheme outperforms the PI control scheme in terms of dynamic performance of the BLDC motor. Simulation results are validated with the experimental results.

Keywords: Fuzzy logic controller, matrix converter, permanent magnet brushless DC motor, PI controller.

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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Authors: Syed Manzoor Qasim, Shuja Abbasi, Saleh Alshebeili, Bandar Almashary, Ateeq Ahmad Khan

Abstract:

Higher-order Statistics (HOS), also known as cumulants, cross moments and their frequency domain counterparts, known as poly spectra have emerged as a powerful signal processing tool for the synthesis and analysis of signals and systems. Algorithms used for the computation of cross moments are computationally intensive and require high computational speed for real-time applications. For efficiency and high speed, it is often advantageous to realize computation intensive algorithms in hardware. A promising solution that combines high flexibility together with the speed of a traditional hardware is Field Programmable Gate Array (FPGA). In this paper, we present FPGA-based parallel architecture for the computation of third-order cross moments. The proposed design is coded in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and functionally verified by implementing it on Xilinx Spartan-3 XC3S2000FG900-4 FPGA. Implementation results are presented and it shows that the proposed design can operate at a maximum frequency of 86.618 MHz.

Keywords: Cross moments, Cumulants, FPGA, Hardware Implementation.

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Authors: Muhamad Nugraha

Abstract:

Economic growth always correlate positively with the magnitude of the unemployment rate. This is caused by labor which one of important variable to keep growth in the real sector of the region. Meanwhile, the economic structure in districts of Jember showed an increase of economic activity began to shift towards the industrial sector and some other economic sectors, so they have an affects to considerations for policy makers to increase economic growth in Jember as an autonomous region in East Java Province. At the fact, SMEs is among the factors driving economic growth in the region. This is shown by the high amount of SMEs. However, employment in the sector grew slightly slowed. It is caused by a lack of productivity in SMEs. Through the analysis of the transformation of economic structure theory, and the theory of Triple Helix using descriptive analytical method Location Quotient and Shift - Share, found that the results of the economic structure in Jember slowly shifting from the agricultural sector to the industrial sector, because it is dominated by trade sector, hotel and restaurant sector. In addition, SMEs is the potential sector of economic growth in Jember. While to maximizing role and functions of the institution's Research and Development Center of SMEs, there are three points to be known, that are Business Landscape, Business Architecture and Value Added.

Keywords: Economic Growth, SMEs, Labor, Research and Development Center of SMEs.

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Authors: M. Boulakroune, M. Challal, H. Louazene, S. Fentiz

Abstract:

This paper presents two types of microstrip bandpass filter (BPF) at microwave frequencies. The first one is a tunable BPF using planar patch resonators based on a varactor diode. The filter is formed by a triple mode circular patch resonator with two pairs of slots, in which the varactor diodes are connected. Indeed, this filter is initially centered at 2.4 GHz; the center frequency of the tunable patch filter could be tuned up to 1.8 GHz simultaneously with the bandwidth, reaching high tuning ranges. Lossless simulations were compared to those considering the substrate dielectric, conductor losses and the equivalent electrical circuit model of the tuning element in order to assess their effects. Within these variations, simulation results showed insertion loss better than 2 dB and return loss better than 10 dB over the passband. The second structure is a BPF for ultra-wideband (UWB) applications based on multiple-mode resonator (MMR) and rectangular-shaped defected ground structure (DGS). This filter, which is compact size of 25.2 x 3.8 mm2, provides in the pass band an insertion loss of 0.57 dB and a return loss greater than 12 dB. The proposed filters presents good performances and the simulation results are in satisfactory agreement with the experimentation ones reported elsewhere.

Keywords: Defected ground structure, varactor diode, microstrip bandpass filter, multiple-mode resonator.

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