Search results for: Cascaded%20H-Bridge%20multilevel%20inverter

Authors: Inderpreet Kaur, Neena Gupta

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Wavelength multiplexing (WDM) technology along with optical amplifiers is used for optical communication systems in S-band, C-band and L-band. To improve the overall system performance Hybrid amplifiers consisting of cascaded TDFA and EDFA with different gain bandwidths are preferred for long haul wavelength multiplexed optical communication systems. This paper deals with statistical analysis of different configuration of hybrid amplifier i.e. analysis of TDFA-EDFA configuration and EDFA – TDFA configuration. In this paper One-Way ANOVA method is used for statistical analysis.

Keywords: WDM, EDFA, TDFA, hybrid amplifier, One-wayANOVA.

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Authors: M. Jagabar Sathik, K. Ramani

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In this paper family of multilevel inverter topology with reduced number of power switches is presented. The proposed inverter can generate both even and odd level. The proposed topology is suitable for symmetric structure. The proposed symmetric inverter results in reduction of power switches, power diode and gate driver circuits and also it may further minimize the installation area and cost. To prove the superiority of proposed topology is compared with conventional topologies. The performance of this symmetric multilevel inverter has been tested by computer based simulation and prototype based experimental setup for nine-level inverter is developed and results are verified.

Keywords: Cascaded H- Bridge (CHB), Multilevel Inverter (MLI), Nearest Level Modulation (NLM), Total Harmonic Distortion (THD).

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Authors: Supayotin Na Songkla, Winai Jaikla

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This article presents a resistorless current-mode firstorder allpass filter based on second generation current controlled current conveyors (CCCIIs). The features of the circuit are that: the pole frequency can be electronically controlled via the input bias current: the circuit description is very simple, consisting of 2 CCCIIs and single grounded capacitor, without any external resistors and component matching requirements. Consequently, the proposed circuit is very appropriate to further develop into an integrated circuit. Low input and high output impedances of the proposed configuration enable the circuit to be cascaded in current-mode without additional current buffers. The PSpice simulation results are depicted. The given results agree well with the theoretical anticipation. The application example as a current-mode quadrature oscillator is included.

Keywords: First-order all pass filter, current-mode, CCCII.

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Authors: Bhausaheb L. Pangarkar, Saroj B. Parjane, M.G. Sane

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In India, the quarrel between the budding human populace and the planet-s unchanging supply of freshwater and falling water tables has strained attention the reuse of gray water as an alternative water resource in rural development. This paper present the finest design of laboratory scale gray water treatment plant, which is a combination of natural and physical operations such as primary settling with cascaded water flow, aeration, agitation and filtration, hence called as hybrid treatment process. The economical performance of the plant for treatment of bathrooms, basins and laundries gray water showed in terms of deduction competency of water pollutants such as COD (83%), TDS (70%), TSS (83%), total hardness (50%), oil and grease (97%), anions (46%) and cations (49%). Hence, this technology could be a good alternative to treat gray water in residential rural area.

Keywords: Gray water treatment plant, gray water, naturaltechnology, pollutant.

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Authors: Juyoung Kim, Taegeun Park

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In this paper, we propose a fully-utilized, block-based 2D DWT (discrete wavelet transform) architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively. Furthermore, the proposed 2D DWT processes in horizontal and vertical directions simultaneously without an idle period, so that it computes the DWT for an N×N image in a period of N2(1-2-2J)/3. Compared to the existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rates. To mitigate the long critical path delay due to the cascaded lattices, we can apply the pipeline technique with four stages, while retaining 100% of hardware utilization. The proposed architecture can be applied in real-time video signal processing.

Keywords: discrete wavelet transform, VLSI architecture, QMF lattice filter, pipelining.

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Authors: Hassan Ghasemzadeh, Sepideh Mazrouee, Hassan Goldani Moghaddam, Hamid Shojaei, Mohammad Reza Kakoee

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Block replacement algorithms to increase hit ratio have been extensively used in cache memory management. Among basic replacement schemes, LRU and FIFO have been shown to be effective replacement algorithms in terms of hit rates. In this paper, we introduce a flexible stack-based circuit which can be employed in hardware implementation of both LRU and FIFO policies. We propose a simple and efficient architecture such that stack-based replacement algorithms can be implemented without the drawbacks of the traditional architectures. The stack is modular and hence, a set of stack rows can be cascaded depending on the number of blocks in each cache set. Our circuit can be implemented in conjunction with the cache controller and static/dynamic memories to form a cache system. Experimental results exhibit that our proposed circuit provides an average value of 26% improvement in storage bits and its maximum operating frequency is increased by a factor of two

Keywords: Cache Memory, Replacement Algorithms, LeastRecently Used Algorithm, First In First Out Algorithm.

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Authors: Hassan Jassim Motlak

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A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: Pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA.

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Authors: M. Mohamed, X. Zhang, K. Wu, M. Elfituri, A. Legnain

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Performance of millimeter-wave (mm-wave) multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) signal generation using frequency quadrupling technique and transmission over fiber is experimentally investigated. The frequency quadrupling is achived by using only one Mach- Zehnder modulator (MZM) that is biased at maximum transmission (MATB) point. At the output, a frequency quadrupling signal is obtained then sent to a second MZM. This MZM is used for MBOFDM UWB signal modulation. In this work, we demonstrate 30- GHz mm-wave wireless that carries three-bands OFDM UWB signals, and error vector magnitude (EVM) is used to analyze the transmission quality. It is found that our proposed technique leads to an improvement of 3.5 dB in EVM at 40% of local oscillator (LO) modulation with comparison to the technique using two cascaded MZMs biased at minimum transmission (MITB) point.

Keywords: Optical communication, Frequency up-conversion, Mach-Zehnder modulator, millimeter wave generation, radio over fiber

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Authors: S. Zouari, H. Daoud, M. Loulou, P. Loumeau, N. Masmoudi

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A wideband 2-1-1 cascaded ΣΔ modulator with a single-bit quantizer in the two first stages and a 4-bit quantizer in the final stage is developed. To reduce sensitivity of digital-to-analog converter (DAC) nonlinearities in the feedback of the last stage, dynamic element matching (DEM) is introduced. This paper presents two modelling approaches: The first is MATLAB description and the second is VHDL-AMS modelling of the proposed architecture and exposes some high-level-simulation results allowing a behavioural study. The detail of both ideal and non-ideal behaviour modelling are presented. Then, the study of the effect of building blocks nonidealities is presented; especially the influences of nonlinearity, finite operational amplifier gain, amplifier slew rate limitation and capacitor mismatch. A VHDL-AMS description presents a good solution to predict system-s performances and can provide sensitivity curves giving the impact of nonidealities on the system performance.

Keywords: behavioural study, DAC nonlinearity, DEM, ΣΔ modulator, VHDL-AMS modelling.

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Authors: Mazidah Tajjudin, Mohd Hezri Fazalul Rahiman, Norhashim Mohd Arshad, Ramli Adnan

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In process control applications, above 90% of the controllers are of PID type. This paper proposed a robust PI controller with fractional-order integrator. The PI parameters were obtained using classical Ziegler-Nichols rules but enhanced with the application of error filter cascaded to the fractional-order PI. The controller was applied on steam temperature process that was described by FOPDT transfer function. The process can be classified as lag dominating process with very small relative dead-time. The proposed control scheme was compared with other PI controller tuned using Ziegler-Nichols and AMIGO rules. Other PI controller with fractional-order integrator known as F-MIGO was also considered. All the controllers were subjected to set point change and load disturbance tests. The performance was measured using Integral of Squared Error (ISE) and Integral of Control Signal (ICO). The proposed controller produced best performance for all the tests with the least ISE index.

Keywords: PID controller, fractional-order PID controller, PI control tuning, steam temperature control, Ziegler-Nichols tuning.

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Authors: N. Ben Ameur, M. Loulou

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This paper study the high-level modelling and design of delta-sigma (ΔΣ) noise shapers for audio Digital-to-Analog Converter (DAC) so as to eliminate the in-band Signal-to-Noise- Ratio (SNR) degradation that accompany one channel mismatch in audio signal. The converter combines a cascaded digital signal interpolation, a noise-shaping single loop delta-sigma modulator with a 5-bit quantizer resolution in the final stage. To reduce sensitivity of Digital-to-Analog Converter (DAC) nonlinearities of the last stage, a high pass second order Data Weighted Averaging (R2DWA) is introduced. This paper presents a MATLAB description modelling approach of the proposed DAC architecture with low distortion and swing suppression integrator designs. The ΔΣ Modulator design can be configured as a 3rd-order and allows 24-bit PCM at sampling rate of 64 kHz for Digital Video Disc (DVD) audio application. The modeling approach provides 139.38 dB of dynamic range for a 32 kHz signal band at -1.6 dBFS input signal level.

Keywords: DVD-audio, DAC, Interpolator and Interpolation Filter, Single-Loop ΔΣ Modulation, R2DWA, Clock Jitter

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Authors: K.Sedhuraman, S.Himavathi, A.Muthuramalingam

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The performance of sensor-less controlled induction motor drive depends on the accuracy of the estimated speed. Conventional estimation techniques being mathematically complex require more execution time resulting in poor dynamic response. The nonlinear mapping capability and powerful learning algorithms of neural network provides a promising alternative for on-line speed estimation. The on-line speed estimator requires the NN model to be accurate, simpler in design, structurally compact and computationally less complex to ensure faster execution and effective control in real time implementation. This in turn to a large extent depends on the type of Neural Architecture. This paper investigates three types of neural architectures for on-line speed estimation and their performance is compared in terms of accuracy, structural compactness, computational complexity and execution time. The suitable neural architecture for on-line speed estimation is identified and the promising results obtained are presented.

Keywords: Sensorless IM drives, rotor speed estimators, artificial neural network, feed- forward architecture, single neuron cascaded architecture.

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Authors: Lokesh Tharani, R.P.Yadav

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This paper presents the results related to the interference reduction technique in multistage multiuser detector for asynchronous DS-CDMA system. To meet the real-time requirements for asynchronous multiuser detection, a bit streaming, cascade architecture is used. An asynchronous multiuser detection involves block-based computations and matrix inversions. The paper covers iterative-based suboptimal schemes that have been studied to decrease the computational complexity, eliminate the need for matrix inversions, decreases the execution time, reduces the memory requirements and uses joint estimation and detection process that gives better performance than the independent parameter estimation method. The stages of the iteration use cascaded and bits processed in a streaming fashion. The simulation has been carried out for asynchronous DS-CDMA system by varying one parameter, i.e., number of users. The simulation result exhibits that system gives optimum bit error rate (BER) at 3rd stage for 15-users.

Keywords: Multi-user detection (MUD), multiple accessinterference (MAI), near-far effect, decision feedback detector, successive interference cancellation detector (SIC) and parallelinterference cancellation (PIC) detector.

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Authors: Vishal Awasthi, Krishna Raj

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Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.

Keywords: Sampling rate conversion, Multirate Filtering, Compensation Theory, Decimation filter, CIC filter, Redundant signed digit arithmetic, Fast adders.

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Authors: Sanghoon Kim, Sun-Tae Chung, Souhwan Jung, Seoungseon Jeon, Jaemin Kim, Seongwon Cho

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In this paper, we propose a face recognition algorithm using AAM and Gabor features. Gabor feature vectors which are well known to be robust with respect to small variations of shape, scaling, rotation, distortion, illumination and poses in images are popularly employed for feature vectors for many object detection and recognition algorithms. EBGM, which is prominent among face recognition algorithms employing Gabor feature vectors, requires localization of facial feature points where Gabor feature vectors are extracted. However, localization method employed in EBGM is based on Gabor jet similarity and is sensitive to initial values. Wrong localization of facial feature points affects face recognition rate. AAM is known to be successfully applied to localization of facial feature points. In this paper, we devise a facial feature point localization method which first roughly estimate facial feature points using AAM and refine facial feature points using Gabor jet similarity-based facial feature localization method with initial points set by the rough facial feature points obtained from AAM, and propose a face recognition algorithm using the devised localization method for facial feature localization and Gabor feature vectors. It is observed through experiments that such a cascaded localization method based on both AAM and Gabor jet similarity is more robust than the localization method based on only Gabor jet similarity. Also, it is shown that the proposed face recognition algorithm using this devised localization method and Gabor feature vectors performs better than the conventional face recognition algorithm using Gabor jet similarity-based localization method and Gabor feature vectors like EBGM.

Keywords: Face Recognition, AAM, Gabor features, EBGM.

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Authors: R. Kamalakannan, N. Ravi Kumar

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The global energy consumption is increasing persistently and need for distributed power generation through renewable energy is essential. To meet the power requirements for consumers without any voltage fluctuations and losses, modeling and design of multilevel inverter with Flexible AC Transmission System (FACTS) capability is presented. The presented inverter is provided with 13-level cascaded H-bridge topology of Insulated Gate Bipolar Transistor (IGBTs) connected along with inbuilt Distributed Static Synchronous Compensators (DSTATCOM). The DSTATCOM device provides control of power factor stability at local feeder lines and the inverter eliminates Total Harmonic Distortion (THD). The 13-level inverter utilizes 52 switches of each H-bridge is fed with single DC sources separately and the Pulse Width Modulation (PWM) technique is used for switching IGBTs. The control strategy implemented for inverter transmits active power to grid as well as it maintains power factor to be stable with achievement of steady state power transmission. Significant outcome of this project is improvement of output voltage quality with steady state power transmission with low THD. Simulation of inverter with DSTATCOM is performed using MATLAB/Simulink environment. The scaled prototype model of proposed inverter is built and its results were validated with simulated results.

Keywords: FACTS devices, distributed-Static synchronous compensators, DSTATCOM, total harmonics elimination, modular multilevel converter.

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Authors: Hailu Dessalegn, T. Srinivas

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We propose new multiple-channel piezoelectric (PZT) actuated tunable optical filter based on racetrack multi-ring resonators for wavelength de-multiplexing network applications. We design tunable eight-channel wavelength de-multiplexer consisting of eight cascaded PZT actuated tunable multi-ring resonator filter with a channel spacing of 1.6nm. The filter for each channel is basically structured on a suspended beam, sandwiched with piezoelectric material and built in integrated ring resonators which are placed on the middle of the beam to gain uniform stress and linearly varying longitudinal strain. A reference single mode serially coupled multi stage racetrack ring resonator with the same radii and coupling length is designed with a line width of 0.8974nm with a flat top pass band at 1dB of 0.5205nm and free spectral range of about 14.9nm. In each channel, a small change in the perimeter of the rings is introduced to establish the shift in resonance wavelength as per the defined channel spacing. As a result, when a DC voltage is applied, the beams will elongate, which involves mechanical deformation of the ring resonators that induces a stress and a strain, which brings a change in refractive index and perimeter of the rings leading to change in the output spectrum shift providing the tunability of central wavelength in each channel. Simultaneous wave length shift as high as 45.54pm/

Keywords: Optical MEMS, piezoelectric (PZT) actuation, tunable optical filter, wavelength de-multiplexer.

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Authors: M. Suresh Kumar, K. Ramani

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This paper proposed the comparison made between Multi-Carrier Pulse Width Modulation, Sinusoidal Pulse Width Modulation and Selective Harmonic Elimination Pulse Width Modulation technique for minimization of Total Harmonic Distortion in Cascaded H-Bridge Multi-Level Inverter. In Multicarrier Pulse Width Modulation method by using Alternate Position of Disposition scheme for switching pulse generation to Multi-Level Inverter. Another carrier based approach; Sinusoidal Pulse Width Modulation method is also implemented to define the switching pulse generation system in the multi-level inverter. In Selective Harmonic Elimination method using Genetic Algorithm and Particle Swarm Optimization algorithm for define the required switching angles to eliminate low order harmonics from the inverter output voltage waveform and reduce the total harmonic distortion value. So, the results validate that the Selective Harmonic Elimination Pulse Width Modulation method does capably eliminate a great number of precise harmonics and minimize the Total Harmonic Distortion value in output voltage waveform in compared with Multi-Carrier Pulse Width Modulation method, Sinusoidal Pulse Width Modulation method. In this paper, comparison of simulation results shows that the Selective Harmonic Elimination method can attain optimal harmonic minimization solution better than Multi-Carrier Pulse Width Modulation method, Sinusoidal Pulse Width Modulation method.

Keywords: Multi-level inverter, Selective Harmonic Elimination Pulse Width Modulation, Multi-Carrier Pulse Width Modulation, Total Harmonic Distortion, Genetic Algorithm.

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Authors: Vikram Jeganathan, A. V. Sai Balasubramanian, N. Ravi Shankar, S. Subbaraman, R. Rengaraj

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Heating systems are a necessity for regions which brace extreme cold weather throughout the year. To maintain a comfortable temperature inside a given place, heating systems making use of- Hydronic boilers- are used. The principle of a single pipe system serves as a base for their working. It is mandatory for these heating systems to control the room temperature, thus maintaining a warm environment. In this paper, the concept of regulation of the room temperature over a wide range is established by using an Adaptive Fuzzy Controller (AFC). This fuzzy controller automatically detects the changes in the outside temperatures and correspondingly maintains the inside temperature to a palatial value. Two separate AFC's are put to use to carry out this function: one to determine the quantity of heat needed to reach the prospective temperature required and to set the desired temperature; the other to control the position of the valve, which is directly proportional to the error between the present room temperature and the user desired temperature. The fuzzy logic controls the position of the valve as per the requirement of the heat. The amount by which the valve opens or closes is controlled by 5 knob positions, which vary from minimum to maximum, thereby regulating the amount of heat flowing through the valve. For the given test system data, different de-fuzzifier methods have been implemented and the results are compared. In order to validate the effectiveness of the proposed approach, a fuzzy controller has been designed by obtaining a test data from a real time system. The simulations are performed in MATLAB and are verified with standard system data. The proposed approach can be implemented for real time applications.

Keywords: Adaptive fuzzy controller, Hydronic heating system

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Authors: O. S. Ebrahim, K. O. Shawky, M. A. Badr, P. K. Jain

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This paper describes an efficient; low-cost; high-availability; induction motor (IM) drive system with intelligent supervisory control for water distribution networks including storage tank. To increase the operational efficiency and reduce cost, the IM drive system includes main pumping unit and an auxiliary voltage source inverter (VSI) fed unit. The main unit comprises smart star/delta starter, regenerative fluid clutch, switched VAR compensator, and hysteresis liquid-level controller. Three-state energy saving mode (ESM) is defined at no-load and a logic algorithm is developed for best energetic cost reduction. To reduce voltage sag, the supervisory controller operates the switched VAR compensator upon motor starting. To provide smart star/delta starter at low cost, a method based on current sensing is developed for interlocking, malfunction detection, and life–cycles counting and used to synthesize an improved fuzzy logic (FL) based availability assessment scheme. Furthermore, a recurrent neural network (RNN) full state estimator is proposed to provide sensor fault-tolerant algorithm for the feedback control. The auxiliary unit is working at low flow rates and improves the system efficiency and flexibility for distributed generation during islanding mode. Compared with doubly-fed IM, the proposed one ensures 30% working throughput under main motor/pump fault conditions, higher efficiency, and marginal cost difference. This is critically important in case of water networks. Theoretical analysis, computer simulations, cost study, as well as efficiency evaluation, using timely cascaded energy-conservative systems, are performed on IM experimental setup to demonstrate the validity and effectiveness of the proposed drive and control.

Keywords: Artificial Neural Network, ANN, Availability Assessment, Cloud Computing, Energy Saving, Induction Machine, IM, Supervisory Control, Fuzzy Logic, FL, Pumped Storage.

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