@article{(Open Science Index):https://publications.waset.org/pdf/5283,
	  title     = {High Order Cascade Multibit ΣΔ Modulator for Wide Bandwidth Applications},
	  author    = {S. Zouari and  H. Daoud and  M. Loulou and  P. Loumeau and  N. Masmoudi},
	  country	= {},
	  institution	= {},
	  abstract     = {A wideband 2-1-1 cascaded ΣΔ modulator with a
single-bit quantizer in the two first stages and a 4-bit quantizer in the
final stage is developed. To reduce sensitivity of digital-to-analog
converter (DAC) nonlinearities in the feedback of the last stage,
dynamic element matching (DEM) is introduced. This paper presents
two modelling approaches: The first is MATLAB description and the
second is VHDL-AMS modelling of the proposed architecture and
exposes some high-level-simulation results allowing a behavioural
study. The detail of both ideal and non-ideal behaviour modelling are
presented. Then, the study of the effect of building blocks
nonidealities is presented; especially the influences of nonlinearity,
finite operational amplifier gain, amplifier slew rate limitation and
capacitor mismatch. A VHDL-AMS description presents a good
solution to predict system-s performances and can provide sensitivity
curves giving the impact of nonidealities on the system performance.},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {1},
	  number    = {9},
	  year      = {2007},
	  pages     = {1337 - 1343},
	  ee        = {https://publications.waset.org/pdf/5283},
	  url   	= {https://publications.waset.org/vol/9},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 9, 2007},