S. Zouari and H. Daoud and M. Loulou and P. Loumeau and N. Masmoudi
High Order Cascade Multibit ΣΔ Modulator for Wide Bandwidth Applications
1337 - 1343
2007
1
9
International Journal of Electronics and Communication Engineering
https://publications.waset.org/pdf/5283
https://publications.waset.org/vol/9
World Academy of Science, Engineering and Technology
A wideband 211 cascaded ΣΔ modulator with a
singlebit quantizer in the two first stages and a 4bit quantizer in the
final stage is developed. To reduce sensitivity of digitaltoanalog
converter (DAC) nonlinearities in the feedback of the last stage,
dynamic element matching (DEM) is introduced. This paper presents
two modelling approaches The first is MATLAB description and the
second is VHDLAMS modelling of the proposed architecture and
exposes some highlevelsimulation results allowing a behavioural
study. The detail of both ideal and nonideal behaviour modelling are
presented. Then, the study of the effect of building blocks
nonidealities is presented; especially the influences of nonlinearity,
finite operational amplifier gain, amplifier slew rate limitation and
capacitor mismatch. A VHDLAMS description presents a good
solution to predict systems performances and can provide sensitivity
curves giving the impact of nonidealities on the system performance.
Open Science Index 9, 2007