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High Order Cascade Multibit ΣΔ Modulator for Wide Bandwidth Applications

Authors: M. Loulou, S. Zouari, H. Daoud, P. Loumeau, N. Masmoudi


A wideband 2-1-1 cascaded ΣΔ modulator with a single-bit quantizer in the two first stages and a 4-bit quantizer in the final stage is developed. To reduce sensitivity of digital-to-analog converter (DAC) nonlinearities in the feedback of the last stage, dynamic element matching (DEM) is introduced. This paper presents two modelling approaches: The first is MATLAB description and the second is VHDL-AMS modelling of the proposed architecture and exposes some high-level-simulation results allowing a behavioural study. The detail of both ideal and non-ideal behaviour modelling are presented. Then, the study of the effect of building blocks nonidealities is presented; especially the influences of nonlinearity, finite operational amplifier gain, amplifier slew rate limitation and capacitor mismatch. A VHDL-AMS description presents a good solution to predict system-s performances and can provide sensitivity curves giving the impact of nonidealities on the system performance.

Keywords: DEM, behavioural study, DAC nonlinearity, ΣΔ modulator, VHDL-AMS modelling

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