Search results for: reconfigurable architectures

Authors: Roukaya Dalbouchi, Abdelkrin Zitouni

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In this paper, we propose a novel design methodology for Dynamic Partial Reconfigurable (DPR) system. This type of system has the property of being able to be modified after its design and during its execution. The suggested design methodology is generic in terms of granularity, number of modules, and reconfigurable region and suitable for any type of modern application. It is based on the interconnection between several design stages. The recommended methodology represents a guide for the design of DPR architectures that meet compromise reconfiguration/performance. To validate the proposed methodology, we use as an application a video watermarking. The comparison result shows that the proposed methodology supports all stages of DPR architecture design and characterized by a high abstraction level. It provides a dynamic/partial reconfigurable architecture; it guarantees material efficiency, the flexibility of reconfiguration, and superior performance in terms of frequency and power consumption.

Keywords: dynamically reconfigurable system, block matching algorithm, partial reconfiguration, motion vectors, video watermarking

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Authors: M. A. Fodha, H. Benfradj, A. Ghazel

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This paper is a survey of recent works that proposes a baseband processor architecture for software defined radio. A classification of different approaches is proposed. The performance of each architecture is also discussed in order to clarify the suitable approaches that meet software-defined radio constraints.

Keywords: multi-core architectures, reconfigurable architectures, software defined radio, baseband processor

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Authors: Abbas Ebrahimi, Mohammad Zandsalimy

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The main purpose of this study is to investigate the feasibility of using FPGA (Field Programmable Gate Arrays) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the Laplace equation. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is an SoC (System on a Chip) FPGA type that integrates both microprocessor and FPGA architectures into a single device. In the present study the Laplace equation is implemented and solved numerically on both reconfigurable hardware and CPU. The precision of results and speedups of the calculations are compared together. The computational process on FPGA, is up to 20 times faster than a conventional CPU, with the same data precision. An analytical solution is used to validate the results.

Keywords: accelerating numerical solutions, CFD, FPGA, hardware definition language, numerical solutions, reconfigurable hardware

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Authors: Adhinarayanan Venkatasubramanian

Abstract:

For design of high speed digital circuit wave pipeline is the best approach this can be operated at higher operating frequencies by adjusting clock periods and skews so as latch the o/p of combinational logic circuit at the stable period. In this paper, there are two methods are proposed in automation task one is BIST (Built in self test) and second method is Reconfigurable technique. For the above two approaches dedicated AND gate (multiplier) by applying wave pipeline technique. BIST approach is implemented by Xilinx Spartan-II device. In reconfigurable technique done by ASIC. From the results, wave pipeline circuits are faster than nonpipeline circuit and area, power dissipation are reduced by reconfigurable technique.

Keywords: SOC, wave-pipelining, FPGA, self-testing, reconfigurable, ASIC

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Authors: D. Rama Krishna, Y. Pandu Rangaiah

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This paper presents the design of multiband reconfigurable antenna using PIN diodes for four iterations and all the four iterations have been validated by measuring return loss and pattern measurements of developed prototype antenna. The simulated and experimental data have demonstrated the concepts of a multiband reconfigurable antenna by switching OFF and ON of PIN diodes for multiple band frequencies. The technique has taken the advantage of a different number of radiating lengths with the use of PIN diode switches, each configuration resonating at multiband frequencies.

Keywords: frequency reconfigurable, meandered line multiband antenna, PIN diode, multiband frequencies

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Authors: M. Srilatha, R. Hemalatha, T. Sri Aditya

Abstract:

Communication of today world is dominated by wireless technology. This is mainly due to the revolutionary development of new wireless communication system generations. The evolving new generations of wireless systems are accommodating the demand through better resource management including improved transmission technologies with optimized communication devices. To keep up with the evolution of technologies, the communication systems must be designed to optimize transparent insertion of newly evolved technologies virtually at all stages of their life cycle. After the insertion of new technologies, the upgraded devices should continue the communication without squalor in quality. The concern of improving spectrum access and spectrum efficiency combined with both the introduction of Software Defined Radios (SDR) and the possibility of the software application to radios has led to an evolution of wireless radio research. The software defined radio term was coined in the 1970s to overcome the problems in the application of software to wireless radios which eliminates the requirement of hardware changes. SDR has become the prime theme of research since it eliminates the drawbacks associated with conventional wireless communication systems implementation. This paper identifies and discusses key enabling technologies and possibility of research and development in SDRs. In addition transmitter and receiver architectures of SDR are also discussed along with their feasibility for reconfigurable radio application.

Keywords: software defined radios, wireless communication, reconfigurable, reconfigurable transmitter, reconfigurable receivers, FPGA, DSP

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Authors: Mohsin Raza, Arne Bilberg, Thomas Ditlev Brunø, Ann-Louise Andersen, Filip SKärin

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Shifting from a dedicated or flexible manufacturing system to a reconfigurable manufacturing system (RMS) requires a significant amount of time, money, and effort. Therefore, it is vital to verify beforehand that the potential reconfigurable solution will be able to achieve the organizational objectives. Discrete event simulation offers the opportunity of assessing several reconfigurable alternatives against the set objectives. This study signifies the importance of using discrete-event simulation as a tool to verify several reconfiguration options. Two different industrial cases have been presented in the study to elaborate on the role of discrete event simulation in the implementation methodology of RMSs. The study concluded that discrete event simulation is one of the important tools to consider in the RMS implementation methodology.

Keywords: reconfigurable manufacturing system, discrete event simulation, Tecnomatix plant simulation, RMS

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

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This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: reconfigurable, fast Fourier transform (FFT), single-path delay feedback (SDF), 3GPP-LTE

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Authors: Manpreet Singh, V. P. Agrawal, Gurmanjot Singh Bhatti

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From the last decades, there is a significant technological advancement in the field of robotics, and a number of modular self-reconfigurable robots were introduced that can help in space exploration, bucket to stuff, search, and rescue operation during earthquake, etc. As there are numbers of self-reconfigurable robots, choosing the optimum one is always a concern for robot user since there is an increase in available features, facilities, complexity, etc. The objective of this research work is to present a multiple attribute decision making based methodology for coding, evaluation, comparison ranking and selection of modular self-reconfigurable robots using a technique for order preferences by similarity to ideal solution approach. However, 86 attributes that affect the structure and performance are identified. A database for modular self-reconfigurable robot on the basis of different pertinent attribute is generated. This database is very useful for the user, for selecting a robot that suits their operational needs. Two visual methods namely linear graph and spider chart are proposed for ranking of modular self-reconfigurable robots. Using five robots (Atron, Smores, Polybot, M-Tran 3, Superbot), an example is illustrated, and raking of the robots is successfully done, which shows that Smores is the best robot for the operational need illustrated, and this methodology is found to be very effective and simple to use.

Keywords: self-reconfigurable robots, MADM, TOPSIS, morphogenesis, scalability

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Authors: B. Kirubakaran, C. Rajasekaran

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Reconfigurable techniques are used in many engineering and industrial applications for the efficient data transmissions through the wireless sensor networks. Nowadays most of the industrial applications are work for try to minimize the size and cost. During runtime the reconfigurable technique avoid the unwanted hang and delay in the system performance. In recent world Field Programmable Gate Array (FPGA) as one of the most efficient reconfigurable device and widely used for most of the hardware and software reconfiguration applications. In this paper, the work deals with whatever going to make changes in the hardware and software during runtime it’s should not affect the current running process that’s the main objective of the paper our changes be done in a parallel manner at the same time concentrating the cost and power transmission problems during data trans-receiving. Analog sensor (Temperature) as an input for the controller (PIC) through that control the FPGA digital sensors in generalized manner.

Keywords: field programmable gate array, peripheral interrupt controller, runtime reconfigurable techniques, wireless sensor networks

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Authors: Akhilesh G. Naik, Dipankar Pal

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In today’s scenario, the complexity of digital signal processing (DSP) applications and various microcontroller architectures have been increasing to such an extent that the traditional approaches to multiplier design in most processors are becoming outdated for being comparatively slow. Modern processing applications require suitable pipelined approaches, and therefore, algorithms that are friendlier with pipelined architectures. Traditional algorithms like Wallace Tree, Radix-4 Booth, Radix-8 Booth, Dadda architectures have been proven to be comparatively slow for pipelined architectures. These architectures, therefore, need to be optimized or combined with other architectures amongst them to enhance its performances and to be made suitable for pipelined hardware/architectures. Recently, Vedic algorithm mathematically has proven to be efficient by appearing to be less complex and with fewer steps for its output establishment and have assumed renewed importance. This paper describes and shows how the Vedic algorithm can be better suited for pipelined architectures and also can be combined with traditional architectures and algorithms for enhancing its ability even further. In this paper, we also established that for complex applications on DSP and other microcontroller architectures, using Vedic approach for multiplication proves to be the best available and efficient option.

Keywords: Wallace Tree, Radix-4 Booth, Radix-8 Booth, Dadda, Vedic, Single-Stage Karatsuba (SSK), Looped Karatsuba (LK)

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Authors: Gaurav Upadhyay, Nand Kishore, Prashant Ranjan, V. S. Tripathi, Shivesh Tripathi

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A frequency reconfigurable multiband antenna for intelligent transportation system (ITS) applications is proposed in this paper. A PIN-diode is used for reconfigurability. Centre frequencies are 1.38, 1.98, 2.89, 3.86, and 4.34 GHz in “ON” state of Diode and 1.56, 2.16, 2.88, 3.91 and 4.45 GHz in “OFF” state. Achieved maximum bandwidth is 18%. The maximum gain of the proposed antenna is 2.7 dBi in “ON” state and 3.95 dBi in “OFF” state of the diode. The antenna is simulated, fabricated, and tested in the lab. Measured and simulated results are in good confirmation.

Keywords: ITS, multiband antenna, PIN-diode, reconfigurable

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Authors: Roscoe McLean, Jared Padayachee, Glen Bright

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There is currently a gap in the technology covering the rapid establishment of control after a reconfiguration in a Reconfigurable Manufacturing System. This gap involves the detection of the factory floor state and the communication link between the factory floor and the high-level software. In this paper, a thin, hardware-supported Middleware Management System (MMS) is proposed and its design and implementation are discussed. The research found that a cost-effective localization technique can be combined with intelligent software to speed up the ramp-up of a reconfigured system. The MMS makes the process more intelligent, more efficient and less time-consuming, thus supporting the industrial implementation of the RMS paradigm.

Keywords: intelligent systems, middleware, reconfigurable manufacturing, management system

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Authors: André Lages, Victor Dmitriev, Juliano Bazzo, Gianni Portela

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This work evaluates the feasibility of the graphene application to perform as a wideband reconfigurable material for lens antennas in 5G/6G and satellite applications. Based on transformation optics principles, the electromagnetic waves can be efficiently guided by modifying the effective refractive index. Graphene behavior can range between a lossy dielectric and a good conductor due to the variation of its chemical potential bias, thus arising as a promising solution for electromagnetic devices. The graphene properties and a lens antenna comprising multiples layers and periodic arrangements of graphene patches were analyzed using full-wave simulations. A dipole directivity was improved from 7 to 18.5 dBi at 29 GHz. In addition, the realized gain was enhanced 7 dB across a 14 GHz bandwidth within the Ka/5G band.

Keywords: 5G/6G, graphene, lens, reconfigurable, satellite

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Authors: Farha Lakhani, Michael J. Pont

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There are two main architectures used to develop software for modern embedded systems: these can be labelled as “event-triggered” (ET) and “time-triggered” (TT). The research presented in this paper is concerned with the issues involved in migration between these two architectures. Although TT architectures are widely used in safety-critical applications they are less familiar to developers of mainstream embedded systems. The research presented in this paper began from the premise that–for a broad class of systems that have been implemented using an ET architecture–migration to a TT architecture would improve reliability. It may be tempting to assume that conversion between ET and TT designs will simply involve converting all event-handling software routines into periodic activities. However, the required changes to the software architecture are, in many cases rather more profound. The main contribution of the work presented in this paper is to identify ways in which the significant effort involved in migrating between existing ET architectures and “equivalent” (and effective) TT architectures could be reduced. The research described in this paper has taken an innovative step in this regard by introducing the use of ‘Design patterns’ for this purpose for the first time.

Keywords: embedded applications, software architectures, reliability, pattern

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Authors: Jun Seung Woo, Shin Dong Ho

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The Image Captioning models with Attention technology have developed significantly compared to previous models, but it is still unsatisfactory in recognizing images. We perform an extensive search over seven interesting Convolutional Neural Networks(CNN) architectures to analyze the behavior of different models for image captioning. We compared seven different CNN Architectures, according to batch size, using on public benchmarks: MS-COCO datasets. In our experimental results, DenseNet and InceptionV3 got about 14% loss and about 160sec training time per epoch. It was the most satisfactory result among the seven CNN architectures after training 50 epochs on GPU.

Keywords: deep learning, image captioning, CNN architectures, densenet, inceptionV3

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Authors: Nikolaj Troels Graf Von Malotky, Robin Nicolay, Alke Martens

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There exist a plethora of architectures for ITSs (Intelligent Tutoring Systems). A thorough analysis and comparison of the architectures revealed, that in most cases the architecture extensions are evolutionary grown, reflecting state of the art trends of each decade. However, from the perspective of software engineering, the main aspect of an ITS has not been reflected in any of these architectures, yet. From the perspective of cognitive research, the construction of the teaching process is what makes an ITS 'intelligent' regarding the spectrum of interaction with the students. Thus, in our approach, we focus on a behavior based architecture, which is based on the main teaching processes. To create a new general architecture for ITS, we have to define the prerequisites. This paper analyzes the current state of the existing architectures and derives rules for the behavior of ITS. It is presenting a teaching process for ITSs to be used together with the architecture.

Keywords: intelligent tutoring, ITS, tutoring process, system architecture, interaction process

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Authors: Tiago Sampaio, André Vasconcelos, Bruno Fragoso

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The Normalized Systems Theory, which is designed to be applied to software architectures, provides a set of theorems, elements and rules, with the purpose of enabling evolution in Information Systems, as well as ensuring that they are ready for change. In order to make that possible, this work’s solution is to apply the Normalized Systems Theory to the domain of enterprise architectures, using Archimate. This application is achieved through the adaptation of the elements of this theory, making them artifacts of the modeling language. The theorems are applied through the identification of the viewpoints to be used in the architectures, as well as the transformation of the theory’s encapsulation rules into architectural rules. This way, it is possible to create normalized enterprise architectures, thus fulfilling the needs and requirements of the business. This solution was demonstrated using the Portuguese Public Procurement System. The Portuguese government aims to make this system as fair as possible, allowing every organization to have the same business opportunities. The aim is for every economic operator to have access to all public tenders, which are published in any of the 6 existing platforms, independently of where they are registered. In order to make this possible, we applied our solution to the construction of two different architectures, which are able of fulfilling the requirements of the Portuguese government. One of those architectures, TO-BE A, has a Message Broker that performs the communication between the platforms. The other, TO-BE B, represents the scenario in which the platforms communicate with each other directly. Apart from these 2 architectures, we also represent the AS-IS architecture that demonstrates the current behavior of the Public Procurement Systems. Our evaluation is based on a comparison between the AS-IS and the TO-BE architectures, regarding the fulfillment of the rules and theorems of the Normalized Systems Theory and some quality metrics.

Keywords: archimate, architecture, broker, enterprise, evolvable systems, interoperability, normalized architectures, normalized systems, normalized systems theory, platforms

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Authors: Gaurav Upadhyay, Nand Kishore, Prashant Ranjan, Shivesh Tripathi, V. S. Tripathi

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In this paper, a patch antenna array design is proposed for vehicular communication. The antenna consists of 2-element patch array. The antenna array is operating at multiple frequency bands. The multiband operation is achieved by use of slots at proper locations at the patch. The array is made reconfigurable by use of two PIN-diodes. The antenna is simulated and measured in four states of diodes i.e. ON-ON, ON-OFF, OFF-ON, and OFF-OFF. In ON-ON state of diodes, the resonant frequencies are 4.62-4.96, 6.50-6.75, 6.90-7.01, 7.34-8.22, 8.89-9.09 GHz. In ON-OFF state of diodes, the measured resonant frequencies are 4.63-4.93, 6.50-6.70 and 7.81-7.91 GHz. In OFF-ON states of diodes the resonant frequencies are 1.24-1.46, 3.40-3.75, 5.07-5.25 and 6.90-7.20 GHz and in the OFF-OFF state of diodes 4.49-4.75 and 5.61-5.98 GHz. The maximum bandwidth of the proposed antenna is 16.29%. The peak gain of the antenna is 3.4 dB at 5.9 GHz, which makes it suitable for vehicular communication.

Keywords: antenna, array, reconfigurable, vehicular

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Authors: Peter Tabatt, Christian Siemers

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Using FPGA devices to improve the behavior of time-critical parts of embedded systems is a proven concept for years. With reconfigurable FPGA devices, the logical blocks can be partitioned and grouped into static and dynamic parts. The dynamic parts can be reloaded 'on demand' at runtime. This work uses cellular automata, which are constructed through compilation from (partially restricted) ANSI-C sources, to determine the suitability of various metrics for optimal partitioning. Significant metrics, in this case, are for example the area on the FPGA device for the partition, the pass count for loop constructs and communication characteristics to other partitions. With successful partitioning, it is possible to use smaller FPGA devices for the same requirements as with not reconfigurable FPGA devices or – vice versa – to use the same FPGAs for larger programs.

Keywords: reconfigurable FPGA, cellular automata, partitioning, metrics, parallel computing

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Authors: Mr. P. Suryaprasad, R. Lalitha

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This paper presents an efficient area and delay architectures for the implementation of one dimensional and two dimensional discrete cosine transform (DCT). These are supported to different lengths (4, 8, 16, and 32). DCT blocks are used in the different video coding standards for the image compression. The 2D- DCT calculation is made using the 2D-DCT separability property, such that the whole architecture is divided into two 1D-DCT calculations by using a transpose buffer. Based on the existing 1D-DCT architecture two different types of 2D-DCT architectures, folded and parallel types are implemented. Both of these two structures use the same transpose buffer. Proposed transpose buffer occupies less area and high speed than existing transpose buffer. Hence the area, low power and delay of both the 2D-DCT architectures are reduced.

Keywords: transposition buffer, video compression, discrete cosine transform, high efficiency video coding, two dimensional picture

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Authors: Sudhina H. K, Ravi M. Yadahalli, N. M. Shetti

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Reconfigurable antennas represent a recent innovation in antenna design that changes from classical fixed-form, Fixed function antennas to modifiable structures that can be adapted to fit the requirements of a time varying system. The ability to control the operating band of an antenna system can have many useful applications. Systems that operate in an acquire-and-track configuration would see a benefit from active bandwidth control. In such systems a wide band search mode is first employed to find a desired signal, Then a narrow band track mode is used to follow only that signal. Utilizing active antenna bandwidth control, A single antenna would function for both the wide band and narrow band configurations providing the rejection of unwanted signals with the antenna hardware. This ability to move a portion of the RF filtering out of the receiver and onto the antenna itself will also aid in reducing the complexity of the often expensive RF processing subsystems.

Keywords: designing methods, mems, stack, reconfigurable elements

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Authors: Tanish Mittal, Preyansh Agrawal, Esha Pahwa, Aarya Makwana

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Multi-Scale and U-shaped Networks are widely used in various image restoration problems, including deblurring. Keeping in mind the wide range of applications, we present a comparison of these architectures and their effects on image deblurring. We also introduce a new block called as NFResblock. It consists of a Fast Fourier Transformation layer and a series of modified Non-Linear Activation Free Blocks. Based on these architectures and additions, we introduce NFResnet and NFResnet+, which are modified multi-scale and U-Net architectures, respectively. We also use three differ-ent loss functions to train these architectures: Charbonnier Loss, Edge Loss, and Frequency Reconstruction Loss. Extensive experiments on the Deep Video Deblurring dataset, along with ablation studies for each component, have been presented in this paper. The proposed architectures achieve a considerable increase in Peak Signal to Noise (PSNR) ratio and Structural Similarity Index (SSIM) value.

Keywords: multi-scale, Unet, deblurring, FFT, resblock, NAF-block, nfresnet, charbonnier, edge, frequency reconstruction

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Authors: Qinghua Zhang, Yanhe Zhu, Xiang Zhao, Yeqin Yang, Hongwei Jing, Guoan Zhang, Jie Zhao

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This paper presents a wearable reconfigurable supernumerary robotic limb with differential actuated joints, which is lightweight, compact and comfortable for the wearers. Compared to the existing supernumerary robotic limbs which mostly adopted series structure with large movement space but poor carrying capacity, a prototype with the series-parallel configuration to better adapt to different task requirements has been developed in this design. To achieve a compact structure, two kinds of cable-driven mechanical structures based on guide pulleys and differential actuated joints were designed. Moreover, two different tension devices were also designed to ensure the reliability and accuracy of the cable-driven transmission. The proposed device also employed self-designed bearings which greatly simplified the structure and reduced the cost.

Keywords: cable-driven, differential actuated joints, reconfigurable, supernumerary robotic limb

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Authors: Getaneh Berie Tarekegn

Abstract:

Wireless communication via unmanned aerial vehicles (UAVs) has drawn a great deal of attention due to its flexibility in establishing line-of-sight (LoS) communications. However, in complex urban and dynamic environments, the movement of UAVs can be blocked by trees and high-rise buildings that obstruct directional paths. With reconfigurable intelligent surfaces (RIS), this problem can be effectively addressed. To achieve this goal, accurate channel estimation in RIS-assisted UAV-enabled wireless communications is crucial. This paper proposes an accurate channel estimation model using long short-term memory (LSTM) for a multi-user RIS-assisted UAV-enabled wireless communication system. According to simulation results, LSTM can improve the channel estimation performance of RIS-assisted UAV-enabled wireless communication.

Keywords: channel estimation, reconfigurable intelligent surfaces, long short-term memory, unmanned aerial vehicles

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Authors: Y. Lacroix, J.-F. Malbranque

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We present a chronological evolution for naval telecommunication networks. We distinguish periods: with or without multiplexers, with switch systems, with federative systems, with medium switching, and with medium switching with wireless networks. This highlights the introduction of new layers and technology in the architecture. These architectures are presented using layer models of transmission, in a unified way, which enables us to integrate pre-existing models. A ship of a naval fleet has internal communications (i.e. applications' networks of the edge) and external communications (i.e. the use of the means of transmission between edges). We propose architectures, deduced from the layer model, which are the point of convergence between the networks on board and the HF, UHF radio, and satellite resources. This modelling allows to consider end-to-end naval communications, and in a more global way, that is from the user on board towards the user on shore, including transmission and networks on the shore side. The new architectures need take care of quality of services for end-to-end communications, the more remote control develops a lot and will do so in the future. Naval telecommunications will be more and more complex and will use more and more advanced technologies, it will thus be necessary to establish clear global communication schemes to grant consistency of the architectures. Our latest model has been implemented in a military naval situation, and serves as the basic architecture for the RIFAN2 network.

Keywords: equilibrium beach profile, eastern tombolo of Giens, potential function, erosion

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Authors: Yousef Farhaoui

Abstract:

An IDS is a tool which is used to improve the level of security.In this paper we present different architectures of IDS. We will also discuss measures that define the effectiveness of IDS and the very recent works of standardization and homogenization of IDS. At the end, we propose a new model of IDS called BiIDS (IDS Based on the two principles of detection).

Keywords: intrusion detection, architectures, characteristic, tools, security

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Authors: Elmahdi Khalil, Saad Enniari, Mostapha Zbakh

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Cloud computing promises to increase innovation and the velocity with witch applications are deployed, all while helping any enterprise meet most IT service needs at a lower total cost of ownership and higher return investment. As the march of cloud continues, it brings both new opportunities and new security challenges. To take advantages of those opportunities while minimizing risks, we think that Intrusion Detection Systems (IDS) integrated in the cloud is one of the best existing solutions nowadays in the field. The concept of intrusion detection was known since past and was first proposed by a well-known researcher named Anderson in 1980's. Since that time IDS's are evolving. Although, several efforts has been made in the area of Intrusion Detection systems for cloud computing environment, many attacks still prevail. Therefore, the work presented in this paper proposes a multi criteria analysis and a comparative study between several IDS architectures designated to work in a cloud computing environments. To achieve this objective, in the first place we will search in the state of the art of several consistent IDS architectures designed to work in a cloud environment. Whereas, in a second step we will establish the criteria that will be useful for the evaluation of architectures. Later, using the approach of multi criteria decision analysis Mac Beth (Measuring Attractiveness by a Categorical Based Evaluation Technique we will evaluate the criteria and assign to each one the appropriate weight according to their importance in the field of IDS architectures in cloud computing. The last step is to evaluate architectures against the criteria and collecting results of the model constructed in the previous steps.

Keywords: cloud computing, cloud security, intrusion detection/prevention system, multi-criteria decision analysis

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Authors: Deepak Kumar, Debasish Deb, Reena Mamgain

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Radar signal processing requires high number crunching capability. Most often this is achieved using multiprocessor platform. Though multiprocessor platform provides the capability of meeting the real time computational challenges, the architecture of the same along with mapping of the algorithm on the architecture plays a vital role in efficiently using the platform. Towards this, along with standard performance metrics, few additional metrics are defined which helps in evaluating the multiprocessor platform along with the algorithm mapping. A generic multiprocessor architecture can not suit all the processing requirements. Depending on the system requirement and type of algorithms used, the most suitable architecture for the given problem is decided. In the paper, we study different architectures and quantify the different performance metrics which enables comparison of different architectures for their merit. We also carried out case study of different architectures and their efficiency depending on parallelism exploited on algorithm or data or both.

Keywords: radar signal processing, multiprocessor architecture, efficiency, load imbalance, buffer requirement, pipeline, parallel, hybrid, cluster of processors (COPs)

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Authors: Ting Gao, Mingyue He

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Reconfigurable intelligent surfaces (RISs) are expected to be an important part of next-generation wireless communication networks due to their potential to reduce the hardware cost and energy consumption of millimeter Wave (mmWave) massive multiple-input multiple-output (MIMO) technology. However, owing to the lack of signal processing abilities of the RIS, the perfect channel state information (CSI) in RIS-assisted communication systems is difficult to acquire. In this paper, the uplink channel estimation for mmWave systems with a hybrid active/passive RIS architecture is studied. Specifically, a deep learning-based estimation scheme is proposed to estimate the channel between the RIS and the user. In particular, the sparse structure of the mmWave channel is exploited to formulate the channel estimation as a sparse reconstruction problem. To this end, the proposed approach is derived to obtain the distribution of non-zero entries in a sparse channel. After that, the channel is reconstructed by utilizing the least-squares (LS) algorithm and compressed sensing (CS) theory. The simulation results demonstrate that the proposed channel estimation scheme is superior to existing solutions even in low signal-to-noise ratio (SNR) environments.

Keywords: channel estimation, reconfigurable intelligent surface, wireless communication, deep learning

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