Search results for: CMOS capacitor array

Authors: Tomasz Grzes, Maciej Kopczynski, Jaroslaw Stepaniuk

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The rough sets theory developed by Prof. Z. Pawlak is one of the tools that can be used in the intelligent systems for data analysis and processing. Banking, medicine, image recognition and security are among the possible fields of utilization. In all these fields, the amount of the collected data is increasing quickly, but with the increase of the data, the computation speed becomes the critical factor. Data reduction is one of the solutions to this problem. Removing the redundancy in the rough sets can be achieved with the reduct. A lot of algorithms of generating the reduct were developed, but most of them are only software implementations, therefore have many limitations. Microprocessor uses the fixed word length, consumes a lot of time for either fetching as well as processing of the instruction and data; consequently, the software based implementations are relatively slow. Hardware systems don’t have these limitations and can process the data faster than a software. Reduct is the subset of the decision attributes that provides the discernibility of the objects. For the given decision table there can be more than one reduct. Core is the set of all indispensable condition attributes. None of its elements can be removed without affecting the classification power of all condition attributes. Moreover, every reduct consists of all the attributes from the core. In this paper, the hardware implementation of the two-stage greedy algorithm to find the one reduct is presented. The decision table is used as an input. Output of the algorithm is the superreduct which is the reduct with some additional removable attributes. First stage of the algorithm is calculating the core using the discernibility matrix. Second stage is generating the superreduct by enriching the core with the most common attributes, i.e., attributes that are more frequent in the decision table. Described above algorithm has two disadvantages: i) generating the superreduct instead of reduct, ii) additional first stage may be unnecessary if the core is empty. But for the systems focused on the fast computation of the reduct the first disadvantage is not the key problem. The core calculation can be achieved with a combinational logic block, and thus add respectively little time to the whole process. Algorithm presented in this paper was implemented in Field Programmable Gate Array (FPGA) as a digital device consisting of blocks that process the data in a single step. Calculating the core is done by the comparators connected to the block called 'singleton detector', which detects if the input word contains only single 'one'. Calculating the number of occurrences of the attribute is performed in the combinational block made up of the cascade of the adders. The superreduct generation process is iterative and thus needs the sequential circuit for controlling the calculations. For the research purpose, the algorithm was also implemented in C language and run on a PC. The times of execution of the reduct calculation in a hardware and software were considered. Results show increase in the speed of data processing.

Keywords: data reduction, digital systems design, field programmable gate array (FPGA), reduct, rough set

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Authors: M. Marjaneh, M. Y. Narazah, H. Shahrul

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Array-based gene expression analysis is a powerful tool to profile expression of genes and to generate information on therapeutic effects of new anti-cancer compounds. Anti-apoptotic effect of thymoquinone was studied in MCF7 breast cancer cell line using gene expression profiling with cDNA micro array. The purity and yield of RNA samples were determined using RNeasyPlus Mini kit. The Agilent RNA 6000 Nano LabChip kit evaluated the quantity of the RNA samples. AffinityScript RT oligo-dT promoter primer was used to generate cDNA strands. T7 RNA polymerase was used to convert cDNA to cRNA. The cRNA samples and human universal reference RNA were labelled with Cy-3-CTP and Cy-5-CTP, respectively. Feature Extraction and GeneSpring software analysed the data. The single experiment analysis revealed involvement of 64 pathways with up-regulated genes and 78 pathways with down-regulated genes. The MAPK and p38-MAPK pathways were inhibited due to the up-regulation of PTPRR gene. The inhibition of p38-MAPK suggested up-regulation of TGF-ß pathway. Inhibition of p38 - MAPK caused up-regulation of TP53 and down-regulation of Bcl2 genes indicating involvement of intrinsic apoptotic pathway. Down-regulation of CARD16 gene as an adaptor molecule regulated CASP1 and suggested necrosis-like programmed cell death and involvement of caspase in apoptosis. Furthermore, down-regulation of GPCR, EGF-EGFR signalling pathways suggested reduction of ER. Involvement of AhR pathway which control cytochrome P450 and glucuronidation pathways showed metabolism of Thymoquinone. The findings showed differential expression of several genes in apoptosis pathways with thymoquinone treatment in estrogen receptor-positive breast cancer cells.

Keywords: cDNA microarray, thymoquinone, CARD16, PTPRR, CASP10

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Authors: Mahdiar Hosseighadiry, Farnaz Fotovatikhah, Razali Ismail, Mohsen Khaledian, Mehdi Saeidemanesh

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In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles.

Keywords: full adders, low-power, high-performance, VLSI design

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Authors: Kala Bharathan, R. Seshasayanan

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In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Galu Papy Yuma

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This paper presents a new dynamic simulation of a power system consisting of four machines equipped with the Generalized Unified Power Flow Controller (GUPFC) to improve power system stability. The dynamic simulation of the GUPFC consists of one shunt converter and two series converters based on voltage source converter, and DC link capacitor installed in the power system. MATLAB/Simulink is used to arrange the dynamic simulation of the GUPFC, where the power system is simulated in order to investigate the impact of the controller on power system oscillation damping and to show the simulation program reliability. The Improved Chaotic- Harmony Search (IC-HS) Algorithm is used to provide the parameter controller in order to lead-lag compensation design. The results obtained by simulation show that the power system with four machines is suitable for stability analysis. The use of GUPFC and IC-HS Algorithm provides the excellent capability in fast damping of power system oscillations and improve greatly the dynamic stability of the power system.

Keywords: GUPFC, IC-HS algorithm, Matlab/Simulink, damping oscillation

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Authors: M. A. Aleem, M. S. Awan

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Flat spiral coil for electromagnetic forming system has been modelled in FEMM 4.2 software. Copper strip was chosen as the material for designing the actuator coil. Relationship between height to width ratio (S-factor) of the copper strip and coil’s performance has been studied. Magnetic field intensities, eddy currents, and Lorentz force were calculated for the coils that were designed using six different 'S-factor' values (0.65, 0.75, 1.05, 1.25, 1.54 and 1.75), keeping the cross-sectional area of strip the same. Results obtained through simulation suggest that actuator coil with S-factor ~ 1 shows optimum forming performance as it exerts maximum Lorentz force (84 kN) on work piece. The same coils were fabricated and used for electromagnetic sheet forming experiments. Aluminum 6061 sheets of thickness 1.5 mm have been formed using different voltage levels of capacitor bank. Smooth forming profiles were obtained with dome heights 28, 35 and 40 mm in work piece at 800, 1150 and 1250 V respectively.

Keywords: FEM modelling, electromagnetic forming, spiral coil, Lorentz force

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Authors: A. Djahbar, M. Aillerie, E. Bounadja

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In this paper we treat a new structure of a high-power actuator which is used to either industry or electric traction. Indeed, the actuator is constituted by two induction motors, the first is a six-phase motor connected in series with another three-phase motor via the stators. The whole is supplied by a single static converter. Our contribution in this paper is the optimization of the system supply source. This is feeding the multimotor group by a direct converter frequency without using the DC-link capacitor. The modelling of the components of multimotor system is presented first. Only the first component of stator currents is used to produce the torque/flux of the first machine in the group. The second component of stator currents is considered as additional degrees of freedom and which can be used for power conversion for the other connected motors. The decoupling of each motor from the group is obtained using the direct vector control scheme. Simulation results demonstrate the effectiveness of the proposed structure.

Keywords: induction machine, motor drives, scalar modulation technique, three-to-six phase matrix converter

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Authors: Matthew Yeager, Christopher Willy, John Bischoff

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The conceptualization and design phases of a system lifecycle consume a significant amount of the lifecycle budget in the form of direct tasking and capital, as well as the implicit costs associated with unforeseeable design errors that are only realized during downstream phases. Ad hoc or iterative approaches to generating system requirements oftentimes fail to consider the full array of feasible systems or product designs for a variety of reasons, including, but not limited to: initial conceptualization that oftentimes incorporates a priori or legacy features; the inability to capture, communicate and accommodate stakeholder preferences; inadequate technical designs and/or feasibility studies; and locally-, but not globally-, optimized subsystems and components. These design pitfalls can beget unanticipated developmental or system alterations with added costs, risks and support activities, heightening the risk for suboptimal system performance, premature obsolescence or forgone development. Supported by rapid advances in learning algorithms and hardware technology, sensors and sensor systems have become commonplace in both commercial and industrial products. The evolving array of hardware components (i.e. sensors, CPUs, modular / auxiliary access, etc…) as well as recognition, data fusion and communication protocols have all become increasingly complex and critical for design engineers during both concpetualization and implementation. This work seeks to develop and utilize a non-deterministic approach for sensor system design within the multi-attribute tradespace exploration (MATE) paradigm, a technique that incorporates decision theory into model-based techniques in order to explore complex design environments and discover better system designs. Developed to address the inherent design constraints in complex aerospace systems, MATE techniques enable project engineers to examine all viable system designs, assess attribute utility and system performance, and better align with stakeholder requirements. Whereas such previous work has been focused on aerospace systems and conducted in a deterministic fashion, this study addresses a wider array of system design elements by incorporating both traditional tradespace elements (e.g. hardware components) as well as popular multi-sensor data fusion models and techniques. Furthermore, statistical performance features to this model-based MATE approach will enable non-deterministic techniques for various commercial systems that range in application, complexity and system behavior, demonstrating a significant utility within the realm of formal systems decision-making.

Keywords: multi-attribute tradespace exploration, data fusion, sensors, systems engineering, system design

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Authors: Mohamad Baqer Heidari, Hefzollah.Mohammadian

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This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

Keywords: analog signal processing, current-mode operation, functional core, multiplier, reconfigurable circuits, industrial package systems

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Authors: Santhosh Ravichandran, F. J. Rodríguez-Varela

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In this study, a biocarbon (BC) was made from sewage sludge from the water treatment plant (PTAR) in Saltillo, Coahuila, Mexico. The sludge was carbonized in water and then chemically activated by pyrolysis. The biocarbon was evaluated physicochemically using XRD, SEM-EDS, and FESEM. A broad (002) peak attributable to graphitic structures indicates that the material is amorphous. The resultant biocarbon has a high specific surface area (412 m2 g-1), a large pore volume (0.39 cm3 g-1), interconnected hierarchical porosity, and outstanding electrochemical performance. It is appropriate for high-performance supercapacitor electrode materials due to its high specific capacitance of 358 F g-1, great rate capability, and outstanding cycling stability (around 87% capacitance retention after 10,000 cycles, even at a high current density of 19 A g-1). In an aqueous solution, the constructed BC/BC symmetric supercapacitor exhibits increased super capacitor behavior with a high energy density of 29.5 Whkg-1. The concept provides an efficient method for producing high-performance electrode materials for supercapacitors from conventional water treatment biomass wastes.

Keywords: supercapacitors, carbon, material science, batteries

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Authors: Md. Asif Ullah, M. A. R. Sarkar

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This paper illustrates 2-D and 3-D simulations of sub-channels of a Pressurized Water Reactor (PWR) having hexagonal array of fuel rods. At a steady state, the temperature of outer surface of the cladding of fuel rod is kept about 1200°C. The temperature of this isothermal surface is taken as boundary condition for simulation. Water with temperature of 290°C is given as a coolant inlet to the primary water circuit which is pressurized upto 157 bar. Turbulent flow of pressurized water is used for heat removal. In 2-D model, temperature, velocity, pressure and Nusselt number distributions are simulated in a vertical sectional plane through the sub-channels of a hexagonal fuel rod assembly. Temperature, Nusselt number and Y-component of convective heat flux along a line in this plane near the end of fuel rods are plotted for different Reynold’s number. A comparison between X-component and Y-component of convective heat flux in this vertical plane is analyzed. Hexagonal fuel rod assembly has three types of sub-channels according to geometrical shape whose boundary conditions are different too. In 3-D model, temperature, velocity, pressure, Nusselt number, total heat flux magnitude distributions for all the three sub-channels are studied for a suitable Reynold’s number. A horizontal sectional plane is taken from each of the three sub-channels to study temperature, velocity, pressure, Nusselt number and convective heat flux distribution in it. Greater values of temperature, Nusselt number and Y-component of convective heat flux are found for greater Reynold’s number. X-component of convective heat flux is found to be non-zero near the bottom of fuel rod and zero near the end of fuel rod. This indicates that the convective heat transfer occurs totally along the direction of flow near the outlet. As, length to radius ratio of sub-channels is very high, simulation for a short length of the sub-channels are done for graphical interface advantage. For the simulations, Turbulent Flow (K-Є ) module and Heat Transfer in Fluids (ht) module of COMSOL MULTIPHYSICS 5.0 are used.

Keywords: sub-channels, Reynold’s number, Nusselt number, convective heat transfer

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Authors: Kamran Yousefpour, Mojtaba Rostaghi-Chalaki, Jason Warden, Chanyeop Park

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There has been a rising trend in using impulse current generators to investigate the lightning strike protection of materials including aluminum and composites in structures such as wind turbine blade and aircraft body. The focus of this research is to present a new impulse current generator built in the High Voltage Lab at Mississippi State University. The generator is capable of producing component A and D of the natural lightning discharges in accordance with the Society of Automotive Engineers (SAE) standard, which is widely used in the aerospace industry. The generator can supply lightning impulse energy up to 400 kJ with the capability of producing impulse currents with magnitudes greater than 200 kA. The electrical circuit and physical components of an improved impulse current generator are described and several lightning strike waveforms with different amplitudes is presented for comparing with the standard waveform. The results of this study contribute to the fundamental understanding the functionality of the impulse current generators and present a new impulse current generator developed at the High Voltage Lab of Mississippi State University.

Keywords: impulse current generator, lightning, society of automotive engineers, capacitor

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Authors: Yousfi Abdelkader, Chaker Abdelkader, Bot Youcef

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This article proposes a five-level shunt active power filter for power quality improvement using a interval type-2 fuzzy logic controller (IT2 FLC). The reference compensating current is extracted using the P-Q theory. The majority of works previously reported are based on two-level inverters with a conventional Proportional integral (PI) controller, which requires rigorous mathematical modeling of the system. In this paper, a IT2 FLC controlled five-level active power filter is proposed to overcome the problem associated with PI controller. The IT2 FLC algorithm is applied for controlling the DC-side capacitor voltage as well as the harmonic currents of the five-level active power filter. The active power filter with a IT2 FLC is simulated in MATLAB Simulink environment. The simulated response shows that the proposed shunt active power filter controller has produced a sinusoidal supply current with low harmonic distortion and in phase with the source voltage.

Keywords: power quality, shunt active power filter, interval type-2 fuzzy logic controller (T2FL), multilevel inverter

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Authors: Arturo Daag

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The Philippine Institute of Volcanology and Seismology (PHIVOLCS) is enhancing its liquefaction hazard map towards a detailed probabilistic approach using SDS and geophysical data. Target sites for liquefaction assessment are public schools in Metro Manila. Since target sites are in highly urbanized-setting, the objective of the project is to conduct both non-destructive geotechnical studies using Screw Driving Testing (SDFS) combined with geophysical data such as refraction microtremor array (ReMi), 3 component microtremor Horizontal to Vertical Spectral Ratio (HVSR), and ground penetrating RADAR (GPR). Initial test data was conducted in liquefaction impacted areas from the Mw 6.1 earthquake in Central Luzon last April 22, 2019 Province of Pampanga. Numerous accounts of liquefaction events were documented areas underlain by quaternary alluvium and mostly covered by recent lahar deposits. SDS estimated values showed a good correlation to actual SPT values obtained from available borehole data. Thus, confirming that SDS can be an alternative tool for liquefaction assessment and more efficient in terms of cost and time compared to SPT and CPT. Conducting borehole may limit its access in highly urbanized areas. In order to extend or extrapolate the SPT borehole data, non-destructive geophysical equipment was used. A 3-component microtremor obtains a subsurface velocity model in 1-D seismic shear wave velocity of the upper 30 meters of the profile (Vs30). For the ReMi, 12 geophone array with 6 to 8-meter spacing surveys were conducted. Microtremor data were computed through the Factor of Safety, which is the quotient of Cyclic Resistance Ratio (CRR) and Cyclic Stress Ratio (CSR). Complementary GPR was used to study the subsurface structure and used to inferred subsurface structures and groundwater conditions.

Keywords: screw drive testing, microtremor, ground penetrating RADAR, liquefaction

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Authors: Edwin Foo, Woei Wen, Lui, Meijun Zhao, Shigeru Kuchii, Chin Sai Wong, Chung Sern Goh, Yi Hao He

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This presentation presents an elderly care and assistive social robot development work. We named this robot JOS and he is restricted to table top operation. JOS is designed to have a maximum volume of 3600 cm3 with its base restricted to 250 mm and his mission is to provide companion, assist and help the elderly. In order for JOS to accomplish his mission, he will be equipped with perception, reaction and cognition capability. His appearance will be not human like but more towards cute and approachable type. JOS will also be designed to be neutral gender. However, the robot will still have eyes, eyelid and a mouth. For his eyes and eyelids, they will be built entirely with Robotis Dynamixel AX18 motor. To realize this complex task, JOS will be also be equipped with micro-phone array, vision camera and Intel i5 NUC computer and a powered by a 12 V lithium battery that will be self-charging. His face is constructed using 1 motor each for the eyelid, 2 motors for the eyeballs, 3 motors for the neck mechanism and 1 motor for the lips movement. The vision senor will be house on JOS forehead and the microphone array will be somewhere below the mouth. For the vision system, Omron latest OKAO vision sensor is used. It is a compact and versatile sensor that is only 60mm by 40mm in size and operates with only 5V supply. In addition, OKAO vision sensor is capable of identifying the user and recognizing the expression of the user. With these functions, JOS is able to track and identify the user. If he cannot recognize the user, JOS will ask the user if he would want him to remember the user. If yes, JOS will store the user information together with the capture face image into a database. This will allow JOS to recognize the user the next time the user is with JOS. In addition, JOS is also able to interpret the mood of the user through the facial expression of the user. This will allow the robot to understand the user mood and behavior and react according. Machine learning will be later incorporated to learn the behavior of the user so as to understand the mood of the user and requirement better. For the speech system, Microsoft speech and grammar engine is used for the speech recognition. In order to use the speech engine, we need to build up a speech grammar database that captures the commonly used words by the elderly. This database is built from research journals and literature on elderly speech and also interviewing elderly what do they want to robot to assist them with. Using the result from the interview and research from journal, we are able to derive a set of common words the elderly frequently used to request for the help. It is from this set that we build up our grammar database. In situation where there is more than one person near JOS, he is able to identify the person who is talking to him through an in-house developed microphone array structure. In order to make the robot more interacting, we have also included the capability for the robot to express his emotion to the user through the facial expressions by changing the position and movement of the eyelids and mouth. All robot emotions will be in response to the user mood and request. Lastly, we are expecting to complete this phase of project and test it with elderly and also delirium patient by Feb 2015.

Keywords: social robot, vision, elderly care, machine learning

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Authors: Gurcharan Singh Buttar

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It has been discovered that although these two areas, statistics, and information theory, are independent in their nature, they can be combined to create applications in multidisciplinary mathematics. This is due to the fact that where in the field of statistics, statistical parameters (measures) play an essential role in reference to the population (distribution) under investigation. Information measure is crucial in the study of ambiguity, assortment, and unpredictability present in an array of phenomena. The following communication is a link between the two, and it has been demonstrated that the well-known conventional statistical measures can be used as a measure of information.

Keywords: probability distribution, entropy, concavity, symmetry, variance, central tendency

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Authors: Ian O'Loughlin

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Memory networks aim to integrate some of the recent successes in machine learning with a dynamic memory base that can be updated and deployed in artificial reasoning tasks. These models involve training networks to identify, update, and operate over stored elements in a large memory array in order, for example, to ably perform question and answer tasks parsing real-world and simulated discourses. This family of approaches still faces numerous challenges: the performance of these network models in simulated domains remains considerably better than in open, real-world domains, wide-context cues remain elusive in parsing words and sentences, and even moderately complex sentence structures remain problematic. This innovation, employing an array of stored and updatable ‘memory’ elements over which the system operates as it parses text input and develops responses to questions, is a compelling one for at least two reasons: first, it addresses one of the difficulties that standard machine learning techniques face, by providing a way to store a large bank of facts, offering a way forward for the kinds of long-term reasoning that, for example, recurrent neural networks trained on a corpus have difficulty performing. Second, the addition of a stored long-term memory component in artificial reasoning seems psychologically plausible; human reasoning appears replete with invocations of long-term memory, and the stored but dynamic elements in the arrays of memory networks are deeply reminiscent of the way that human memory is readily and often characterized. However, this apparent psychological plausibility is belied by a recent turn in the study of human memory in cognitive science. In recent years, the very notion that there is a stored element which enables remembering, however dynamic or reconstructive it may be, has come under deep suspicion. In the wake of constructive memory studies, amnesia and impairment studies, and studies of implicit memory—as well as following considerations from the cognitive neuroscience of memory and conceptual analyses from the philosophy of mind and cognitive science—researchers are now rejecting storage and retrieval, even in principle, and instead seeking and developing models of human memory wherein plasticity and dynamics are the rule rather than the exception. In these models, storage is entirely avoided by modeling memory using a recurrent neural network designed to fit a preconceived energy function that attains zero values only for desired memory patterns, so that these patterns are the sole stable equilibrium points in the attractor network. So although the array of long-term memory elements in memory networks seem psychologically appropriate for reasoning systems, they may actually be incurring difficulties that are theoretically analogous to those that older, storage-based models of human memory have demonstrated. The kind of emergent stability found in the attractor network models more closely fits our best understanding of human long-term memory than do the memory network arrays, despite appearances to the contrary.

Keywords: artificial reasoning, human memory, machine learning, neural networks

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Authors: Guo-Ming Sung, Ramavath Naga Raju Naik

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This paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Deepak Choudhary

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COEP-Microgrid, a project by the students of College of Engineering Pune aims at establishing a micro grid in the college campus serving as a living laboratory for research and development of novel grid technologies. Proposed micro grid has an AC-bus and DC-bus, interconnected together with a tie line DC-AC converter. In grid-connected mode AC bus of microgrid is synchronized with utility grid. Synchronization with utility grid requires grid and AC bus to have synchronism in frequency, phase sequence and voltage. Power flow requires phase difference between grid and AC bus. Control System is required to effectively regulate power flow between the grid and AC bus. The grid synchronizing control system is composed of frequency and phase control for regulated power flow and voltage control system for reduction of reactive power flow. The control system involves automatic active power flow control. It takes the feedback of DC link Capacitor and changes the power angle accordingly. Control system incorporating voltage, phase and power control was developed for grid-tie inverter. This paper discusses the design, simulation and practical implementation of control system described in various micro grid scenarios.

Keywords: microgrid, Grid-tie inverter, voltage control, automatic power control

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Authors: Amir Mahdavi

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In this paper, a circuit topology of voltage-controlled oscillators (VCO) which is suitable for ultra-low-phase noise operations is introduced. To do so, a new low phase noise cross-coupled oscillator by using the general topology of cross-coupled oscillator and adding a differential stage for tail current shaping is designed. In addition, a tail current shaping technique to improve phase noise in differential LC VCOs is presented. The tail current becomes large when the oscillator output voltage arrives at the maximum or minimum value and when the sensitivity of the output phase to the noise is the smallest. Also, the tail current becomes small when the phase noise sensitivity is large. The proposed circuit does not use extra power and extra noisy active devices. Furthermore, this topology occupies small area. Simulation results show the improvement in phase noise by 2.5dB under the same conditions and at the carrier frequency of 1 GHz for GSM applications. The power consumption of the proposed circuit is 2.44 mW and the figure of merit (FOM) with -192.2 dBc/Hz is achieved for the new oscillator.

Keywords: LC oscillator, low phase noise, current shaping, diff mode

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

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The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: low-frequency noise, random telegraph noise, dynamic variation, SRRV

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

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As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: scan chain, single event transient, soft error, 8051 processor

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Authors: Safia Bashir, Zulfiqar Memon

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During the last decade, renewable energy sources in particular solar photovoltaic (PV) has gained increased attention. Therefore, various PV converters topologies have emerged. Among this topology, the modular multilevel converter (MMC) is considered as one of the most promising topologies for the grid-connected PV system due to its modularity and transformerless features. When it comes to the safe operation of MMC, the balancing of the Submodules Voltages (SMs) plays a critical role. This paper proposes a balancing approach based on space vector PWM (SVPWM). Unlike the existing techniques, this method generates the switching vectors for the MMC by using only one SVPWM for the upper arm. The lower arm switching vectors are obtained by finding the complement of the upper arm switching vectors. The use of one SVPWM not only simplifies the calculation but also helped in reducing the circulating current in the MMC. The proposed method is varied through simulation using Matlab/Simulink and compared with other available modulation methods. The results validate the ability of the suggested method in balancing the SMs capacitors voltages and reducing the circulating current which will help in reducing the power loss of the PV system.

Keywords: capacitor voltage balancing, circulating current, modular multilevel converter, PV system

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Authors: Hyungil Chae

Abstract:

This work presents a method to reduce spinning current of a Hall-effect sensor for low-power magnetic sensor applications. Spinning current of a Hall-effect sensor changes the direction of bias current periodically and can separate signals from DC-offset. The bias current is proportional to the sensor sensitivity but also increases the power consumption. To achieve both high sensitivity and low power consumption, the bias current can be pulse-width modulated. When the bias current duration Tb is reduced by a factor of N compared to the spinning current period of Tₛ/2, the total power consumption can be saved by N times. N can be large as long as the Hall-effect sensor settles down within Tb. The proposed scheme is implemented and simulated in a 0.18um CMOS process, and the power saving factor is 9.6 when N is 10. Acknowledgements: This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (20160001360022003, Development of Hall Semi-conductor for Smart Car and Device).

Keywords: chopper stabilization, Hall-effect sensor, pulse width modulation, spinning current

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Authors: Ly. Benbahouche

Abstract:

Currently, several soft switching topologies have been studied to achieve high power switching efficiency, reduced cost, improved reliability and reduced parasites. It is well known that improvement in power electronics systems always depend on advanced in power devices. The IGBT has been successfully used in a variety of switching applications such as motor drives and appliance control because of its superior characteristics. The aim of this paper is focuses on simulation and explication of the internal dynamics of IGBTs behaviour under the most popular soft switching schemas that is Zero Current Switching (ZCS) environments. The main purpose of this paper is to point out some mechanisms relating to current tail during the turn-off and examination of the response at turn-off with variation of temperature, inductance L, snubber capacitors Cs, and bus voltage in order to achieve an improved understanding of internal carrier dynamics. It is shown that the snubber capacitor, the inductance and even the temperature controls the magnitude and extent of the tail current, hence the turn-off time (switching speed of the device). Moreover, it has also been demonstrated that the ZCS switching can be utilized efficiently to improve and reduce the power losses as well as the turn-off time. Furthermore, the turn-off loss in ZCS was found to depend on the time of switching of the device.

Keywords: PT-IGBT, ZCS, turn-off losses, dV/dt

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Authors: Amin Sedighfar, M. R. Moniri

Abstract:

Determination of state of charge (SOC) in today’s world becomes an increasingly important issue in all the applications that include a battery. In fact, estimation of the SOC is a fundamental need for the battery, which is the most important energy storage in Hybrid Electric Vehicles (HEVs), smart grid systems, drones, UPS and so on. Regarding those applications, the SOC estimation algorithm is expected to be precise and easy to implement. This paper presents an online method for the estimation of the SOC of Valve-Regulated Lead Acid (VRLA) batteries. The proposed method uses the well-known Kalman Filter (KF), and Neural Networks (NNs) and all of the simulations have been done with MATLAB software. The NN is trained offline using the data collected from the battery discharging process. A generic cell model is used, and the underlying dynamic behavior of the model has used two capacitors (bulk and surface) and three resistors (terminal, surface, and end), where the SOC determined from the voltage represents the bulk capacitor. The aim of this work is to compare the performance of conventional integration-based SOC estimation methods with a mixed algorithm. Moreover, by containing the effect of temperature, the final result becomes more accurate. 

Keywords: Kalman filter, neural networks, state-of-charge, VRLA battery

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Authors: Muhammad Abdullah Arafat, Nahrin Nowrose

Abstract:

Wireless charging of electric vehicles is becoming more and more attractive as large amount of power can now be transferred to a reasonable distance using magnetic resonance coupling method. However, proper tuning of the compensation network is required to achieve maximum power transmission. Due to the variation of coil distance from the nominal value as a result of change in tire condition, change in weight or uneven road condition, the tuning of the compensation network has become challenging. In this paper, a tuning method has been described to determine the optimum values of the compensation network in order to maximize the average output power. The simulation results show that 5.2 percent increase in average output power is obtained for 10 percent variation in coupling coefficient using the optimum values without the need of additional space and electro-mechanical components. The proposed method is applicable to both static and dynamic charging of electric vehicles.

Keywords: coupling coefficient, electric vehicles, magnetic resonance coupling, tuning capacitor, wireless power transfer

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Authors: Nour Hassan Ismail, Abdelmonem Nassar, Khaled Baz

Abstract:

Semiconductor crystals smaller than about 10 nm, known as quantum dots, have properties that differ from large samples, including a band gap that becomes larger for smaller particles. These properties create several applications for quantum dots. In this paper, new shapes of quantum dot arrays are used to enhance the photo physical properties of gold nano-particles. This paper presents a study of the effect of nano-particles shape, array, and size on their absorption characteristics.

Keywords: quantum dots, nano-particles, LSPR

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Authors: Mohammed Berka, Khaled Merit

Abstract:

Recent works on microwave filters show that the constituent materials such filters are very important in the design and realization. Several solutions have been proposed to improve the qualities of filtering. In this paper, we propose a new dual band-pass filter based on the coupling of a composite (CRLH) coplanar waveguide with complementary split ring resonators (CSRRs). The (CRLH) CPW is composed of two resonators, each one has an interdigital capacitor (CID) and two short-circuited stubs parallel to top ground plane. On the lower ground plane, we use defected ground structure technology (DGS) to engrave two (CSRRs) offered with different shapes and dimensions. Between the top ground plane and the substrate, we place a ferrite layer to control the electromagnetic coupling between (CRLH) CPW and (CSRRs). The global filter that has coplanar access will have a dual band-pass behavior around the magnetic resonances of (CSRRs). Since there’s no scientific or experimental result in the literature for this kind of complicated structure, it was necessary to perform simulation using HFSS Ansoft designer.

Keywords: complementary split ring resonators, coplanar waveguide, ferrite, filter, stub.

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Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: floating active resistor, complementary common gate, complementary regulated cascode, current mirror

Procedia PDF Downloads 236