Search results for: CMOS transistors

Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

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This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

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Authors: Ahmed Nassim Moulai Khatir

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Fin field effect transistors (FinFETs) deliver superior levels of scalability than the classical structure of MOSFETs by offering the elimination of short channel effects. Modern FinFETs are 3D structures that rise above the planar substrate, but some of these structures have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections usually used. Fin cross section shape of FinFETs results in some device issues, like potential distribution performance. This work analyzes that impact with three-dimensional numeric simulation of several triple-gate FinFETs with various top and bottom widths of fin. Results of the simulation show that the potential distribution and the electrical field in the fin depend on the sidewall inclination angle.

Keywords: FinFET, cross section shape, SILVACO, trapezoidal FinFETs

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Authors: Chyuan Haur Kao, Hsiang Chen, Yu Sheng Tsai, Chen Hao Hung, Yu Shan Lee

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Dielectric electrolyte-insulator-semiconductor sensing membranes-based biosensors have been intensively investigated because of their simple fabrication, low cost, and fast response. However, to enhance their sensing performance, it is worthwhile to explore alternative materials, distinct processes, and novel treatments. An ISFET can be viewed as a variation of MOSFET with the dielectric oxide layer as the sensing membrane. Then, modulation on the work function of the gate caused by electrolytes in various ion concentrations could be used to calculate the ion concentrations. Recently, owing to the advancement of CMOS technology, some high dielectric materials substrates as the sensing membranes of electrolyte-insulator-semiconductor (EIS) structures. The EIS with a stacked-layer of SiO₂ layer between the sensing membrane and the silicon substrate exhibited a high pH sensitivity and good long-term stability. IGZO is a wide-bandgap (~3.15eV) semiconductor of the III-VI semiconductor group with several preferable properties, including good transparency, high electron mobility, wide band gap, and comparable with CMOS technology. IGZO was sputtered by reactive radio frequency (RF) on a p-type silicon wafer with various gas ratios of Ar:O₂ and was treated with rapid thermal annealing in O₂ ambient. The sensing performance, including sensitivity, hysteresis, and drift rate was measured and XRD, XPS, and AFM analyses were also used to study the material properties of the IGZO membrane. Moreover, IGZO was used as a sensing membrane in dielectric EIS bio-sensor structures. In addition to traditional pH sensing capability, detection for concentrations of Na+, K+, urea, glucose, and creatinine was performed. Moreover, post rapid thermal annealing (RTA) treatment was confirmed to improve the material properties and enhance the multi-analyte sensing capability for various ions or chemicals in solutions. In this study, the IGZO sensing membrane with annealing in O₂ ambient exhibited a higher sensitivity, higher linearity, higher H+ selectivity, lower hysteresis voltage and lower drift rate. Results indicate that the IGZO dielectric sensing membrane on the EIS structure is promising for future bio-medical device applications.

Keywords: dielectric sensing membrane, IGZO, hydrogen ion, plasma, rapid thermal annealing

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

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This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: reconfigurable, fast Fourier transform (FFT), single-path delay feedback (SDF), 3GPP-LTE

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Authors: Zhao Bin, Yan Dan Lei

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In this paper, a multi-pattern parallel PRBS generator and a dedicated parallel BER tester is proposed for the 8-Gbps On-chip interconnection testing. A unique full-parallel PRBS checker is also proposed. The proposed design, together with the custom-designed high-speed parallel-to-serial and the serial-to-parallel circuit, will be used to test different on-chip interconnection transceivers. The design is implemented in TSMC 28nm CMOS technology with working voltage at 1.0 V. The serial to parallel ratio is 8:1 so the parallel PRBS generation and BER Tester can be run at lower speed.

Keywords: PRBS, BER, high speed, generator

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Authors: Chetna Tyagi, Ambuj Tripathi, Devesh Avasthi

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Graphene oxide consists of sp³ hybridization along with sp² hybridization due to the presence of different oxygen-containing functional groups on its edges and basal planes. However, its sp³ / sp² hybridization can be tuned by various methods to utilize it in different applications, like transistors, solar cells and biosensors. Ion beam irradiation can also be one of the methods to optimize sp² and sp³ hybridization ratio for its desirable properties. In this work, graphene oxide films were irradiated with 100 keV Argon ions at different fluences varying from 10¹³ to 10¹⁶ ions/cm². Synchrotron X-ray diffraction measurements showed an increase in crystallinity at the low fluence of 10¹³ ions/cm². Raman spectroscopy performed on irradiated samples determined the defects induced by the ion beam qualitatively. Also, identification of different groups and their removal with different fluences was done using Fourier infrared spectroscopy technique.

Keywords: graphene oxide, ion beam irradiation, spectroscopy, X-ray diffraction

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Authors: Boudjedra Abderrahim, Toumi Salah, Boutalbi Mostefa, Frihi Mohammed

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Nowadays, using the advancement of technology in semiconductor device fabrication, many transistors can be integrated to a single chip (VLSI). Although the growth chip density potentially eases systems-on-chip (SoCs) integrating thousands of processing element (PE) such as memory, processor, interfaces cores, system complexity, high-performance interconnect and scalable on-chip communication architecture become most challenges for many digital and embedded system designers. Networks-on-chip (NoCs) becomes a new paradigm that makes possible integrating heterogeneous devices and allows many communication constraints and performances. In this paper, we are interested for good performance and low area for implementation and a behavioral modeling of network on chip mesh topology design using VHDL hardware description language with performance evaluation and FPGA implementation results.

Keywords: design, implementation, communication system, network on chip, VHDL

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Authors: Varsha Prasad, S. Sandya

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Cosmic Ray effects in microelectronics such as single event effect (SET) and total dose ionization (TID) have been of major concern in space electronics since 1970. Advanced CMOS technologies have demonstrated reduced sensitivity to TID effect. However, charge pump Phase Locked Loop is very much vulnerable to single event transient effect. This paper presents an SET analysis model, where the SET is modeled as a double exponential pulse. The time domain analysis reveals that the settling time of the voltage controlled oscillator (VCO) depends on the SET pulse strength, setting the time constant and the damping factor. The analysis of the proposed SET analysis model is confirmed by the simulation results.

Keywords: charge pump, phase locked loop, SET, VCO

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Authors: Vasileios Gerakis, Fontounasios Christos, Alkis Hatzopoulos

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A study of the impact of metal guard rings on the coupling between two square metal pads is presented. The structure is designed over a bulk silicon substrate with epitaxial layer, so the coupling through the substrate is also involved. A lightly doped profile is adopted and is simulated by means of an electromagnetic simulator for various pad distances and different metal layers, assuming a 65 nm bulk CMOS technology. The impact of various guard ring design (geometrical) parameters is examined. Furthermore, the increase of isolation (resulting in reduction of the noise coupling) between the pads by cutting the ring, or by using multiple rings, is also analyzed. S parameters are used to compare the various structures.

Keywords: guard rings, metal pad coupling, millimeter wave frequencies, substrate noise,

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Authors: Ararat Khachatryan, Davit Mirzoyan

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In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.

Keywords: aging effect, HCI, NBTI, nanoscale

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Authors: Xuerui Niu, Bolin Wang, Xinchuang Zhang, Xiaohua Ma, Bin Hou, Ling Yang

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The application of discrete GaN-based power switches requires the collaboration of silicon-based peripheral circuit structures. However, the packages and interconnection between the Si and GaN devices can introduce parasitic effects to the circuit, which has great impacts on GaN power transistors. GaN-based monolithic power integration technology is an emerging solution which can improve the stability of circuits and allow the GaN-based devices to achieve more functions. Complementary logic circuits consisting of GaN-based E-mode p-channel heterostructure field-effect transistors (p-HFETs) and E-mode n-channel HEMTs can be served as the gate drivers. E-mode p-HFETs with recessed gate have attracted increasing interest because of the low leakage current and large gate swing. However, they suffer from a poor interface between the gate dielectric and polarized nitride layers. The reliability of p-HFETs is analyzed and discussed in this work. In circuit applications, the inverter is always operated with dynamic gate voltage (VGS) rather than a constant VGS. Therefore, dynamic electrical stress has been simulated to resemble the operation conditions for E-mode p-HFETs. The dynamic electrical stress condition is as follows. VGS is a square waveform switching from -5 V to 0 V, VDS is fixed, and the source grounded. The frequency of the square waveform is 100kHz with the rising/falling time of 100 ns and duty ratio of 50%. The effective stress time is 1000s. A number of stress tests are carried out. The stress was briefly interrupted to measure the linear IDS-VGS, saturation IDS-VGS, As VGS switches from -5 V to 0 V and VDS = 0 V, devices are under negative-bias-instability (NBI) condition. Holes are trapped at the interface of oxide layer and GaN channel layer, which results in the reduction of VTH. The negative shift of VTH is serious at the first 10s and then changes slightly with the following stress time. However, different phenomenon is observed when VDS reduces to -5V. VTH shifts negatively during stress condition, and the variation in VTH increases with time, which is different from that when VDS is 0V. Two mechanisms exists in this condition. On the one hand, the electric field in the gate region is influenced by the drain voltage, so that the trapping behavior of holes in the gate region changes. The impact of the gate voltage is weakened. On the other hand, large drain voltage can induce the hot holes generation and lead to serious hot carrier stress (HCS) degradation with time. The poor-quality interface between the oxide layer and GaN channel layer at the gate region makes a major contribution to the high-density interface traps, which will greatly influence the reliability of devices. These results emphasize that the improved etching and pretreatment processes needs to be developed so that high-performance GaN complementary logics with enhanced stability can be achieved.

Keywords: GaN-based E-mode p-HFETs, dynamic electric stress, threshold voltage, monolithic power integration technology

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Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza

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This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.

Keywords: divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver

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Authors: Kittipong Tripetch

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This paper proposes for the first time symbolic formula of the power spectrum of cross couple oscillator and its modified circuit. Many principle existed to derived power spectrum in microwave textbook such as impedance, admittance parameters, ABCD, H parameters, etc. It can be compared by graph of power spectrum which methodology is the best from the point of view of practical measurement setup such as condition of impedance parameter which used superposition of current to derived (its current injection of the other port of the circuit is zero, which is impossible in reality). Four Graphs of impedance parameters of cross couple oscillator is proposed. After that four graphs of Scattering parameters of cross couple oscillator will be shown.

Keywords: optimization, power spectrum, impedance parameters, scattering parameter

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Authors: T. Bielewicz, S. Dogan, C. Klinke

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Two-dimensional, solution-processable semiconductor materials are interesting for low-cost electronic applications [1]. We demonstrate the synthesis of lead sulfide nanosheets and how their size, shape and height can be tuned by varying concentrations of pre-cursors, ligands and by varying the reaction temperature. Especially, the charge carrier confinement in the nanosheets’ height adjustable from 2 to 20 nm has a decisive impact on their electronic properties. This is demonstrated by their use as conduction channel in a field effect transistor [2]. Recently we also showed that especially thin nanosheets show a high carrier multiplication (CM) efficiency [3] which could make them, through the confinement induced band gap and high photoconductivity, very attractive for application in photovoltaic devices. We are already able to manufacture photovoltaic devices out of single nanosheets which show promising results.

Keywords: physical sciences, chemistry, materials, chemistry, colloids, physics, condensed-matter physics, semiconductors, two-dimensional materials

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Authors: Shao-Ku Kao

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This paper presents an active rectifier with time-domain delay compensation to enhance the efficiency. A delay calibration circuit is designed to convert delay time to voltage and adaptive control on/off delay in variable input voltage. This circuit is designed in 0.18 mm CMOS process. The input voltage range is from 2 V to 3.6 V with the output voltage from 1.8 V to 3.4 V. The efficiency can maintain more than 85% when the load from 50 Ω ~ 1500 Ω for 3.6 V input voltage. The maximum efficiency is 92.4 % at output power to be 38.6 mW for 3.6 V input voltage.

Keywords: wireless power transfer, active diode, delay compensation, time to voltage converter, PCE

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Authors: S. Slimani, B. Djellouli

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Novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials like Ge is a very promising material due to its high mobility and is being considered to replace Si in the channel to achieve higher drive currents and switching speeds .Various approaches to circumvent the scaling limits to benchmark the performance of nanoscale MOSFETS with different channel materials, the optimized structure is simulated within nextnano in order to highlight the quantum effects on DG MOSFETs when Si is replaced by Ge and SiO2 is replaced by ZrO2 and HfO2as the gate dielectric. The results have shown that Ge MOSFET have the highest mobility and high permittivity oxides serve to maintain high drive current. The simulations show significant improvements compared with DGMOSFET using SiO2 gate dielectric and Si channel.

Keywords: high mobility, high-k, quantum effects, SOI-DGMOSFET

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

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The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, GaInP

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Authors: Mahsa Fathollahzadeh

Abstract:

The quick advancement of nanotechnology necessitates the creation of innovative theoretical approaches to elucidate complex experimental findings and forecast novel capabilities of nanodevices. Therefore, over the past ten years, a difficult task in quantum chemistry has been comprehending electron and spin transport in molecular devices. This thorough evaluation presents a comprehensive overview of current research and its status in the field of molecular electronics, emphasizing the theoretical applications to various device types and including a brief introduction to theoretical methods and their practical implementation plan. The subject matter includes a variety of molecular mechanisms like molecular cables, diodes, transistors, electrical and visual switches, nano detectors, magnetic valve gadgets, inverse electrical resistance gadgets, and electron tunneling exploration. The text discusses both the constraints of the method presented and the potential strategies to address them, with a total of 183 references.

Keywords: chemistry, nanotechnology, quantum, molecule, spin

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Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

Abstract:

This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: boost converter, current sensing, power-on protection, step-up converter, soft-start

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Authors: Soo Ho Lim, Minju Lee, Dong In Kim, Gi Youn Han, Seunghun Hong, Hyung Wook Kwon

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We report a floating electrode-based bioelectronic tongue mimicking honeybee taste systems for the detection and discrimination of various nutrients. Here, carbon nanotube field effect transistors with floating electrodes (CNT-FET) were hybridized with nanovesicles containing honeybee nutrient receptors, gustatory receptors of Apis mellifera. This strategy enables us to detect nutrient substance with a high sensitivity and selectivity. It could also be utilized for the detection of nutrients in liquid food. This floating electrode-based bioelectronic tongue mimicking insect taste systems can be a simple, but highly effective strategy in many different basic research areas about sensory systems. Moreover, our research provides opportunities to develop various applications such as food screening, and it also can provide valuable insights on insect taste systems.

Keywords: taste system, CNT-FET, insect gustatory receptor, biolelectronic tongue

Procedia PDF Downloads 190

Authors: L. Giraudet, O. Simonetti, G. de Tournadre, N. Dumelié, B. Clarenc, F. Reisdorffer

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In this paper we intend to give a comprehensive view of the saturation misbehavior of thin film transistors (TFTs) based on disordered semiconductors, such as most organic TFTs, and its link to the field activation of the mobility. Experimental evidence of the field activation of the mobility is given for disordered semiconductor based TFTs, when reducing the gate length. Saturation misbehavior is observed simultaneously. Advanced transport models have been implemented in a quasi-2D numerical TFT simulation software. From the numerical simulations it is clearly established that field activation of the mobility alone cannot explain the saturation misbehavior. Evidence is given that high longitudinal field gradient at the drain end of the channel is responsible for an excess charge accumulation, preventing saturation. The two combined effects allow reproducing the experimental output characteristics of short channel TFTs, with S-shaped characteristics and saturation failure.

Keywords: mobility field activation, numerical simulation, OTFT, saturation failure

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Authors: Kaivan Karami, Sahalu Hassan, Sanna Taking, Afesome Ofiare, Aniket Dhongde, Abdullah Al-Khalidi, Edward Wasige

Abstract:

We have made a comparative study on the influence of Al₂O₃ and HfO₂ grown using atomic layer deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of Al₂O₃ and HfO₂ respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al₂O₃ gate dielectric layers respectively. The negative shift for the 20 nm HfO2 and 20 nm Al₂O₃ were 1.2 V and 4.9 V respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO₂ than Al₂O₃. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 10^4 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: G. Traini, V. Giacometti, R. Mirabelli, V. Patera, D. Pinci, A. Sarti, A. Sciubba, M. Marafini

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The MONDO (MOnitor for Neutron Dose in hadrOntherapy) project aims a precise characterisation of the secondary fast and ultrafast neutrons produced in particle therapy treatments. The detector is composed of a matrix of scintillating fibres (250 um) readout by CMOS Digital-SPAD based sensors. Recoil protons from n-p elastic scattering are detected and used to track neutrons. A prototype was tested with proton beams (Trento Proton Therapy Centre): efficiency, light yield, and track-reconstruction capability were studied. The results of a MonteCarlo FLUKA simulation used to evaluated double scattering efficiency and expected backgrounds will be presented.

Keywords: secondary neutrons, particle therapy, tracking, elastic scattering

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Authors: Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng

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A digital baseband Application-Specific Integrated Circuit (ASIC) is developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm² in chip area (digital baseband: 0.060 mm², decimation filter: 0.056 mm²), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).

Keywords: biomedical sensor, decimation filter, radio frequency integrated circuit (RFIC) baseband, temperature sensor

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Authors: Zhipeng Dong, Jing Guo

Abstract:

Graphene-semiconductor contacts have been extensively studied recently, both as a stand-alone diode device for potential applications in photodetectors and solar cells, and as a building block to vertical transistors. Graphene is a two-dimensional nanomaterial with vanishing density-of-states at the Dirac point, which differs from conventional metal. In this work, image-charge-induced barrier lowering (BL) in graphene-semiconductor contacts is studied and compared to that in metal Schottky contacts. The results show that despite of being a semimetal with vanishing density-of-states at the Dirac point, the image-charge-induced BL is significant. The BL value can be over 50% of that of metal contacts even in an intrinsic graphene contacted to an organic semiconductor, and it increases as the graphene doping increases. The dependences of the BL on the electric field and semiconductor dielectric constant are examined, and an empirical expression for estimating the image-charge-induced BL in graphene-semiconductor contacts is provided.

Keywords: graphene, semiconductor materials, schottky barrier, image charge, contacts

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Authors: Min-Hao Wang, Shih-Chih Chen

Abstract:

Recently, the merits such as simple structure, low power consumption, and compatibility with complementary metal oxide semiconductor (CMOS) process give an advantage of resistive random access memory (RRAM) as a promising candidate for the next generation memory， hafnium dioxide (HfO2) has been widely studied as an oxide layer material, but the use of copper (Cu) as both top and bottom electrodes has rarely been studied. In this study, radio frequency sputtering was used to deposit the intermediate layer HfO₂, and electron beam evaporation was used. For the upper and lower electrodes (cu), using different AR: O ratios, we found that the control of the metal filament will make the filament widely distributed, causing the current to rise to the limit current during Reset. However, if the flow ratio is controlled well, the ON/OFF ratio can reach 104, and the set voltage is controlled below 3v.

Keywords: RRAM, metal filament, HfO₂, Cu electrode

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Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

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In this paper, the transient device performance analysis of n-type Gate Inside Junctionless Transistor (GIJLT)has been evaluated. 3-D Bohm Quantum Potential (BQP)transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor(TGF) and unity gain cut-off frequency (fT) and subthreshold slope (SS) of the GI-JLT and Gate-all-around junctionless transistor(GAA-JLT) have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: gate-inside junctionless transistor GI-JLT, gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product

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Authors: F. Z. Mahi, H. Marinchio, C. Palermo, L. Varani

Abstract:

We propose an analytical approach for the admittance response calculation of the high mobility InGaAs channel transistors. The development of the small-signal admittance takes into account the longitudinal and transverse electric fields through a pseudo two-dimensional approximation of the Poisson equation. The total currents and the potentials matrix relation between the gate and the drain terminals determine the frequency-dependent small-signal admittance response. The analytical results show that the admittance spectrum exhibits a series of resonant peaks corresponding to the excitation of plasma waves. The appearance of the resonance is discussed and analyzed as functions of the channel length and the temperature. The model can be used, on one hand, to control the appearance of plasma resonances, and on the other hand, can give significant information about the admittance phase frequency dependence.

Keywords: small-signal admittance, Poisson equation, currents and potentials matrix, the drain and the gate terminals, analytical model

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Authors: Adonis Menezes, Julio C. Passos

Abstract:

The present work deals with the theoretical and experimental investigation of the convective boiling of CO₂ in macro and mini-channels. A review of the state of the art of convective boiling studies in mini-channels and conventional channels for operating with CO₂ was carried out, with special attention to the flow patterns and pressure drop maps in single-phase and two-phase flows. To carry out an experimental analysis of the convective boiling of CO₂, a properly instrumented experimental bench was built, which allows a parametric analysis for different thermodynamic conditions, such as mass velocities between 200 and 1300 kg/(m².s), pressures between 20 and 70bar, temperature monitoring at the entrance of the mini-channels, heat flow and pressure drop in the test section. The visualization of flow patterns was possible with the use of a high-speed CMOS camera. The results obtained are in line with those found in the literature, both for flow patterns and for the heat transfer coefficient.

Keywords: carbon dioxide, convective boiling, CO₂, mini-channels

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Authors: Pooja S. Billade, Sanjay S. Chopade

Abstract:

This paper focuses on the design of three phase induction motor control using single phase input and GSM.The controller used in this work is a wireless speed control using a GSM technique that proves to be very efficient and reliable in applications.The most common principle is the constant V/Hz principle which requires that the magnitude and frequency of the voltage applied to the stator of a motor maintain a constant ratio. By doing this, the magnitude of the magnetic field in the stator is kept at an approximately constant level throughout the operating range. Thus, maximum constant torque producing capability is maintained. The energy that a switching power converter delivers to a motor is controlled by Pulse Width Modulated signals applied to the gates of the power transistors in H-bridge configuration. PWM signals are pulse trains with fixed frequency and magnitude and variable pulse width. When a PWM signal is applied to the gate of a power transistor, it causes the turn on and turns off intervals of the transistor to change from one PWM period.

Keywords: index terms— PIC, GSM (global system for mobile), LCD (Liquid Crystal Display), IM (Induction Motor)

Procedia PDF Downloads 420