Search results for: RPC – RISC Processor Core

Authors: Iman Zangeneh, Mostafa Moradi, Mazyar Baranpouyan

Abstract:

System is using multiple processors for computing and information processing, is increasing rapidly speed operation of these systems compared with single processor systems, very significant impact on system performance is increased .important differences to yield a single multi-processor cpu, the scheduling policies, to reduce the implementation time of all processes. Notwithstanding the famous algorithms such as SPT, LPT, LSPT and RLPT for scheduling and there, but none led to the answer are not optimal.In this paper scheduling using genetic algorithms and innovative way to finish the whole process faster that we do and the result compared with three algorithms we mentioned.

Keywords: Multiprocessor system, genetic algorithms, time implementation process.

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Authors: K. Easawi, M. Nabil, T. Abdallah, S. Negm, H. Talaat

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Composite nanostructures of metal core/semiconductor shell (Au/CdS) configuration were prepared using organometalic method. UV-Vis spectra for the Au/CdS colloids show initially two well separated bands, corresponding to surface plasmon of the Au core, and the exciton of CdS shell. The absorption of CdS shell is enhanced, while the Au plasmon band is suppressed as the shell thickness increases. The shell sizes were estimated from the optical spectra using the effective mass approximation model (EMA), and compared to the sizes of the Au core and CdS shell measured by high resolution transmission electron microscope (HRTEM). The changes in the absorption features are discussed in terms of gradual increase in the coupling strength of the Au core surface plasmon and the exciton in the CdS. leading to charge transfer and modification of electron oscillation in Au core.

Keywords: Nanocomposites, Plasmonics.

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Authors: Shiji Hu, Lei Li, Wanting Zhou, Daohong Yang

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The data encryption is the foundation of today’s communication. On this basis, to improve the speed of data encryption and decryption is always an important goal for high-speed applications. This paper proposed an elliptic curve crypto processor architecture based on SM2 prime field. Regarding hardware implementation, we optimized the algorithms in different stages of the structure. For modulo operation on finite field, we proposed an optimized improvement of the Karatsuba-Ofman multiplication algorithm and shortened the critical path through the pipeline structure in the algorithm implementation. Based on SM2 recommended prime field, a fast modular reduction algorithm is used to reduce 512-bit data obtained from the multiplication unit. The radix-4 extended Euclidean algorithm was used to realize the conversion between the affine coordinate system and the Jacobi projective coordinate system. In the parallel scheduling point operations on elliptic curves, we proposed a three-level parallel structure of point addition and point double based on the Jacobian projective coordinate system. Combined with the scalar multiplication algorithm, we added mutual pre-operation to the point addition and double point operation to improve the efficiency of the scalar point multiplication. The proposed ECC hardware architecture was verified and implemented on Xilinx Virtex-7 and ZYNQ-7 platforms, and each 256-bit scalar multiplication operation took 0.275ms. The performance for handling scalar multiplication is 32 times that of CPU (dual-core ARM Cortex-A9).

Keywords: Elliptic curve cryptosystems, SM2, modular multiplication, point multiplication.

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Authors: Chih-Wei Hsieh, Chau-Yi Chou, Sheng-HsiuKuo, Tsung-Che Tsai, I-Chen Wu

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This paper presents the benchmarking results and performance evaluation of differentclustersbuilt atthe National Center for High-Performance Computingin Taiwan. Performance of processor, memory subsystem andinterconnect is a critical factor in the overall performance of high performance computing platforms. The evaluation compares different system architecture and software platforms. Most supercomputer used HPL to benchmark their system performance, in accordance with the requirement of the TOP500 List. In this paper we consider system memory access factors that affect benchmark performance, such as processor and memory performance.We hope these works will provide useful information for future development and construct cluster system.

Keywords: Performance Evaluation, Benchmarking and High-Performance Computing

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Authors: Hwan Su Jung, Ahn Jun Gil, Jong Tae Kim

Abstract:

Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

Keywords: Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.

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Authors: G.A.C.P. Ganegoda, D.M.A. Samaranayake, L.S. Bandara, K.A.D.N.K. Wimalawarne

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With the popularity of the multi-core and many-core architectures there is a great requirement for software frameworks which can support parallel programming methodologies. In this paper we introduce an Eclipse toolkit, JConqurr which is easy to use and provides robust support for flexible parallel progrmaming. JConqurr is a multi-core and many-core programming toolkit for Java which is capable of providing support for common parallel programming patterns which include task, data, divide and conquer and pipeline parallelism. The toolkit uses an annotation and a directive mechanism to convert the sequential code into parallel code. In addition to that we have proposed a novel mechanism to achieve the parallelism using graphical processing units (GPU). Experiments with common parallelizable algorithms have shown that our toolkit can be easily and efficiently used to convert sequential code to parallel code and significant performance gains can be achieved.

Keywords: Multi-core, parallel programming patterns, GPU, Java, Eclipse plugin, toolkit,

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Authors: G. Kim, R. Sterkenburg

Abstract:

One of the disadvantages of honeycomb sandwich structure is that they are prone to fluid intrusion. The purpose of this study is to determine if the structural properties of honeycomb core are affected by contact with a fluid. The test specimens were manufactured of fiberglass prepreg for the facesheets and Nomex^® honeycomb core for the core material in accordance with ASTM C-365/365M. Test specimens were soaked in several different kinds of fluids, such as aircraft fuel, turbine engine oil, hydraulic fluid, and water for a period of 60 days. A flatwise compressive test was performed, and the test results were analyzed to determine how the contact with aircraft fluids affected the compressive strength of the Nomex^® honeycomb core and how the strength was recovered when the specimens were dry. In addition, the investigation of de-bonding between facesheet and core material after soaking were performed to support the study.

Keywords: Debonding, environmental degradation, honeycomb sandwich structure.

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Authors: Choon Ki Ahn, Jung Hun Park, Wook Hyun Kwon

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CEMTool is a command style design and analyzing package for scientific and technological algorithm and a matrix based computation language. In this paper, we present new 2D & 3D finite element method (FEM) packages for CEMTool. We discuss the detailed structures and the important features of pre-processor, solver, and post-processor of CEMTool 2D & 3D FEM packages. In contrast to the existing MATLAB PDE Toolbox, our proposed FEM packages can deal with the combination of the reserved words. Also, we can control the mesh in a very effective way. With the introduction of new mesh generation algorithm and fast solving technique, our FEM packages can guarantee the shorter computational time than MATLAB PDE Toolbox. Consequently, with our new FEM packages, we can overcome some disadvantages or limitations of the existing MATLAB PDE Toolbox.

Keywords: CEMTool, Finite element method (FEM), Numericalanalysis, Partial differential equation (PDE)

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Authors: Fan-Yong Meng

Abstract:

In this paper, we first introduce the model of games on augmenting systems with a coalition structure, which can be seen as an extension of games on augmenting systems. The core of games on augmenting systems with a coalition structure is defined, and an equivalent form is discussed. Meantime, the Shapley function for this type of games is given, and two axiomatic systems of the given Shapley function are researched. When the given games are quasi convex, the relationship between the core and the Shapley function is discussed, which does coincide as in classical case. Finally, a numerical example is given.

Keywords: Cooperative game, augmenting system, Shapley function, core.

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Authors: Ezequiel Herruzo, Juan José Cruz, José Ignacio Benavides, Oscar Plata

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This paper describes a new algorithm of arrangement in parallel, based on Odd-Even Mergesort, called division and concurrent mixes. The main idea of the algorithm is to achieve that each processor uses a sequential algorithm for ordering a part of the vector, and after that, for making the processors work in pairs in order to mix two of these sections ordered in a greater one, also ordered; after several iterations, the vector will be completely ordered. The paper describes the implementation of the new algorithm on a Message Passing environment (such as MPI). Besides, it compares the obtained experimental results with the quicksort sequential algorithm and with the parallel implementations (also on MPI) of the algorithms quicksort and bitonic sort. The comparison has been realized in an 8 processors cluster under GNU/Linux which is running on a unique PC processor.

Keywords: Parallel algorithm, arrangement, MPI, sorting, parallel program.

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Authors: Nathar Shah, Visham Cheerkoot

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CScheme, a concurrent programming paradigm based on scheme concept enables concurrency schemes to be constructed from smaller synchronization units through a GUI based composer and latter be reused on other concurrency problems of a similar nature. This paradigm is particularly important in the multi-core environment prevalent nowadays. In this paper, we demonstrate techniques to separate concurrency from functional code using the CScheme paradigm. Then we illustrate how the CScheme methodology can be used to solve some of the traditional concurrency problems – critical section problem, and readers-writers problem - using synchronization schemes such as Single Threaded Execution Scheme, and Readers Writers Scheme.

Keywords: Concurrent Programming, Object Oriented Programming, Environments for multiple-processor systems, Programming paradigms.

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Authors: Yoshiaki Shikata, Nobutane Hanayama

Abstract:

We present a prioritized, limited multi-server processor sharing (PS) system where each server has various capacities, and N (≥2) priority classes are allowed in each PS server. In each prioritized, limited server, different service ratio is assigned to each class request, and the number of requests to be processed is limited to less than a certain number. Routing strategies of such prioritized, limited multi-server PS systems that take into account the capacity of each server are also presented, and a performance evaluation procedure for these strategies is discussed. Practical performance measures of these strategies, such as loss probability, mean waiting time, and mean sojourn time, are evaluated via simulation. In the PS server, at the arrival (or departure) of a request, the extension (shortening) of the remaining sojourn time of each request receiving service can be calculated by using the number of requests of each class and the priority ratio. Utilising a simulation program which executes these events and calculations, the performance of the proposed prioritized, limited multi-server PS rule can be analyzed. From the evaluation results, most suitable routing strategy for the loss or waiting system is clarified.

Keywords: Processor sharing, multi-server, various capacity, N priority classes, routing strategy, loss probability, mean sojourn time, mean waiting time, simulation.

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Authors: A. Melka, N. Slater, A. Mualem, Y. Louzoun

Abstract:

Networks are often presented as containing a “core” and a “periphery.” The existence of a core suggests that some vertices are central and form the skeleton of the network, to which all other vertices are connected. An alternative view of graphs is through communities. Multiple measures have been proposed for dense communities in graphs, the most classical being k-cliques, k-cores, and k-plexes, all presenting groups of tightly connected vertices. We here show that the edge number thresholds for such communities to emerge and for their percolation into a single dense connectivity component are very close, in all networks studied. These percolating cliques produce a natural core and periphery structure. This result is generic and is tested in configuration models and in real-world networks. This is also true for k-cores and k-plexes. Thus, the emergence of this connectedness among communities leading to a core is not dependent on some specific mechanism but a direct result of the natural percolation of dense communities.

Keywords: Networks, cliques, percolation, core structure, phase transition.

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Authors: Yoshiaki Shikata

Abstract:

Performance of a limited Round-Robin (RR) rule is studied in order to clarify the characteristics of a realistic sharing model of a processor. Under the limited RR rule, the processor allocates to each request a fixed amount of time, called a quantum, in a fixed order. The sum of the requests being allocated these quanta is kept below a fixed value. Arriving requests that cannot be allocated quanta because of such a restriction are queued or rejected. Practical performance measures, such as the relationship between the mean sojourn time, the mean number of requests, or the loss probability and the quantum size are evaluated via simulation. In the evaluation, the requested service time of an arriving request is converted into a quantum number. One of these quanta is included in an RR cycle, which means a series of quanta allocated to each request in a fixed order. The service time of the arriving request can be evaluated using the number of RR cycles required to complete the service, the number of requests receiving service, and the quantum size. Then an increase or decrease in the number of quanta that are necessary before service is completed is reevaluated at the arrival or departure of other requests. Tracking these events and calculations enables us to analyze the performance of our limited RR rule. In particular, we obtain the most suitable quantum size, which minimizes the mean sojourn time, for the case in which the switching time for each quantum is considered.

Keywords: Limited RR rule, quantum, processor sharing, sojourn time, performance measures, simulation, loss probability.

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Authors: Shu-Chiao Yang, Jong-Jiann Shieh

Abstract:

A Simultaneous Multithreading (SMT) Processor is capable of executing instructions from multiple threads in the same cycle. SMT in fact was introduced as a powerful architecture to superscalar to increase the throughput of the processor. Simultaneous Multithreading is a technique that permits multiple instructions from multiple independent applications or threads to compete limited resources each cycle. While the fetch unit has been identified as one of the major bottlenecks of SMT architecture, several fetch schemes were proposed by prior works to enhance the fetching efficiency and overall performance. In this paper, we propose a novel fetch policy called queue situation identifier (QSI) which counts some kind of long latency instructions of each thread each cycle then properly selects which threads to fetch next cycle. Simulation results show that in best case our fetch policy can achieve 30% on speedup and also can reduce the data cache level 1 miss rate.

Keywords: SMT, QSI, DL1 miss rate.

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Authors: Bindu Sankar, Jaideep Chakraborty, Rashmi Nawlakha, A. Venkatesan, S. Raghupathy, T. Jayanthi, S.A.V. Satya Murty

Abstract:

Component handling system is one of the important sub systems of Prototype Fast Breeder Reactor (PFBR) used for fuel handling. Core handling system is again a sub system of component handling system. Core handling system consists of in-vessel and ex-vessel subassembly handling. In-vessel core handling involves transfer arm, large rotatable plug and small rotatable plug operations. Modeling and simulation of in-vessel core handling is a part of development of Prototype Fast Breeder Reactor Operator Training Simulator. This paper deals with simulation and modeling of operations of transfer arm, large rotatable plug and small rotatable plug needed for in-vessel core handling. Process modeling was developed in house using platform independent Cµ code with OpenGL (Open Graphics Library). The control logic models and virtual panel were modeled using simulation tool.

Keywords: Animation, Core Handling System, Prototype Fast Breeder Reactor, Simulator

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Authors: Görkem Arslan Kılınç

Abstract:

Due to the high construction, operation, and maintenance costs of tall buildings, quantification of the area in the plan layout which provides a financial return is an important design criterion. The area of the “core and the structural system elements” does not provide financial return but must exist in the plan layout. Some characteristic items of tall office buildings affect the size of these areas. From this point of view, 15 tall office buildings were systematically investigated. The typical office floor plans of these buildings were re-produced digitally. The area of the “core and the structural system elements” in each building and the characteristic items of each building were calculated. These characteristic items are the size of the long and short plan edge, plan length/width ratio, size of the core long and short edge, core length/width ratio, core area, slenderness, building height, number of floors, and floor height. These items were analyzed by correlation and regression analyses. Results of this paper put forward that; characteristic items which affect the area of "core and structural system elements" are plan long and short edge size, core short edge size, building height, and the number of floors. A one-unit increase in plan short side size increases the area of the "core and structural system elements" in the plan by 12,378 m2. An increase in core short edge size increases the area of the core and structural system elements in the plan by 25,650 m2. Subsequent studies can be conducted by expanding the sample of the study and considering the geographical location of the building.

Keywords: Core area, correlation analysis, floor area, regression analysis, space efficiency, tall office buildings.

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Authors: Ginhsuan Li, Chiuyun Hung, Desheng Chen, Yiwen Wang

Abstract:

Application-Specific Instruction (ASI ) set Processors (ASIP) have become an important design choice for embedded systems due to runtime flexibility, which cannot be provided by custom ASIC solutions. One major bottleneck in maximizing ASIP performance is the limitation on the data bandwidth between the General Purpose Register File (GPRF) and ASIs. This paper presents the Implicit Registers (IRs) to provide the desirable data bandwidth. An ASI Input/Output model is proposed to formulate the overheads of the additional data transfer between the GPRF and IRs, therefore, an IRs allocation algorithm is used to achieve the better performance by minimizing the number of extra data transfer instructions. The experiment results show an up to 3.33x speedup compared to the results without using IRs.

Keywords: Application-Specific Instruction-set Processors, data bandwidth, configurable processor, implicit register.

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Authors: S. S. Pati, L. Herojit Singh, A. C. Oliveira, V. K. Garg

Abstract:

Chitosan functionalized Fe3O4-Au core shell nanoparticles have been prepared using a two-step wet chemical approach using NaBH4 as reducing agent for formation of Au in ethylene glycol. X-ray diffraction studies shows individual phases of Fe3O4 and Au in the as prepared samples with crystallite size of 5.9 and 11.4 nm respectively. The functionalization of the core-shell nanostructure with Chitosan has been confirmed using Fourier transform infrared spectroscopy along with signatures of octahedral and tetrahedral sites of Fe3O4 below 600cm-1. Mössbauer spectroscopy shows decrease in particle-particle interaction in presence of Au shell (72% sextet) than pure oleic coated Fe3O4 nanoparticles (88% sextet) at room temperature. At 80K, oleic acid coated Fe3O4 shows only sextets whereas the Chitosan functionalized Fe3O4 and Chitosan functionalized Fe3O4@Au core shell show presence of 5 and 11% doublet, respectively.

Keywords: Magnetic nanoparticles, Fe3O4@Au core shell, iron oxide, Au nanoparticles.

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Authors: Juntae Kim, Jaeyoung Park, Kyoungkun Lee, Jong Tae Kim

Abstract:

The H.264/AVC standard is a highly efficient video codec providing high-quality videos at low bit-rates. As employing advanced techniques, the computational complexity has been increased. The complexity brings about the major problem in the implementation of a real-time encoder and decoder. Parallelism is the one of approaches which can be implemented by multi-core system. We analyze macroblock-level parallelism which ensures the same bit rate with high concurrency of processors. In order to reduce the encoding time, dynamic data partition based on macroblock region is proposed. The data partition has the advantages in load balancing and data communication overhead. Using the data partition, the encoder obtains more than 3.59x speed-up on a four-processor system. This work can be applied to other multimedia processing applications.

Keywords: H.264/AVC, video coding, thread-level parallelism, OpenMP, multimedia

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Authors: Viriyavudh Sim, Woo Young Jung

Abstract:

This paper presents numerical analysis in terms of buckling resistance of GFRP sandwich infill panels system under the influence of increased temperature on the foam core. Failure mode under in-plane compression is studied by means of numerical analysis with ABAQUS platform. Parameters considered in this study are contact length and both the type of foam for core and the variation of its module elastic under the thermal influence. Increment of temperature is considered in static cases and only applied to core. Indeed, it is proven that the effect of temperature alters the mechanical properties of the entire panel system. Moreover, the rises of temperature result in a decrease in strength of the panel. This is due to the polymeric nature of this material. Additionally, the contact length also displays the effect on performance of infill panel. Their significance factors are based on type of polymer for core. Therefore, by comparing difference type of core material, the variation can be reducing.

Keywords: Buckling, contact length, foam core, temperature dependent.

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Authors: Halûk Gümüşkaya

Abstract:

In this paper we analyze the core issues affecting software architecture in enterprise projects where a large number of people at different backgrounds are involved and complex business, management and technical problems exist. We first give general features of typical enterprise projects and then present foundations of software architectures. The detailed analysis of core issues affecting software architecture in software development phases is given. We focus on three main areas in each development phase: people, process, and management related issues, structural (product) issues, and technology related issues. After we point out core issues and problems in these main areas, we give recommendations for designing good architecture. We observed these core issues and the importance of following the best software development practices and also developed some novel practices in many big enterprise commercial and military projects in about 10 years of experience.

Keywords: Software architecture, enterprise projects.

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Authors: Matthew Dickinson

Abstract:

A core/trunk exoskeleton design has been produced that is aimed to assist the raise to stand motion. A 3D model was produced to examine the use of additive manufacturing as a core method for producing structural components for the exoskeleton presented. The two materials that were modelled for this simulation work were Polylatic acid (PLA) and polyethylene terephthalate with carbon (PET-C), and the central spinal cord of the design being Nitrile rubber. The aim of this study was to examine the use of 3D printed materials as the main skeletal structure to support the core of a human when moving raising from a resting position. The objective in this work was to identify if the 3D printable materials could be offered as an equivalent alternative to conventional more expensive materials, thus allow for greater access for production for home maintenance. A maximum load of lift force was calculated, and this was incrementally reduced to study the effects on the material. The results showed a total number of 8 simulations were run to study the core in conditions with no muscular support through to 90% of operational support. The study presents work in the form of a core/trunk exoskeleton that presents 3D printing as a possible alternative to conventional manufacturing.

Keywords: 3D printing, Exo-Skeleton, PLA, PETC.

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Authors: Takeshi Takeda

Abstract:

A separate effect test (SET) simulated natural circulation (NC) under high core power condition of a pressurized water reactor (PWR) utilizing the ROSA/LSTF (rig of safety assessment/large-scale test facility). The LSTF test results clarified the relationship between the primary loop mass inventory and the primary loop mass flow rate being dependent on the NC mode at a constant core power of 8% of the volumetric-scaled PWR nominal power. When the core power was 9% or more during reflux condensation, large-amplitude level oscillation in a form of slow fill and dump occurred in steam generator (SG) U-tubes. At 11% core power during reflux condensation, intermittent rise took place in the cladding surface temperature of simulated fuel rods. The RELAP5/MOD3.3 code indicated the insufficient prediction of the SG U-tube liquid level behavior during reflux condensation.

Keywords: LSTF, natural circulation, core power, RELAP5.

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Authors: H. Ait Abderrahmane, M. Fayed, H. D. Ng, G. H. Vatistas

Abstract:

The present paper expands details and confirms the transition mechanism between two subsequent polygonal patterns of the hollow-core vortex. Using power spectral analysis, we confirm in this work that the transition from any N-gon to (N+1)-gon pattern observed within a hollow-core vortex of shallow rotating flows occurs in two steps. The regime was quasi-periodic before the frequencies lock (synchronization). The ratios of locking frequencies were found to be equal to (N-1)/N.

Keywords: Patterns, quasi-periodic, swirling, synchronization, transition.

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Authors: Manasi Pathade, Prachi Kadam, Renuka Kulkarni, Tejas Teredesai

Abstract:

In this paper, we propose a novel concept of relative distance measurement using Stereo Vision Technology and discuss its implementation on a FPGA based real-time image processor. We capture two images using two CCD cameras and compare them. Disparity is calculated for each pixel using a real time dense disparity calculation algorithm. This algorithm is based on the concept of indexed histogram for matching. Disparity being inversely proportional to distance (Proved Later), we can thus get the relative distances of objects in front of the camera. The output is displayed on a TV screen in the form of a depth image (optionally using pseudo colors). This system works in real time on a full PAL frame rate (720 x 576 active pixels @ 25 fps).

Keywords: Stereo Vision, Relative Distance Measurement, Indexed Histogram, Real time FPGA Image Processor

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Authors: Jayant V Kulkarni, Jayadevan R, Suresh N Mali, Hemant K Abhyankar, Raghunath S Holambe

Abstract:

The paper describes a new approach for fingerprint classification, based on the distribution of local features (minute details or minutiae) of the fingerprints. The main advantage is that fingerprint classification provides an indexing scheme to facilitate efficient matching in a large fingerprint database. A set of rules based on heuristic approach has been proposed. The area around the core point is treated as the area of interest for extracting the minutiae features as there are substantial variations around the core point as compared to the areas away from the core point. The core point in a fingerprint has been located at a point where there is maximum curvature. The experimental results report an overall average accuracy of 86.57 % in fingerprint classification.

Keywords: Minutiae distribution, Minutiae, Classification, Orientation, Heuristic.

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Authors: S. Jedari Salami

Abstract:

In this paper the effects of adding an extra layer within a sandwich panel and core- types in top and bottom cores on quasi- static loading are studied experimentally. The panel includes polymer composite laminated sheets for faces and the internal laminated sheet called extra layer sheet, and two types of crushable foams are selected as the core material. Quasi- static tests were done by ZWICK testing machine on fully backed specimens with two foam cores, Poly Urethane Rigid (PUR) and Poly Vinyl Chloride (PVC). It was found that the core material type has made significant role on improving the sandwich panel’s behavior compared with the effect of extra layer location.

Keywords: Multi-layer sandwich structures, Internal sheet, Crushable foam, Top core, Bottom core.

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Authors: Rashmi Priyadarshini, S. R. N. Reddy, R. M. Mehra

Abstract:

This paper presents one of the best applications of wireless sensor network for campus Monitoring. With the help of PIR sensor, temperature sensor and humidity sensor, effective utilization of energy resources has been implemented in one of rooms of Sharda University, Greater Noida, India. The RISC microcontroller is used here for analysis of output of sensors and providing proper control using ZigBee protocol. This wireless sensor module presents a tremendous power saving method for any campus

Keywords: PIC microcontroller, wireless sensor network, ZigBee.

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Authors: Irakli V. Gugushvili, Nickolay M. Evstigneev

Abstract:

Numerical integration of initial boundary problem for advection equation in 3 ℜ is considered. The method used is  conditionally stable semi-Lagrangian advection scheme with high order interpolation on unstructured mesh. In order to increase time step integration the BFECC method with limiter TVD correction is used. The method is adopted on parallel graphic processor unit environment using NVIDIA CUDA and applied in Navier-Stokes solver. It is shown that the calculation on NVIDIA GeForce 8800  GPU is 184 times faster than on one processor AMDX2 4800+ CPU. The method is extended to the incompressible fluid dynamics solver. Flow over a Cylinder for 3D case is compared to the experimental data.

Keywords: Advection equations, CUDA technology, Flow overthe 3D Cylinder, Incompressible Pressure Projection Solver, Parallel computation.

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