TY - JFULL AU - Ginhsuan Li and Chiuyun Hung and Desheng Chen and Yiwen Wang PY - 2011/6/ TI - Application-Specific Instruction Sets Processor with Implicit Registers to Improve Register Bandwidth T2 - International Journal of Computer and Information Engineering SP - 432 EP - 437 VL - 5 SN - 1307-6892 UR - https://publications.waset.org/pdf/13514 PU - World Academy of Science, Engineering and Technology NX - Open Science Index 53, 2011 N2 - Application-Specific Instruction (ASI ) set Processors (ASIP) have become an important design choice for embedded systems due to runtime flexibility, which cannot be provided by custom ASIC solutions. One major bottleneck in maximizing ASIP performance is the limitation on the data bandwidth between the General Purpose Register File (GPRF) and ASIs. This paper presents the Implicit Registers (IRs) to provide the desirable data bandwidth. An ASI Input/Output model is proposed to formulate the overheads of the additional data transfer between the GPRF and IRs, therefore, an IRs allocation algorithm is used to achieve the better performance by minimizing the number of extra data transfer instructions. The experiment results show an up to 3.33x speedup compared to the results without using IRs. ER -