Search results for: processor sharing

Authors: Amal Ezzidani, Abdelghani Ben Tahar, Mohamed Hanini

Abstract:

A sequence of finite tandem queue is considered for this study. Each one has a single server, which operates under the egalitarian processor sharing discipline. External customers arrive at each queue according to a renewal input process and having a general service times distribution. Upon completing service, customers leave the current queue and enter to the next. Under mild assumptions, including critical data, we prove the existence and the uniqueness of the fluid solution. For asymptotic behavior, we provide necessary and sufficient conditions for the invariant state and the convergence to this invariant state. In the end, we establish the convergence of a correctly normalized state process to a fluid limit characterized by a system of algebraic and integral equations.

Keywords: Fluid Limit, fluid model, measure valued process, processor sharing, tandem queue.

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Authors: Hamed Homaei, Iraj Mahdavi, Ali Tajdin

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One of the main concerns of miners is to increase the quality level of their products because the mining metals price depends on their quality level; however, increasing the quality level of these products has different costs at different levels of the supply chain. These costs usually increase after extractor level. This paper studies the coordination issue of a decentralized three-level supply chain with one supplier (extractor), one mineral processor and one manufacturer in which the increasing product quality level cost at the processor level is higher than the supplier and at the level of the manufacturer is more than the processor. We identify the optimal product quality level for each supply chain member by designing a revenue sharing contract. Finally, numerical examples show that the designed contract not only increases the final product quality level but also provides a win-win condition for all supply chain members and increases the whole supply chain profit.

Keywords: Three-stage supply chain, product quality improvement, channel coordination, revenue sharing.

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Authors: Yoshiaki Shikata, Nobutane Hanayama

Abstract:

We present a prioritized, limited multi-server processor sharing (PS) system where each server has various capacities, and N (≥2) priority classes are allowed in each PS server. In each prioritized, limited server, different service ratio is assigned to each class request, and the number of requests to be processed is limited to less than a certain number. Routing strategies of such prioritized, limited multi-server PS systems that take into account the capacity of each server are also presented, and a performance evaluation procedure for these strategies is discussed. Practical performance measures of these strategies, such as loss probability, mean waiting time, and mean sojourn time, are evaluated via simulation. In the PS server, at the arrival (or departure) of a request, the extension (shortening) of the remaining sojourn time of each request receiving service can be calculated by using the number of requests of each class and the priority ratio. Utilising a simulation program which executes these events and calculations, the performance of the proposed prioritized, limited multi-server PS rule can be analyzed. From the evaluation results, most suitable routing strategy for the loss or waiting system is clarified.

Keywords: Processor sharing, multi-server, various capacity, N priority classes, routing strategy, loss probability, mean sojourn time, mean waiting time, simulation.

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Authors: Kamaraju.M, Lal Kishore.K, Tilak.A.V.N

Abstract:

The general purpose processors that are used in embedded systems must support constraints like execution time, power consumption, code size and so on. On the other hand an Application Specific Instruction-set Processor (ASIP) has advantages in terms of power consumption, performance and flexibility. In this paper, a 16-bit Application Specific Instruction-set processor for the sensor data transfer is proposed. The designed processor architecture consists of on-chip transmitter and receiver modules along with the processing and controlling units to enable the data transmission and reception on a single die. The data transfer is accomplished with less number of instructions as compared with the general purpose processor. The ASIP core operates at a maximum clock frequency of 1.132GHz with a delay of 0.883ns and consumes 569.63mW power at an operating voltage of 1.2V. The ASIP is implemented in Verilog HDL using the Xilinx platform on Virtex4.

Keywords: ASIP, Data transfer, Instruction set, Processor

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Authors: Yoshiaki Shikata

Abstract:

Performance of a limited Round-Robin (RR) rule is studied in order to clarify the characteristics of a realistic sharing model of a processor. Under the limited RR rule, the processor allocates to each request a fixed amount of time, called a quantum, in a fixed order. The sum of the requests being allocated these quanta is kept below a fixed value. Arriving requests that cannot be allocated quanta because of such a restriction are queued or rejected. Practical performance measures, such as the relationship between the mean sojourn time, the mean number of requests, or the loss probability and the quantum size are evaluated via simulation. In the evaluation, the requested service time of an arriving request is converted into a quantum number. One of these quanta is included in an RR cycle, which means a series of quanta allocated to each request in a fixed order. The service time of the arriving request can be evaluated using the number of RR cycles required to complete the service, the number of requests receiving service, and the quantum size. Then an increase or decrease in the number of quanta that are necessary before service is completed is reevaluated at the arrival or departure of other requests. Tracking these events and calculations enables us to analyze the performance of our limited RR rule. In particular, we obtain the most suitable quantum size, which minimizes the mean sojourn time, for the case in which the switching time for each quantum is considered.

Keywords: Limited RR rule, quantum, processor sharing, sojourn time, performance measures, simulation, loss probability.

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Authors: Jae-Yeon Song, Seung-Yerl Lee, Kyu-Yeul Wang, Byung-Soo Kim, Sang-Seol Lee, Seong-Seob Shin, Jae-Young Choi, Chong Ho Lee, Jeahyun Park, Duck-Jin Chung

Abstract:

In this paper, we propose disease diagnosis hardware architecture by using Hypernetworks technique. It can be used to diagnose 3 different diseases (SPECT Heart, Leukemia, Prostate cancer). Generally, the disparate diseases require specified diagnosis hardware model for each disease. Using similarities of three diseases diagnosis processor, we design diagnosis processor that can diagnose three different diseases. Our proposed architecture that is combining three processors to one processor can reduce hardware size without decrease of the accuracy.

Keywords: Diagnosis processor, Hypernetworks, Leukemia, Mask, Prostate cancer, SPECT Heart data

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Authors: Yoshiaki Shikata, Wataru Katagiri, Yoshitaka Takahashi

Abstract:

We propose a novel prioritized limited processor-sharing (PS) rule and a simulation algorithm for the performance evaluation of this rule. The performance measures of practical interest are evaluated using this algorithm. Suppose that there are two classes and that an arriving (class-1 or class-2) request encounters n1 class-1 and n2 class-2 requests (including the arriving one) in a single-server system. According to the proposed rule, class-1 requests individually and simultaneously receive m / (m * n1+ n2) of the service-facility capacity, whereas class-2 requests receive 1 / (m *n1 + n2) of it, if m * n1 + n2 ≤ C. Otherwise (m * n1 + n2 > C), the arriving request will be queued in the corresponding class waiting room or rejected. Here, m (
1) denotes the priority ratio, and C ( ∞), the service-facility capacity. In this rule, when a request arrives at [or departs from] the system, the extension [shortening] of the remaining sojourn time of each request receiving service can be calculated using the number of requests of each class and the priority ratio. Employing a simulation program to execute these events and calculations enables us to analyze the performance of the proposed prioritized limited PS rule, which is realistic in a time-sharing system (TSS) with a sufficiently small time slot. Moreover, this simulation algorithm is expanded for the evaluation of the prioritized limited PS system with N
3 priority classes.

Keywords: PS rule, priority ratio, service-facility capacity, simulation algorithm, sojourn time, performance measures

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Authors: Yi-Pin Hsu, Shin-Yu Lin

Abstract:

In order to protect original data, watermarking is first consideration direction for digital information copyright. In addition, to achieve high quality image, the algorithm maybe can not run on embedded system because the computation is very complexity. However, almost nowadays algorithms need to build on consumer production because integrator circuit has a huge progress and cheap price. In this paper, we propose a novel algorithm which efficient inserts watermarking on digital image and very easy to implement on digital signal processor. In further, we select a general and cheap digital signal processor which is made by analog device company to fit consumer application. The experimental results show that the image quality by watermarking insertion can achieve 46 dB can be accepted in human vision and can real-time execute on digital signal processor.

Keywords: watermarking, digital signal processor, embedded system

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Authors: S. Roziana, R. Azizah, A.R. Hamidah

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This paper discusses the issues and challenge that academia faced in knowledge sharing at a research university in Malaysia. The partial results of interview are presented from the actual study. The main issues in knowledge sharing practices are university structure and designation and title. The academia awareness in sharing knowledge is also influenced by culture. Our investigation highlight that the concept of reciprocal relationship of sharing knowledge may hinder knowledge sharing awareness among academia. Hence, we concluded that further investigation could be carried out on the social interaction and trust culture among academia in sharing knowledge within research/ranking university environment.

Keywords: Knowledge sharing awareness, knowledge sharing practices, research university.

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Authors: Fariba Haghbin, Othman Bin Ibrahim, Mohammad Reza Attarzadeh Niaki

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With the development of virtual communities, there is an increase in the number of members in Virtual Communities (VCs). Many join VCs with the objective of sharing their knowledge and seeking knowledge from others. Despite the eagerness of sharing knowledge and receiving knowledge through VCs, there is no standard of assessing ones knowledge sharing capabilities and prospects of knowledge sharing. This paper developed a vector space model to assess the knowledge sharing prospect of VC users.

Keywords: Knowledge sharing network, Virtual community, knowledge relationship, Vector Space Model.

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Authors: Dchieche Amina, Aboulaich Rajae

Abstract:

Profit and loss sharing suggests an equitable sharing of risks and profits between the parts involved in a financial transaction. Salam is a contract in which advance payment is made for goods to be delivered at a future date. The purpose of this work is to price a new contract for profit and loss sharing based on Salam contract, using Khiyar Al Ghabn which is an agreement of choice in case of misrepresent facts.

Keywords: Islamic finance, Shariah compliance, profit and loss sharing, derivatives, risks, hedging, salam contract.

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Authors: Xiaoqing Wang, Fang Youyuan, Zheng Yanxing, Gu Tianyang, Zong Jianjian, Tong Jinrong

Abstract:

Compared with traditional distributed environment, the net-centric environment brings on more demanding challenges for information sharing with the characteristics of ultra-large scale and strong distribution, dynamic, autonomy, heterogeneity, redundancy. This paper realizes an information sharing model and a series of core services, through which provides an open, flexible and scalable information sharing platform.

Keywords: Net-centric environment, Information sharing, Metadata registry and catalog, Cross-domain data access control.

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Authors: Sajjad Rostami-Sani, Mojtaba Valinataj, Amir-Hossein Khojir-Angasi

Abstract:

The cache has an important role in the reduction of access delay between a processor and memory in high-performance embedded systems. In these systems, the energy consumption is one of the most important concerns, and it will become more important with smaller processor feature sizes and higher frequencies. Meanwhile, the cache system dissipates a significant portion of energy compared to the other components of a processor. There are some elements that can affect the energy consumption of the cache such as replacement policy and degree of associativity. Due to these points, it can be inferred that selecting an appropriate configuration for the cache is a crucial part of designing a system. In this paper, we investigate the effect of different cache replacement policies on both cache’s performance and energy consumption. Furthermore, the impact of different Instruction Set Architectures (ISAs) on cache’s performance and energy consumption has been investigated.

Keywords: L1-cache, energy consumption, replacement policy, Instruction set architecture, multicore processor.

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Authors: Marzena Świgoń

Abstract:

The purpose of this paper is to describe the perceptions of knowledge and information sharing by the Polish academic community. An electronic questionnaire was used to gather opinions of respondents. The presented results are a part of the findings of empirical studies carried out amongst academics from various types of universities and academia located throughout Poland.

Keywords: Academics, Information Sharing, Knowledge Sharing, Scholarly Communication.

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Authors: Sirous Panahi , Jason Watson , Helen Partridge

Abstract:

With the advent of social web initiatives, some argued that these new emerging tools might be useful in tacit knowledge sharing through providing interactive and collaborative technologies. However, there is still a poverty of literature to understand how and what might be the contributions of social media in facilitating tacit knowledge sharing. Therefore, this paper is intended to theoretically investigate and map social media concepts and characteristics with tacit knowledge creation and sharing requirements. By conducting a systematic literature review, five major requirements found that need to be present in an environment that involves tacit knowledge sharing. These requirements have been analyzed against social media concepts and characteristics to see how they map together. The results showed that social media have abilities to comply some of the main requirements of tacit knowledge sharing. The relationships have been illustrated in a conceptual framework, suggesting further empirical studies to acknowledge findings of this study.

Keywords: Knowledge sharing, Tacit knowledge, Social media, Web 2.0

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

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Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circuit. The nMPRA concept is a hardware processor with the scheduler implemented at the processor level; this is done without affecting a possible bus communication, as is the case with the other CPU solutions. The implementation of static or dynamic scheduling operations in hardware and the improvement of handling interrupts and events by the real-time executive described in the present article represent a key solution for eliminating the overhead of the operating system functions. The nMPRA processor is capable of executing a preemptive scheduling, using various algorithms without a software scheduler. Therefore, we have also presented various scheduling methods and algorithms used in scheduling the real-time tasks.

Keywords: nMPRA architecture, pipeline processor, preemptive scheduling, real-time system.

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Authors: M. Bogers, R. Beeres

Abstract:

This paper contributes to the literature concerning burden sharing. We provide a quantitative expression of the burden sharing behaviour of 174 states in the case of combating terrorist financing and address specific burden sharing issues in this context (i.e., weakest link; no substitutability). We conclude that advanced states have shown more effort to control terrorist financing than developing states. In this particular case, there is an incentive for advanced states to support developing states. Failing to do so will make the total financial system worse off.

Keywords: Burden sharing, combating terrorist financing, weakest link.

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Authors: Ying-Hueih Chen, Jyh-Jeng Wu, Shu-Hua Chien, Yui-Chuin Shiah

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Interorganizational knowledge sharing is the major driving force to maximize the operational benefits across supply chain. Trust is considered as the key to facilitate knowledge sharing. This research proposes shared values and relational embeddedness as antecedents of interorganizational trust. Survey based on managers in major industrial parks in Taiwan confirm that trust is enforced when organizations develop shared values and formed social relational embeddedness. Trust leads to interorganizational knowledge sharing. This research has theoretical and practical implications.

Keywords: Shared Goal, Relational Embeddedness, Trust, Knowledge Sharing.

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Authors: Noor Asilah Nordin, Normala Daud, Wan Ummi Kalsom Meor Osman

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This study applied Theory of Planned Behaviour (TPB) to explain the knowledge sharing behaviour among academic staff at a Public Higher Education Institution (HEI) in Malaysia. The main objectives of this study are; to identify the components that influence knowledge sharing behaviour and to determine the levels of knowledge sharing behaviour among academic staff. A total of 200 respondents were participated in answering questionnaires. The findings of this study revealed that level of perceiving and implementing knowledge sharing behaviour among academic staff at a Public HEI in Malaysia exist but not openly or strongly practiced. The findings were discussed and recommendations for the future research were also addressed.

Keywords: Attitude, Knowledge Sharing Behaviour, Perceived Behavioural Control, Subjective Norm.

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Authors: Feryal Aslani, Mohammad Mousakhani, Alireza Aslani

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One of the most important areas of knowledge management studies is knowledge sharing. Measured in terms of number of scientific articles and organization-s applications, knowledge sharing stands as an example of success in the field. This paper reviews the related papers in the context of the underlying individual behavioral variables to providea direction framework for future research and writing.

Keywords: future research, individual variables, knowledge sharing, organizational behavior

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Authors: Said Abdullah Al Saifi

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The goal of this research is to examine the impact of trust, motivation, and national culture on knowledge sharing within the context of electronic mail. This study is quantitative and survey based. In order to conduct the research, 200 students from a leading university in New Zealand were chosen randomly to participate in a questionnaire survey. Motivation and trust were found to be significantly and positively related to knowledge sharing. The research findings illustrated that face saving, face gaining, and individualism positively moderates the relationship between motivation and knowledge sharing. In addition, collectivism culture negatively moderates the relationship between motivation and knowledge sharing. Moreover, the research findings reveal that face saving, individualism, and collectivism culture positively moderate the relationship between trust and knowledge sharing. In addition, face gaining culture negatively moderates the relationship between trust and knowledge sharing. This study sets out several implications for researchers and practitioners. The study produces an integrative model that shows how attributes of national culture impact knowledge sharing through the use of emails. A better understanding of the relationship between knowledge sharing and trust, motivation, and national culture differences will increase individuals’ ability to make wise choices when sharing knowledge with those from different cultures.

Keywords: Knowledge sharing, motivation, national culture, trust.

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Authors: Sang Su Lee, Sang Woo Lee, Yong Sung Jeon, Ki Young Kim

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IPsec protocol[1] is a set of security extensions developed by the IETF and it provides privacy and authentication services at the IP layer by using modern cryptography. In this paper, we describe both of H/W and S/W architectures of our router system, SRS-10. The system is designed to support high performance routing and IPsec VPN. Especially, we used Cavium-s CN2560 processor to implement IPsec processing in inline-mode.

Keywords: IP, router, VPN, IPsec.

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Authors: Yi-Pin Hsu, Shin-Yu Lin

Abstract:

An efficient parallel form in digital signal processor can improve the algorithm performance. The butterfly structure is an important role in fast Fourier transform (FFT), because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even though recent research which call as novel memory reference reduction methods (NMRRM) for FFT focus on reduce memory reference in twiddle factor, the data-dependent property still exists. In this paper, we propose a parallel-computing approach for FFT implementation on digital signal processor (DSP) which is based on data-independent property and still hold the property of low-memory reference. The proposed method combines final two steps in NMRRM FFT to perform a novel data-independent structure, besides it is very suitable for multi-operation-unit digital signal processor and dual-core system. We have applied the proposed method of radix-2 FFT algorithm in low memory reference on TI TMSC320C64x DSP. Experimental results show the method can reduce 33.8% clock cycles comparing with the NMRRM FFT implementation and keep the low-memory reference property.

Keywords: Parallel-computing, FFT, low-memory reference, TIDSP.

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Authors: Hui-Jae You, Sun-Tae Chung, Souhwan Jung

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SAD (Sum of Absolute Difference) algorithm is heavily used in motion estimation which is computationally highly demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an efficient implementation of SAD algorithm on the VLIW processor is essential. SAD algorithm is programmed as a nested loop with a conditional branch. In VLIW processors, loop is usually optimized by software pipelining, but researches on optimal scheduling of software pipelining for nested loops, especially nested loops with conditional branches are rare. In this paper, we propose an optimal scheduling and implementation of SAD algorithm with conditional branch on a VLIW DSP processor. The proposed optimal scheduling first transforms the nested loop with conditional branch into a single loop with conditional branch with consideration of full utilization of ILP capability of the VLIW processor and realization of earlier escape from the loop. Next, the proposed optimal scheduling applies a modulo scheduling technique developed for single loop. Based on this optimal scheduling strategy, optimal implementation of SAD algorithm on TMS320C67x, a VLIW DSP is presented. Through experiments on TMS320C6713 DSK, it is shown that H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations, and that the code size of the optimal SAD implementation is small enough to be appropriate for embedded environments.

Keywords: Optimal implementation, SAD algorithm, VLIW, TMS320C6713.

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Authors: Erh-Wen Hu, Cyril S. Ku, Andrew T. Russo, Bogong Su, Jian Wang

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Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an application, processor performance is usually the major concern for digital signal processing (DSP) application developers. Performance data are also essential for the designers of DSP processors to improve their design. Consequently, several DSP performance benchmarks have been proposed over the past decade or so. However, none of these benchmarks seem to have included recent new DSP applications. In this paper, we use a new benchmark that we recently developed to compare the performance of popular DSP processors from Texas Instruments and StarCore. The new benchmark is based on the Selectable Mode Vocoder (SMV), a speech-coding program from the recent third generation (3G) wireless voice applications. All benchmark kernels are compiled by the compilers of the respective DSP processors and run on their simulators. Weighted arithmetic mean of clock cycles and arithmetic mean of code size are used to compare the performance of five DSP processors. In addition, we studied how the performance of a processor is affected by code structure, features of processor architecture and optimization of compiler. The extensive experimental data gathered, analyzed, and presented in this paper should be helpful for DSP processor and compiler designers to meet their specific design goals.

Keywords: digital signal processors, DSP benchmark, instruction level parallelism, modified cyclomatic complexity, performance analysis.

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Authors: Mohammad S. Laghari, Gulzar A. Khuwaja

Abstract:

Many problems in computer vision and image processing present potential for parallel implementations through one of the three major paradigms of geometric parallelism, algorithmic parallelism and processor farming. Static process scheduling techniques are used successfully to exploit geometric and algorithmic parallelism, while dynamic process scheduling is better suited to dealing with the independent processes inherent in the process farming paradigm. This paper considers the application of parallel or multi-computers to a class of problems exhibiting spatial data characteristic of the geometric paradigm. However, by using processor farming paradigm, a dynamic scheduling technique is developed to suit the MIMD structure of the multi-computers. A hybrid scheme of scheduling is also developed and compared with the other schemes. The specific problem chosen for the investigation is the Hough transform for line detection.

Keywords: Hough transforms, parallel computer, parallel paradigms, scheduling.

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Authors: Ulrich Berger, Yuliya Lebedynska, Veronica Vargas

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The right information at the right time influences the enterprise and technical success. Sharing knowledge among members of a big organization may be a complex activity. And as long as the knowledge is not shared, can not be exploited by the organization. There are some mechanisms which can originate knowledge sharing. It is intended, in this paper, to trigger these mechanisms by using semantic nets. Moreover, the intersection and overlapping of terms and sub-terms, as well as their relationships will be described through the mereology science for the whole knowledge sharing system. It is proposed a knowledge system to supply to operators with the right information about a specific process and possible risks, e.g. at the assembly process, at the right time in an automated manufacturing environment, such as at the automotive industry.

Keywords: Automated manufacturing, knowledge sharing, mereology, risk management, semantic net.

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Authors: S. Abdallah, A. Khalil, A. Divine

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The purpose of this study was to explore the relationship between knowledge sharing and innovation capability, by examining the influence of individual, organizational and technological factors on knowledge sharing. The research is based on a survey of 103 employees from different organizations in the United Arab Emirates. The study is based on a model and a questionnaire that was previously tested by Lin [1]. Thus, the study aims at examining the validity of that model in UAE context. The results of the research show varying degrees of correlation between the different variables, with ICT use having the strongest relationship with the innovation capabilities of organizations. The study also revealed little evidence of knowledge collecting and knowledge sharing among UAE employees.

Keywords: Knowledge sharing, Organization Innovation, Technology Use, Innovation Capabilities.

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Authors: Szu-Yuan Sun, Teresa L. Ju, Hao-Fan Chumg, Chang-Yao Wu, Pei-Ju Chao

Abstract:

Despite the fact that Knowledge Sharing (KS) is very important, we found only little discussion about the reasons why people have the willingness to share knowledge at such platform even though there is no immediate benefit to the persons who contribute knowledge in it. The aim of this study is to develop an integrative understanding of the factors that support or inhibit individuals- knowledge sharing intentions in virtual communities and to find whether habit would generate people-s willingness to be involved. We apply Social Capital Theory (SCT), and we also add two dimensions for discussion: member incentive and habitual domain (HD). This research assembles the questionnaire from individuals who have experienced knowledge sharing in virtual communities, and applies survey and Structural Equation Model (SEM) to analyze the results from the questionnaires. Finally, results confirm that individuals are willing to share knowledge in virtual communities: (1) if they consider reciprocity, centrality, and have longer tenure in their field, and enjoy helping. (2) if they have the habit of sharing knowledge. This study is useful for the developers of virtual communities to insight into knowledge sharing in cyberspace.

Keywords: Habitual domains, knowledge sharing, social capital theory, virtual community.

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Authors: Toshitaka Higashino, Naoki Wakamiya

Abstract:

Human beings perform a task by perceiving information from outside, recognizing them, and responding them. There have been various attempts to analyze and understand internal processes behind the reaction to a given stimulus by conducting psychological experiments and analysis from multiple perspectives. Among these, we focused on Model Human Processor (MHP). However, it was built based on psychological experiments and thus the relation with brain activity was unclear so far. To verify the validity of the MHP and propose our model from a viewpoint of neuroscience, EEG (Electroencephalography) measurements are performed during experiments in this study. More specifically, first, experiments were conducted where Latin alphabet characters were used as visual stimuli. In addition to response time, ERPs (event-related potentials) such as N100 and P300 were measured by using EEG. By comparing cycle time predicted by the MHP and latency of ERPs, it was found that N100, related to perception of stimuli, appeared at the end of the perceptual processor. Furthermore, by conducting an additional experiment, it was revealed that P300, related to decision making, appeared during the response decision process, not at the end. Second, by experiments using Japanese Hiragana characters, i.e. Japan's own phonetic symbols, those findings were confirmed. Finally, Japanese Kanji characters were used as more complicated visual stimuli. A Kanji character usually has several readings and several meanings. Despite the difference, a reading-related task and a meaning-related task exhibited similar results, meaning that they involved similar information processing processes of the brain. Based on those results, our model was proposed which reflects response time and ERP latency. It consists of three processors: the perception processor from an input of a stimulus to appearance of N100, the cognitive processor from N100 to P300, and the decision-action processor from P300 to response. Using our model, an application system which reflects brain activity can be established.

Keywords: Brain activity, EEG, information processing model, model human processor.

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