Search results for: RLC short circuit

Authors: K. A. Sumitra Devi, N. P. Banashree, Annamma Abraham

Abstract:

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its often essential to sub-divide multi -million transistor design into manageable Pieces. This paper looks at the various partitioning techniques aspects of VLSI CAD, targeted at various applications. We proposed an evolutionary time-series model and a statistical glitch prediction system using a neural network with selection of global feature by making use of clustering method model, for partitioning a circuit. For evolutionary time-series model, we made use of genetic, memetic & neuro-memetic techniques. Our work focused in use of clustering methods - K-means & EM methodology. A comparative study is provided for all techniques to solve the problem of circuit partitioning pertaining to VLSI design. The performance of all approaches is compared using benchmark data provided by MCNC standard cell placement benchmark net lists. Analysis of the investigational results proved that the Neuro-memetic model achieves greater performance then other model in recognizing sub-circuits with minimum amount of interconnections between them.

Keywords: VLSI, circuit partitioning, memetic algorithm, genetic algorithm.

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Authors: E. Farshidi

Abstract:

This paper presents a new general technique for analysis of noise in static log-domain translinear circuits. It is demonstrated that employing this technique, leads to a general, simple and routine method of the noise analysis. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.

Keywords: Noise analysis, log-domain, static, dynamic, translinear loop, companding.

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Authors: Ridha Salhi, Mondher Labidi, Fethi Choubani

Abstract:

Metamaterials have attracted much attention in recent years because of their electromagnetic exquisite proprieties. We will present, in this paper, the modeling of three metamaterial structures by equivalent circuit model. We begin by modeling the SRR (Split Ring Resonator), then we model the HIS (High Impedance Surfaces), and finally, we present the model of the CPW (Coplanar Wave Guide). In order to validate models, we compare the results obtained by an equivalent circuit models with numerical simulation.

Keywords: Metamaterials, SRR, HIS, CPW, IDC.

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Authors: S. Abdollahi Pour, M. Saneei

Abstract:

This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 10 μW for 32nm technology and about 12 μW for 65nm technology at the same power supply voltage as the core power supply. Moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop.

Keywords: leakage current, leakage power monitor, body biasing, low power

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Authors: Anamika Jain, A. S. Thoke, R. N. Patel

Abstract:

This paper addresses the problems encountered by conventional distance relays when protecting double-circuit transmission lines. The problems arise principally as a result of the mutual coupling between the two circuits under different fault conditions; this mutual coupling is highly nonlinear in nature. An adaptive protection scheme is proposed for such lines based on application of artificial neural network (ANN). ANN has the ability to classify the nonlinear relationship between measured signals by identifying different patterns of the associated signals. One of the key points of the present work is that only current signals measured at local end have been used to detect and classify the faults in the double circuit transmission line with double end infeed. The adaptive protection scheme is tested under a specific fault type, but varying fault location, fault resistance, fault inception angle and with remote end infeed. An improved performance is experienced once the neural network is trained adequately, which performs precisely when faced with different system parameters and conditions. The entire test results clearly show that the fault is detected and classified within a quarter cycle; thus the proposed adaptive protection technique is well suited for double circuit transmission line fault detection & classification. Results of performance studies show that the proposed neural network-based module can improve the performance of conventional fault selection algorithms.

Keywords: Double circuit transmission line, Fault detection and classification, High impedance fault and Artificial Neural Network.

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Authors: Hassan Ghasemzadeh, Sepideh Mazrouee, Hassan Goldani Moghaddam, Hamid Shojaei, Mohammad Reza Kakoee

Abstract:

Block replacement algorithms to increase hit ratio have been extensively used in cache memory management. Among basic replacement schemes, LRU and FIFO have been shown to be effective replacement algorithms in terms of hit rates. In this paper, we introduce a flexible stack-based circuit which can be employed in hardware implementation of both LRU and FIFO policies. We propose a simple and efficient architecture such that stack-based replacement algorithms can be implemented without the drawbacks of the traditional architectures. The stack is modular and hence, a set of stack rows can be cascaded depending on the number of blocks in each cache set. Our circuit can be implemented in conjunction with the cache controller and static/dynamic memories to form a cache system. Experimental results exhibit that our proposed circuit provides an average value of 26% improvement in storage bits and its maximum operating frequency is increased by a factor of two

Keywords: Cache Memory, Replacement Algorithms, LeastRecently Used Algorithm, First In First Out Algorithm.

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Authors: H. Mazouz, A. Belghachi, F. Hadjaj

Abstract:

Solar cells used in orbit are exposed to radiation environment mainly protons and high energy electrons. These particles degrade the output parameters of the solar cell. The aim of this work is to characterize the effects of electron irradiation fluence on the J (V) characteristic and output parameters of GaAs solar cell by numerical simulation. The results obtained demonstrate that the electron irradiation-induced degradation of performances of the cells concerns mainly the short circuit current

Keywords: GaAs solar cell, 1MeV electron irradiation, irradiation fluence.

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Authors: Gulshan Sachdeva, Vaibhav Jain, S. S. Kachhwaha

Abstract:

Cascade refrigeration systems employ series of single stage vapor compression units which are thermally coupled with evaporator/condenser cascades. Different refrigerants are used in each of the circuit depending on the optimum characteristics shown by the refrigerant for a particular application. In the present research study, a steady state thermodynamic model is developed which simulates the working of an actual cascade system. The model provides COP and all other system parameters e.g. total compressor work, temperature, pressure, enthalpy and entropy at different state points. The working fluid in low temperature circuit (LTC) is CO₂ (R744) while Ammonia (R717), Propane (R290), Propylene (R1270), R404A and R12 are the refrigerants in high temperature circuit (HTC). The performance curves of Ammonia, Propane, Propylene, and R404A are compared with R12 to find its nearest substitute. Results show that Ammonia is the best substitute of R12.

Keywords: Cascade system, Refrigerants, Thermodynamic model.

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Authors: Aaron J. Small, Craig A. Fletcher

Abstract:

This study investigates the effect of closed circuit television (CCTV) image patch layout on performance of a simulated train-platform departure task. The within-subjects experimental design measures target detection rate and response latency during a CCTV visual search task conducted as part of the procedure for safe train dispatch. Three interface designs were developed by manipulating CCTV image patch layout. Eye movements, perceived workload and system usability were measured across experimental conditions. Task performance was compared to identify significant differences between conditions. The results of this study have not been determined.

Keywords: Rail human factors, workload, closed circuit television, platform departure, attention, information processing, interface design.

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Authors: Amit Sachan

Abstract:

The purpose of this paper is to acquire the remote electrical parameters like Voltage, Current, and Frequency from Smart grid and send these real time values over GSM network using GSM Modem/phone along with temperature at power station. This project is also designed to protect the electrical circuitry by operating an Electromagnetic Relay. The Relay can be used to operate a Circuit Breaker to switch off the main electrical supply. User can send commands in the form of SMS messages to read the remote electrical parameters. This system also can automatically send the real time electrical parameters periodically (based on time settings) in the form of SMS. This system also send SMS alerts whenever the Circuit Breaker trips or whenever the Voltage or Current exceeds the predefined limits.

Keywords: GSM Modem, Initialization of ADC module of microcontroller, PIC-C compiler for Embedded C programming, PIC kit 2 programmer for dumping code into Micro controller, Express SCH for Circuit design, Proteus for hardware simulation.

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Authors: Radhika Ambatipudi, Hari Babu Kotte, Dr. Kent Bertilsson

Abstract:

In this paper, multilayered coreless printed circuit board (PCB) step-down power transformers for DC-DC converter applications have been designed, manufactured and evaluated. A set of two different circular spiral step-down transformers were fabricated in the four layered PCB. These transformers have been modelled with the assistance of high frequency equivalent circuit and characterized with both sinusoidal and square wave excitation. This paper provides the comparative results of these two different transformers in terms of their resistances, self, leakage, mutual inductances, coupling coefficient and also their energy efficiencies. The operating regions for optimal performance of these transformers for power transfer applications are determined. These transformers were tested for the output power levels of about 30 Watts within the input voltage range of 12-50 Vrms. The energy efficiency for these step down transformers is observed to be in the range of 90%-97% in MHz frequency region.

Keywords: Coreless Step down Transformer, DC-DC Converterapplications, High frequency transformer, MHz operating frequency, Multilayered PCB transformers, Power Transfer Applications.

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Authors: Christos Meletis, Paul Bougas, George Economakos , Paraskevas Kalivas, Kiamal Pekmestzi

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In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.

Keywords: Digital signal processing, systolic circuits, FFTalgorithm.

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Authors: Ming-Chu Yin, Ping-An Du

Abstract:

The shielding ability of a shielding cavity with an aperture will be greatly degraded at resonance frequencies, and the resonance modes and frequencies are affected by aperture resonances and aperture-cavity coupling, which are closely related with aperture sizes. The equivalent circuit method and numerical method of Transmission Line Matrix (TLM) are used to analyze the effects of aperture resonances and aperture-cavity coupling on the electromagnetic resonances of a cavity with an aperture in this paper. Both analytical and numerical results show that the resonance modes of a shielding cavity with an aperture consist of cavity resonance modes and aperture resonance modes, and the resonance frequencies will shift with the change of the aperture sizes because of the aperture resonances and aperture-cavity coupling. Variation rules of electromagnetic resonances with aperture sizes for a cavity with an aperture are given, which will be useful for design of shielding cavities.

Keywords: Aperture-cavity coupling, equivalent circuit method, resonances, shielding equipment.

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Authors: Z. Dibi, F. Djeffal, N. Lakhdar

Abstract:

In this paper, we have developed an explicit analytical drain current model comprising surface channel potential and threshold voltage in order to explain the advantages of the proposed Gate Stack Double Diffusion (GSDD) MOSFET design over the conventional MOSFET with the same geometric specifications that allow us to use the benefits of the incorporation of the high-k layer between the oxide layer and gate metal aspect on the immunity of the proposed design against the self-heating effects. In order to show the efficiency of our proposed structure, we propose the simulation of the power chopper circuit. The use of the proposed structure to design a power chopper circuit has showed that the (GSDD) MOSFET can improve the working of the circuit in terms of power dissipation and self-heating effect immunity. The results so obtained are in close proximity with the 2D simulated results thus confirming the validity of the proposed model.

Keywords: Double-Diffusion, modeling, MOSFET, power.

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Authors: López-Gutiérrez R.M., Rodríguez-Orozco E., Cruz-Hernández C., Inzunza-González E., Posadas-Castillo C., García-Guerrero E.E., Cardoza-Avendaño L.

Abstract:

In this paper, we use Generalized Hamiltonian systems approach to synchronize a modified sixth-order Chua's circuit, which generates hyperchaotic dynamics. Synchronization is obtained between the master and slave dynamics with the slave being given by an observer. We apply this approach to transmit private information (analog and binary), while the encoding remains potentially secure.

Keywords: Hyperchaos synchronization, sixth-order Chua's circuit, observers, simulation, secure communication.

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Authors: Marios N. Moschakis

Abstract:

This paper deals with the assessment of faulted area around an industrial customer connected to a particular electric grid that will cause a certain sag magnitude on this customer. The faulted (critical or exposed) area’s length is calculated by adding all line lengths in the neighborhood of the critical node (customer). The applied method is the so-called Method of Critical Distances. By using advanced short-circuit analysis, the Critical Area can be accurately calculated for radial and meshed power networks due to all symmetrical and asymmetrical faults. For the demonstration of the effectiveness of the proposed methodology, a study case is used.

Keywords: Critical area, fault-induced voltage sags, industrial customers, power quality.

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Authors: G. Martemucci, D. Casamassima, A. G. D'Alessandro

Abstract:

The study aimed to evaluated the reproductive performance response to short term oestrus synchronization during the transition period. One hundred and sixty-five indigenous multiparous non-lactating goats were subdivided into the following six treatment groups for oestrus synchronization: NT control Group (N= 30), Fe-21d, FGA vaginal sponge for 21days+eCG at 19thd; FPe- 11d, FGA 11d + PGF2α and eCG at 9th d; FPe-10d, FGA 10d+ PGF2α and eCG at 8th d; FPe-9d, FGA 9d +PGF2α and eCG at 7thd; PFe-5d, PGF2α at d0 + FGA 5d + eCG at 5thd. The goats were natural mated (1 male/6 females). Fecundity rates (n. births /n. females treated x 100) were statistically higher (P < 0.05) in short term FPe-9d (157.9%), FPe- 11d (115.4%), FPe-10d (111.1%) and PFe-5d (107.7%) groups compared to the NT control Group (66.7%).

Keywords: Goats, oestrus synchronization, short-term protocols.

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Authors: Namal A. Senanayake, Khoo B. How, Quah W. Wai

Abstract:

In this project, a tele-operated anthropomorphic robotic arm and hand is designed and built as a versatile robotic arm system. The robot has the ability to manipulate objects such as pick and place operations. It is also able to function by itself, in standalone mode. Firstly, the robotic arm is built in order to interface with a personal computer via a serial servo controller circuit board. The circuit board enables user to completely control the robotic arm and moreover, enables feedbacks from user. The control circuit board uses a powerful integrated microcontroller, a PIC (Programmable Interface Controller). The PIC is firstly programmed using BASIC (Beginner-s All-purpose Symbolic Instruction Code) and it is used as the 'brain' of the robot. In addition a user friendly Graphical User Interface (GUI) is developed as the serial servo interface software using Microsoft-s Visual Basic 6. The second part of the project is to use speech recognition control on the robotic arm. A speech recognition circuit board is constructed with onboard components such as PIC and other integrated circuits. It replaces the computers- Graphical User Interface. The robotic arm is able to receive instructions as spoken commands through a microphone and perform operations with respect to the commands such as picking and placing operations.

Keywords: Tele-operated Anthropomorphic Robotic Arm and Hand, Robot Motion System, Serial Servo Controller, Speech Recognition Controller.

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Authors: Jinghao Sun, Guozhen Tan, Guangjian Hou

Abstract:

The Chinese Postman Problem (CPP) is one of the classical problems in graph theory and is applicable in a wide range of fields. With the rapid development of hybrid systems and model based testing, Chinese Postman Problem with Time Dependent Travel Times (CPPTDT) becomes more realistic than the classical problems. In the literature, we have proposed the first integer programming formulation for the CPPTDT problem, namely, circuit formulation, based on which some polyhedral results are investigated and a cutting plane algorithm is also designed. However, there exists a main drawback: the circuit formulation is only available for solving the special instances with all circuits passing through the origin. Therefore, this paper proposes a new integer programming formulation for solving all the general instances of CPPTDT. Moreover, the size of the circuit formulation is too large, which is reduced dramatically here. Thus, it is possible to design more efficient algorithm for solving the CPPTDT in the future research.

Keywords: Chinese Postman Problem, Time Dependent, Integer Programming, Upper Bound Analysis.

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Authors: Sun-Ki Hong, Yong-Ho Cho, Ki-Seok Kim, Tae-Sam Kang

Abstract:

Piezoelectric actuator is treated as RC load when it is modeled electrically. For some piezoelectric actuator applications, arbitrary voltage is required to actuate. Especially for unidirectional arbitrary voltage driving like as sine wave, some special inverter with circuit that can charge and discharge the capacitive energy can be used. In this case, the difference between power supply level and the object voltage level for RC load is varied. Because the control gain is constant, the controlled output is not uniform according to the voltage difference. In this paper, for charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator, the controller gain is controlled according to the voltage difference. With the proposed simple idea, the load voltage can have controlled smoothly although the voltage difference is varied. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: Analog voltage inverter, Capacitive load, Gain control, DC-DC converter, Piezoelectric, Voltage waveform.

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Authors: Konstantin Movsovic, Emanuele Stomeo, Tatiana Kalganova

Abstract:

The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

Keywords: Evolvable hardware, evolutionary algorithm, digitallogic circuit, mutation rate.

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Authors: Jackson H. W. Chang, Jedol Dayou, Justin Sentian

Abstract:

Long terms variation of solar insolation had been widely studied. However, its parallel observations in short time scale is rather lacking. This paper aims to investigate the short time scale evolution of solar radiation spectrum (UV, PAR, and NIR bands) due to atmospheric aerosols and water vapors. A total of 25 days of global and diffused solar spectrum ranges from air mass 2 to 6 were collected using ground-based spectrometer with shadowband technique. The result shows that variation of solar radiation is the least in UV fraction, followed by PAR and the most in NIR. Broader variations in PAR and NIR are associated with the short time scale fluctuations of aerosol and water vapors. The corresponding daily evolution of UV, PAR, and NIR fractions implies that aerosol and water vapors variation could also be responsible for the deviation pattern in the Langley-plot analysis.

Keywords: Aerosol, short time scale variation, solar radiation, water vapor.

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Authors: Mehdi Moayyedian, Kazem Abhary, Romeo Marian

Abstract:

This paper presents an evaluation of a plastic defect in injection molding before it occurs in the process; it is known as the short shot defect. The evaluation of different parameters which affect the possibility of short shot defect is the aim of this paper. The analysis of short shot possibility is conducted via SolidWorks Plastics and Taguchi method to determine the most significant parameters. Finite Element Method (FEM) is employed to analyze two circular flat polypropylene plates of 1 mm thickness. Filling time, part cooling time, pressure holding time, melt temperature and gate type are chosen as process and geometric parameters, respectively. A methodology is presented herein to predict the possibility of the short-shot occurrence. The analysis determined melt temperature is the most influential parameter affecting the possibility of short shot defect with a contribution of 74.25%, and filling time with a contribution of 22%, followed by gate type with a contribution of 3.69%. It was also determined the optimum level of each parameter leading to a reduction in the possibility of short shot are gate type at level 1, filling time at level 3 and melt temperature at level 3. Finally, the most significant parameters affecting the possibility of short shot were determined to be melt temperature, filling time, and gate type.

Keywords: Injection molding, plastic defects, short shot, Taguchi method.

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Authors: K. Echchakhaoui, E. Abdelmounim, J. Zbitou, H. Bennis, N. Ababssi, M. Latrach

Abstract:

In this paper a new design of a broadband microwave power limiter is presented and validated into simulation by using ADS software (Advanced Design System) from Agilent technologies. The final circuit is built on microstrip lines by using identical Zero Bias Schottky diodes. The power limiter is designed by Associating 3 stages Schottky diodes. The obtained simulation results permit to validate this circuit with a threshold input power level of 0 dBm until a maximum input power of 30 dBm.

Keywords: Limiter, microstrip, zero-biais.

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Authors: Lei Yao, Jia Hao Cheong, Rui-Feng Xue, Minkyu Je

Abstract:

A closed-loop controlled wireless power transmission circuit block for implantable biomedical applications is described in this paper. The circuit consists of one front-end rectifier, power management sub-block including bandgap reference and low drop-out regulators (LDOs) as well as transmission power detection / feedback circuits. Simulation result shows that the front-end rectifier achieves 80% power efficiency with 750-mV single-end peak-to-peak input voltage and 1.28-V output voltage under load current of 4 mA. The power management block can supply 1.8mA average load current under 1V consuming only 12μW power, which is equivalent to 99.3% power efficiency. The wireless power transmission block described in this paper achieves a maximum power efficiency of 80%. The wireless power transmission circuit block is designed and implemented using UMC 65-nm CMOS/RF process. It occupies 1 mm × 1.2 mm silicon area.

Keywords: Implantable biomedical devices, wireless power transfer, LDO, rectifier, closed-loop power control

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Authors: R. Bansal, A. Jain, M. Kumar, R. S. Meena

Abstract:

Present wireless communication demands compact and intelligent devices with multitasking capabilities at affordable cost. The focus in the presented paper is on a dual band antenna for wireless communication with the capability of operating at two frequency bands with same structure. Two resonance frequencies are observed with the second operation band at 4.2GHz approximately three times the first resonance frequency at 1.5GHz. Structure is simple loop of microstrip line with characteristic impedance 50 ohms. The proposed antenna is designed using defective ground structure (DGS) and shows the nearly one third reductions in size as compared to without DGS. This antenna was simulated on electromagnetic (EM) simulation software and fabricated using microwave integrated circuit technique on RT-Duroid dielectric substrate (ε_r= 2.22) of thickness (H=15 mils). The designed antenna was tested on automatic network analyzer and shows the good agreement with simulated results. The proposed structure is modeled into an equivalent electrical circuit and simulated on circuit simulator. Subsequently, theoretical analysis was carried out and simulated. The simulated, measured, equivalent circuit response, and theoretical results shows good resemblance. The bands of operation draw many potential applications in today’s wireless communication.

Keywords: Defective Ground plane, Dual band, Loop Antenna, Microstrip antenna, Resonance frequency.

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Authors: M.Nafar, A.H.Gheisari, A.Alesaadi

Abstract:

Since large power transformers are the most expensive and strategically important components of any power generator and transmission system, their reliability is crucially important for the energy system operation. Also, Circuit breakers are very important elements in the power transmission line so monitoring the events gives a knowledgebase to determine time to the next maintenance. This paper deals with the introduction of the comparative method of the state estimation of transformers and Circuit breakers using continuous monitoring of voltage, current. This paper gives details a new method based on wavelet to apparatus insulation monitoring. In this paper to insulation monitoring of transformer, a new method based on wavelet transformation and neutral point analysis is proposed. Using the EMTP tools, fault in transformer winding and the detailed transformer winding model were simulated. The current of neutral point of winding was analyzed by wavelet transformation. It is shown that the neutral current of the transformer winding has useful information about fault in insulation of the transformer.

Keywords: Wavelet, Power Transformer, EMTP, CircuitBreaker, Monitoring

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Authors: Montree Kumngern, Kobchai Dejhan

Abstract:

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array.

Keywords: Class-AB, dual-mode CMOS analog multiplier, CMOS analog integrated circuit, CMOS translinear integrated circuit.

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Authors: Brandon Foggo, Nanpeng Yu

Abstract:

Power distribution circuits undergo frequent network topology changes that are often left undocumented. As a result, the documentation of a circuit’s connectivity becomes inaccurate with time. The lack of reliable circuit connectivity information is one of the biggest obstacles to model, monitor, and control modern distribution systems. To enhance the reliability and efficiency of electric power distribution systems, the circuit’s connectivity information must be updated periodically. This paper focuses on one critical component of a distribution circuit’s topology - the secondary transformer to phase association. This topology component describes the set of phase lines that feed power to a given secondary transformer (and therefore a given group of power consumers). Finding the documentation of this component is call Phase Identification, and is typically performed with physical measurements. These measurements can take time lengths on the order of several months, but with supervised learning, the time length can be reduced significantly. This paper compares several such methods applied to Phase Identification for a large range of real distribution circuits, describes a method of training data selection, describes preprocessing steps unique to the Phase Identification problem, and ultimately describes a method which obtains high accuracy (> 96% in most cases, > 92% in the worst case) using only 5% of the measurements typically used for Phase Identification.

Keywords: Distribution network, machine learning, network topology, phase identification, smart grid.

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Authors: Somaye Abdollahi Pour, Mohsen Saneei

Abstract:

This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

Keywords: active mode, delay monitor, body biasing, VDD scaling, low power.

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