Search results for: pipeline processor

Authors: I. Abuiziah, A. Oulhaj, K. Sebari, D. Ouazar, A. A. Saber

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Fluid transient analysis is one of the more challenging and complicated flow problems in the design and the operation of water pipeline systems (wps). When transient conditions "water hammer" exists, the life expectancy of the wps can be adversely impacted, resulting in pump and valve failures and catastrophic pipe ruptures. Transient control has become an essential requirement for ensuring safe operation of wps. An accurate analysis and suitable protection devices should be used to protect wps. This paper presents the problem of modeling and simulation of transient phenomena in wps based on the characteristics method. Also, it provides the influence of using the protection devices to control the adverse effects due to excessive and low pressure occur in the transient. The developed model applied for main wps: pump combined with closed surge tank connected to a reservoir. The results obtained provide that the model is an efficient tool for water hammer analysis. Moreover; using the closed surge tank reduces the unfavorable effects of transients.

Keywords: Flow Transient, Water hammer, Pipeline System, Closed Surge Tank, Simulation Model, Protection Devices, Characteristics Method.

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Authors: Zahra Ramezanpanah, Joachim Carvallo, Aurelien Rodriguez

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This paper aims to detect anomalies in streaming data using machine learning algorithms. In this regard, we designed two separate pipelines and evaluated the effectiveness of each separately. The first pipeline, based on supervised machine learning methods, consists of two phases. In the first phase, we trained several supervised models using the UNSW-NB15 data set. We measured the efficiency of each using different performance metrics and selected the best model for the second phase. At the beginning of the second phase, we first, using Argus Server, sniffed a local area network. Several types of attacks were simulated and then sent the sniffed data to a running algorithm at short intervals. This algorithm can display the results of each packet of received data in real-time using the trained model. The second pipeline presented in this paper is based on unsupervised algorithms, in which a Temporal Graph Network (TGN) is used to monitor a local network. The TGN is trained to predict the probability of future states of the network based on its past behavior. Our contribution in this section is introducing an indicator to identify anomalies from these predicted probabilities.

Keywords: Cyber-security, Intrusion Detection Systems, Temporal Graph Network, Anomaly Detection.

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Authors: Mohammad Ahmad, Sander Gersen, Erwin Wilbers

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Carbon capture, transport and underground storage have become a major solution to reduce CO₂ emissions from power plants and other large CO₂ sources. A big part of this captured CO₂ stream is transported at high pressure dense phase conditions and stored in offshore underground depleted oil and gas fields. CO₂ is also transported in offshore pipelines to be used for enhanced oil and gas recovery. The captured CO₂ stream with impurities may contain water that causes severe corrosion problems, flow assurance failure and might damage valves and instrumentations. Thus, free water formation should be strictly prevented. The purpose of this work is to study the solubility of water in pure CO₂ and in CO₂ mixtures under real pipeline pressure (90-150 bar) and temperature operation conditions (5-35°C). A set up was constructed to generate experimental data. The results show the solubility of water in CO₂ mixtures increasing with the increase of the temperature or/and with the increase in pressure. A drop in water solubility in CO₂ is observed in the presence of impurities. The data generated were then used to assess the capabilities of two mixture models: the GERG-2008 model and the EOS-CG model. By generating the solubility data, this study contributes to determine the maximum allowable water content in CO₂ pipelines.

Keywords: Carbon capture and storage, water solubility, equation of states.

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Authors: Aboamama Atahar Ahmed, Muhammad Shafie Abd Latiff, Kamalrulnizam Abu Bakar, Zainul AhmadRajion

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Distance visualization of large datasets often takes the direction of remote viewing and zooming techniques of stored static images. However, the continuous increase in the size of datasets and visualization operation causes insufficient performance with traditional desktop computers. Additionally, the visualization techniques such as Isosurface depend on the available resources of the running machine and the size of datasets. Moreover, the continuous demand for powerful computing powers and continuous increase in the size of datasets results an urgent need for a grid computing infrastructure. However, some issues arise in current grid such as resources availability at the client machines which are not sufficient enough to process large datasets. On top of that, different output devices and different network bandwidth between the visualization pipeline components often result output suitable for one machine and not suitable for another. In this paper we investigate how the grid services could be used to support remote visualization of large datasets and to break the constraint of physical co-location of the resources by applying the grid computing technologies. We show our grid enabled architecture to visualize large medical datasets (circa 5 million polygons) for remote interactive visualization on modest resources clients.

Keywords: Visualization, Grid computing, Medical datasets, visualization techniques, thin clients, Globus toolkit, VTK.

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Authors: Khalid Kaddoura, Tarek Zayed

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Infrastructure assets are essential in urban cities; their purpose is to facilitate the public needs. As a result, their conditions and states shall always be monitored to avoid any sudden malfunction. Sewer systems, one of the assets, are an essential part of the underground infrastructure as they transfer sewer medium to designated areas. However, their conditions are subject to deterioration due to ageing. Therefore, it is of great significance to assess the conditions of pipelines to avoid sudden collapses. Current practices of sewer pipeline assessment rely on industrial protocols that consider distinct defects and grades to conclude the limited average or peak score of the assessed assets. This research aims to enhance the evaluation by integrating the Quality Function Deployment (QFD) and the Decision-Making Trial and Evaluation Laboratory (DEMATEL) methods in assessing the condition of sewer pipelines. The methodology shall study the cause and effect relationship of the systems’ defects to deduce the relative influence weights of each defect. Subsequently, the overall grade is calculated by aggregating the WHAT’s and HOW’s of the House of Quality (HOQ) using the computed relative weights. Thus, this study shall enhance the evaluation of the assets to conclude informative rehabilitation and maintenance plans for decision makers.

Keywords: Condition assessment, DEMATEL, QFD, sewer pipelines.

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Authors: Mahdi Hamzeh, Sied Mehdi Fakhraie, Caro Lucas

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All practical real-time scheduling algorithms in multiprocessor systems present a trade-off between their computational complexity and performance. In real-time systems, tasks have to be performed correctly and timely. Finding minimal schedule in multiprocessor systems with real-time constraints is shown to be NP-hard. Although some optimal algorithms have been employed in uni-processor systems, they fail when they are applied in multiprocessor systems. The practical scheduling algorithms in real-time systems have not deterministic response time. Deterministic timing behavior is an important parameter for system robustness analysis. The intrinsic uncertainty in dynamic real-time systems increases the difficulties of scheduling problem. To alleviate these difficulties, we have proposed a fuzzy scheduling approach to arrange real-time periodic and non-periodic tasks in multiprocessor systems. Static and dynamic optimal scheduling algorithms fail with non-critical overload. In contrast, our approach balances task loads of the processors successfully while consider starvation prevention and fairness which cause higher priority tasks have higher running probability. A simulation is conducted to evaluate the performance of the proposed approach. Experimental results have shown that the proposed fuzzy scheduler creates feasible schedules for homogeneous and heterogeneous tasks. It also and considers tasks priorities which cause higher system utilization and lowers deadline miss time. According to the results, it performs very close to optimal schedule of uni-processor systems.

Keywords: Computational complexity, Deadline, Feasible scheduling, Fuzzy scheduling, Priority, Real-time multiprocessor systems, Robustness, System utilization.

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Authors: M. A. Fodha, H. Benfradj, A. Ghazel

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This paper is a survey of recent works that proposes a baseband processor architecture for software defined radio. A classification of different approaches is proposed. The performance of each architecture is also discussed in order to clarify the suitable approaches that meet software-defined radio constraints.

Keywords: Multi-core architectures, reconfigurable architecture, software defined radio.

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Authors: A. R. Aswatha, T. Basavaraju, N. Bhaskara Rao

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This paper presents a new technique for the optimum placement of processors to minimize the total effective communication load under multi-processor communication dominated environment. This is achieved by placing heavily loaded processors near each other and lightly loaded ones far away from one another in the physical grid locations. The results are mathematically proved for the Algorithms are described.

Keywords: Ascending Sort Index Vector, EffectiveCommunication Load, Effective Distance Matrix, OptimalPlacement, Sorting Order.

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Authors: Robson C. Santos, Julio C. P. Ribeiro, Iorran M. de Castro, Luan C. F. Rodrigues, Sandro R. L. Silva, Diego M. Quesada

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The work aims to develop a robot in the form of autonomous vehicle to detect, inspection and mapping of underground pipelines through the ATmega328 Arduino platform. Hardware prototyping is very similar to C / C ++ language that facilitates its use in robotics open source, resembles PLC used in large industrial processes. The robot will traverse the surface independently of direct human action, in order to automate the process of detecting buried pipes, guided by electromagnetic induction. The induction comes from coils that send the signal to the Arduino microcontroller contained in that will make the difference in intensity and the treatment of the information, and then this determines actions to electrical components such as relays and motors, allowing the prototype to move on the surface and getting the necessary information. This change of direction is performed by a stepper motor with a servo motor. The robot was developed by electrical and electronic assemblies that allowed test your application. The assembly is made up of metal detector coils, circuit boards and microprocessor, which interconnected circuits previously developed can determine, process control and mechanical actions for a robot (autonomous car) that will make the detection and mapping of buried pipelines plates. This type of prototype can prevent and identifies possible landslides and they can prevent the buried pipelines suffer an external pressure on the walls with the possibility of oil leakage and thus pollute the environment.

Keywords: Robotic, metal detector, embedded system, pipeline.

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Authors: Yahia Salah, Med Lassaad Kaddachi, Rached Tourki

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This paper presents the design, implementation and evaluation of a micro-network, or Network-on-Chip (NoC), based on a generic pipeline router architecture. The router is designed to efficiently support traffic generated by multimedia applications on embedded multi-core systems. It employs a simplest routing mechanism and implements the round-robin scheduling strategy to resolve output port contentions and minimize latency. A virtual channel flow control is applied to avoid the head-of-line blocking problem and enhance performance in the NoC. The hardware design of the router architecture has been implemented at the register transfer level; its functionality is evaluated in the case of the two dimensional Mesh/Torus topology, and performance results are derived from ModelSim simulator and Xilinx ISE 9.2i synthesis tool. An example of a multi-core image processing system utilizing the NoC structure has been implemented and validated to demonstrate the capability of the proposed micro-network architecture. To reduce complexity of the image compression and decompression architecture, the system use image processing algorithm based on classical discrete cosine transform with an efficient zonal processing approach. The experimental results have confirmed that both the proposed image compression scheme and NoC architecture can achieve a reasonable image quality with lower processing time.

Keywords: Generic Pipeline Network-on-Chip Router Architecture, JPEG Image Compression, FPGA Hardware Implementation, Performance Evaluation.

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Authors: Turgut Ayten, Tayfun Çay

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In the current expropriation of Turkey, the state acquires necessary lands for its investment without permission of the owners and not searching for alternative solutions, so it is determined that neither processor nor processed is not happy. In this study, interactions of enterprises in Turkey are analysed in case the necessary land for public investments are acquired by expropriation purposed land consolidation. Legal basis, positive and negative sides, financial effects to enterprises of this method is evaluated according to Konya Kadınhanı, Kolukısa avenue which is on the Konya-Ankara High-Speed Train Route.

Keywords: Land consolidation, expropriation purposed land consolidation, sustainable rural development, cost.

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Authors: Jong-Bae Lee, Seongsoo Lee

Abstract:

Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: Local interconnect network, controller, transceiver, processor.

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Authors: Yiannis G. Smirlis

Abstract:

The classification and the prediction of efficiencies in Data Envelopment Analysis (DEA) is an important issue, especially in large scale problems or when new units frequently enter the under-assessment set. In this paper, we contribute to the subject by proposing a grid structure based on interval segmentations of the range of values for the inputs and outputs. Such intervals combined, define hyper-rectangles that partition the space of the problem. This structure, exploited by Interval DEA models and a dominance relation, acts as a DEA pre-processor, enabling the classification and prediction of efficiency scores, without applying any DEA models.

Keywords: Data envelopment analysis, interval DEA, efficiency classification, efficiency prediction.

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Authors: Dalvinder Singh Dhaliwal, Parvinder S. Sandhu, S. N. Panda

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This paper is on the general discussion of memory consistency model like Strict Consistency, Sequential Consistency, Processor Consistency, Weak Consistency etc. Then the techniques for implementing distributed shared memory Systems and Synchronization Primitives in Software Distributed Shared Memory Systems are discussed. The analysis involves the performance measurement of the protocol concerned that is Multiple Writer Protocol. Each protocol has pros and cons. So, the problems that are associated with each protocol is discussed and other related things are explored.

Keywords: Distributed System, Single owner protocol, Multiple owner protocol

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Authors: Carmen Navarrete, Eloy Anguiano

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In the last years, the computers have increased their capacity of calculus and networks, for the interconnection of these machines. The networks have been improved until obtaining the actual high rates of data transferring. The programs that nowadays try to take advantage of these new technologies cannot be written using the traditional techniques of programming, since most of the algorithms were designed for being executed in an only processor,in a nonconcurrent form instead of being executed concurrently ina set of processors working and communicating through a network.This paper aims to present the ongoing development of a new system for the reconfiguration of grouping of computers, taking into account these new technologies.

Keywords: Dynamic network topology, resource and task allocation, parallel computing, heterogeneous computing, dynamic reconfiguration.

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Authors: M. K. Benhaoua, A. K. Singh, A. E. H. Benyamina, A. Kumar, P. Boulet

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In this paper, we propose a new packing strategy to find a free resource for run-time mapping of application tasks to NoC-based Heterogeneous MPSoC. The proposed strategy minimizes the task mapping time in addition to placing the communicating tasks close to each other. To evaluate our approach, a comparative study is carried out for a platform containing single task supported PEs. Experiments show that our strategy provides better results when compared to latest dynamic mapping strategies reported in the literature.

Keywords: Multi-Processor Systems-on-Chip (MPSoCs), Network-on-Chip (NoC), Heterogeneous architectures, Dynamic mapping heuristics.

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Authors: Junghwan Choi, Seongsoo Lee

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Histogram equalization is often used in image enhancement, but it can be also used in auto exposure. However, conventional histogram equalization does not work well when many pixels are concentrated in a narrow luminance range.This paper proposes an auto exposure method based on 2-way histogram equalization. Two cumulative distribution functions are used, where one is from dark to bright and the other is from bright to dark. In this paper, the proposed auto exposure method is also designed and implemented for image signal processors with full-HD images.

Keywords: Histogram equalization, Auto exposure, Image signal processor, Low-cost, Full HD Video.

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Authors: Ahmad M. Shafiee, Mehrdad Montazeri, Mahdi Nikdast

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Every day human life experiences new equipments more automatic and with more abilities. So the need for faster processors doesn-t seem to finish. Despite new architectures and higher frequencies, a single processor is not adequate for many applications. Parallel processing and networks are previous solutions for this problem. The new solution to put a network of resources on a chip is called NOC (network on a chip). The more usual topology for NOC is mesh topology. There are several routing algorithms suitable for this topology such as XY, fully adaptive, etc. In this paper we have suggested a new algorithm named Intermittent X, Y (IX/Y). We have developed the new algorithm in simulation environment to compare delay and power consumption with elders' algorithms.

Keywords: Computer architecture, parallel computing, NOC, routing algorithm.

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Authors: Trung Hieu Tran, Hyo-Moon Cho, Sang-Bock Cho

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Motion estimation is the most computationally intensive part in video processing. Many fast motion estimation algorithms have been proposed to decrease the computational complexity by reducing the number of candidate motion vectors. However, these studies are for fast search algorithms themselves while almost image and video compressions are operated with software based. Therefore, the timing constraints for running these motion estimation algorithms not only challenge for the video codec but also overwhelm for some of processors. In this paper, the performance of motion estimation is enhanced by using Intel's Streaming SIMD Extension 2 (SSE2) technology with Intel Pentium 4 processor.

Keywords: Motion Estimation, Full Search, Three StepSearch, MMX/SSE/SSE2 Technologies, SIMD.

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Authors: Bachir Boucheham, Youcef Ferdi, Mohamed Chaouki Batouche

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We suggest a novel method to incorporate longterm redundancy (LTR) in signal time domain compression methods. The proposition is based on block-sorting and curve simplification. The proposition is illustrated on the ECG signal as a post-processor for the FAN method. Test applications on the new so-obtained FAN+ method using the MIT-BIH database show substantial improvement of the compression ratio-distortion behavior for a higher quality reconstructed signal.

Keywords: ECG compression, Long-term redundancy, Block-sorting, Curve Simplification.

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Authors: Gao Wei, Xu Minglu, Xu Yan, Zhang Xiaotong, Wang Xinghua

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A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.

Keywords: pipelined ADC, MDAC, operational amplifier.

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Authors: Mir Hadi Seyedafsari, Iraj Hasanzadeh

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Like other external sorting algorithms, the presented algorithm is a two step algorithm including internal and external steps. The first part of the algorithm is like the other similar algorithms but second part of that is including a new easy implementing method which has reduced the vast number of inputoutput operations saliently. As decreasing processor operating time does not have any effect on main algorithm speed, any improvement in it should be done through decreasing the number of input-output operations. This paper propose an easy algorithm for choose the correct record location of the final list. This decreases the time complexity and makes the algorithm faster.

Keywords: External sorting algorithm, internal sortingalgorithm, fast sorting, robust algorithm.

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Authors: Vojtěch Gybas, Libor Klubal, Kateřina Kostolányová

Abstract:

This case study responds to the current trends in ICT. Mobile Touch iPads can provide very good assistance to disabled seniors. The intuitive tablet environment, the possibility of the formation environment and its portability, has a very positive effect on the use of particular communication. For comparison, using a conventional PC/notebook, word processor, keyboard and computer mouse compared to the iPad and selected applications. The results of this case study show that the use of mobile touch devices iPad for seniors with mental retardation is a great benefit. These devices do not require high demands on graphomotorics like a standard PC devices.

Keywords: ICT, iPad, handicapped seniors, communication, computer, notebook, applications, text editor.

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Authors: Ewa Wywial, Shaneen M. Singh

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The PRAF family of proteins is a plant specific family of proteins with distinct domain architecture and various unique sequence/structure traits. We have carried out an extensive search of the Arabidopsis genome using an automated pipeline and manual methods to verify previously known and identify unknown instances of PRAF proteins, characterize their sequence and build 3D structures of their individual domains. Integrating the sequence, structure and whatever little known experimental details for each of these proteins and their domains, we present a comprehensive characterization of the different domains in these proteins and their variant properties.

Keywords: PRAF proteins, homology modeling, Arabidopsisthaliana

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Authors: Farshad Arvin, Shyamala Doraisamy

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This paper presents a new hardware interface using a microcontroller which processes audio music signals to standard MIDI data. A technique for processing music signals by extracting note parameters from music signals is described. An algorithm to convert the voice samples for real-time processing without complex calculations is proposed. A high frequency microcontroller as the main processor is deployed to execute the outlined algorithm. The MIDI data generated is transmitted using the EIA-232 protocol. The analyses of data generated show the feasibility of using microcontrollers for real-time MIDI generation hardware interface.

Keywords: Signal processing, MIDI, Microcontroller, EIA-232.

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Authors: Nathar Shah, Visham Cheerkoot

Abstract:

CScheme, a concurrent programming paradigm based on scheme concept enables concurrency schemes to be constructed from smaller synchronization units through a GUI based composer and latter be reused on other concurrency problems of a similar nature. This paradigm is particularly important in the multi-core environment prevalent nowadays. In this paper, we demonstrate techniques to separate concurrency from functional code using the CScheme paradigm. Then we illustrate how the CScheme methodology can be used to solve some of the traditional concurrency problems – critical section problem, and readers-writers problem - using synchronization schemes such as Single Threaded Execution Scheme, and Readers Writers Scheme.

Keywords: Concurrent Programming, Object Oriented Programming, Environments for multiple-processor systems, Programming paradigms.

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Authors: N.H. Mvungi

Abstract:

This paper addresses control of commutation of switched reluctance (SR) motor without the use of a physical position detector. Rotor position detection schemes for SR motor based on magnetisation characteristics of the motor use normal excitation or applied current /voltage pulses. The resulting schemes are referred to as passive or active methods respectively. The research effort is in realizing an economical sensorless SR rotor position detector that is accurate, reliable and robust to suit a particular application. An effective and reliable means of generating commutation signals of an SR motor based on inductance profile of its stator windings determined using active probing technique is presented. The scheme has been validated online using a 4-phase 8/6 SR motor and an 8-bit processor.

Keywords: Position detection, rotor position, sensorless, switched reluctance, SR.

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Authors: Imron Rosyadi, Ridha A. Djemal, Saleh A. Alshebeili

Abstract:

Design and implementation of a novel B-ACOSD CFAR algorithm is presented in this paper. It is proposed for detecting radar target in log-normal distribution environment. The BACOSD detector is capable to detect automatically the number interference target in the reference cells and detect the real target by an adaptive threshold. The detector is implemented as a System on Chip on FPGA Altera Stratix II using parallelism and pipelining technique. For a reference window of length 16 cells, the experimental results showed that the processor works properly with a processing speed up to 115.13MHz and processing time0.29 ┬Ás, thus meets real-time requirement for a typical radar system.

Keywords: CFAR, FPGA, radar.

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Authors: Ersan Aktas, Eren Turanoğuz

Abstract:

In this study, the quad-electrical rotor driven unmanned aerial vehicle system is designed and modeled using fundamental dynamic equations. After that, mechanical, electronical and control system of the air vehicle are designed and implemented. Brushless motor speeds are altered via electronic speed controllers in order to achieve desired controllability. The vehicle's fundamental Euler angles (i.e., roll angle, pitch angle, and yaw angle) are obtained via AHRS sensor. These angles are provided as an input to the control algorithm that run on soft the processor on the electronic card. The vehicle control algorithm is implemented in the electronic card. Controller is designed and improved for each Euler angles. Finally, flight tests have been performed to observe and improve the flight characteristics.

Keywords: Quadrotor, UAS applications, control architectures, PID.

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Authors: M. Razak, A. Jusoh, A. Zakaria

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This paper presents an on-going research work on the implementation of feature-based machining via macro programming. Repetitive machining features such as holes, slots, pockets etc can readily be encapsulated in macros. Each macro consists of methods on how to machine the shape as defined by the feature. The macro programming technique comprises of a main program and subprograms. The main program allows user to select several subprograms that contain features and define their important parameters. With macros, complex machining routines can be implemented easily and no post processor is required. A case study on machining of a part that comprised of planar face, hole and pocket features using the macro programming technique was carried out. It is envisaged that the macro programming technique can be extended to other feature-based machining fields such as the newly developed STEP-NC domain.

Keywords: Feature-based machining, CNC, Macro, STEP-NC.

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