Search results for: m/chip advance standard

Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, Md Hanif Md Nasir

Abstract:

This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Keywords: methodology, flip chip, bump cell, LEF, astro, calibre, SCHEME, TCL

Procedia PDF Downloads 464

Authors: Long Kim Vu

Abstract:

The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method.

Keywords: CFD, FPGA, heat transfer, thermal analysis

Procedia PDF Downloads 171

Authors: Muthana Saleh Alalaki, Michael Opoku Agyeman

Abstract:

The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements. As a result, Network-on-Chip (NoC) has emerged as a system architecture to overcome intra-communication issues. This paper presents a study of recent contributions on simulation tools for NoC. Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication.

Keywords: WiNoC, simulation tool, network-on-chip, SoC

Procedia PDF Downloads 475

Authors: Nesrine Toubaline, Djamel Bennouar, Ali Mahdoum

Abstract:

3D technology can lead to a significant reduction in power and average hop-count in Networks on Chip (NoCs). It offers short and fast vertical links which copes with the long wire problem in 2D NoCs. This work proposes heuristic-based method to optimize number and placement of vertical links to achieve specified performance goals. Experiments show that significant improvement can be achieved by using a specific number of vertical interconnect.

Keywords: interconnect optimization, monolithic inter-tier vias, network on chip, system on chip, through silicon vias, three dimensional integration circuits

Procedia PDF Downloads 278

Authors: Reza Hadjiaghaie Vafaie, Aysan Madanpasandi, Behrooz Zare Desari, Seyedmohammad Mousavi

Abstract:

High lamination in microchannel is one of the main challenges in on-chip components like micro total analyzer systems and lab-on-a-chips. Electro-osmotic force is highly effective in chip-scale. This research proposes a microfluidic-based micropump for low ionic strength solutions. Narrow microchannels are designed to generate an efficient electroosmotic flow near the walls. Microelectrodes are embedded in the lateral sides and actuated by low electric potential to generate pumping effect inside the channel. Based on the simulation study, the fluid velocity increases by increasing the electric potential amplitude. We achieve a net flow velocity of 100 µm/s, by applying +/- 2 V to the electrode structures. Our proposed low voltage design is of interest in conventional lab-on-a-chip applications.

Keywords: integration, electrokinetic, on-chip, fluid pumping, microfluidic

Procedia PDF Downloads 276

Authors: Martin Pumera

Abstract:

Graphene materials are being widely used in electrochemistry due to their versatility and excellent properties as platforms for biosensing. Here we present current trends in the electrochemical biosensing of pesticides and other toxic compounds. We explore two fundamentally different designs, (i) using graphene and other 2-D nanomaterials as an electrochemical platform and (ii) using these nanomaterials in the laboratory on chip design, together with paramagnetic beads. More specifically: (i) We explore graphene as transducer platform with very good conductivity, large surface area, and fast heterogeneous electron transfer for the biosensing. We will present the comparison of these materials and of the immobilization techniques. (ii) We present use of the graphene in the laboratory on chip systems. Laboratory on the chip had a huge advantage due to small footprint, fast analysis times and sample handling. We will show the application of these systems for pesticide detection and detection of other toxic compounds.

Keywords: graphene, 2D nanomaterials, biosensing, chip design

Procedia PDF Downloads 533

Authors: Arunas Stirke, Neringa Bakute, Gatis Mozolevskis

Abstract:

A technology of microfluidics is an emerging tool in the field of biology, medicine and chemistry. Microfluidic device is also known as ‘lab-on-a-chip’ technology [1]. In moving from macro- to microscale, there is unprecedented control over spatial and temporal gradients and patterns that cannot be captured in conventional Petri dishes and well plates [2]. However, there is not a single standard microfluidic chip designated for all purposes – every different field of studies needs a specific microchip with certain geometries, inlet/outlet, channel depth and other parameters to precisely regulate the required function. Since our group is studying an effect of pulsed electric field (PEF) to the cells, we have manufactured a microfluidic chip designated for high-throughput electroporation of cells. In our microchip, a cell culture chamber is divided into two parallel channels by a membrane, meanwhile electrodes for electroporation are attached to the wall of the channels. Both microchannels have their own inlet and outlet, enabling injection of transfection material separately. Our perspective is to perform electroporation of mammalian cells in two different ways: (1) plasmid and cells are injected in the same microchannel and (2) injected into separate microchannels. Moreover, oxygen and pH sensors are integrated on order to analyse cell viability parameters after PEF treatment.

Keywords: microfluidics, chip, fabrication, electroporation

Procedia PDF Downloads 63

Authors: Mohsen Marani Barzani, Ahmed A. D. Sarhan, Saeed Farahany, Ramesh Singh

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Surface roughness and chip morphology are important output in manufacturing product. In this paper, an experimental investigation was conducted to determine the effects of various cutting speeds and feed rates on surface roughness and chip morphology in turning the Al-Si cast alloy and Sr-containing. Experimental trials carried out using coated carbide inserts. Experiments accomplished under oblique dry cutting when various cutting speeds 70, 130 and 250 m/min and feed rates of 0.05, 0.1 and 0.15 mm/rev were used, whereas depth of cut kept constant at 0.05 mm. The results showed that Sr-containing Al-Si alloy have poor surface roughness in comparison to Al-Si alloy (base alloy). The surface roughness values reduce with cutting speed increment from 70 to 250 m/min. the size of chip changed with changing silicon shape in Al matrix. Also, the surface finish deteriorated with increase in feed rate from 0.5 mm/rev to 0.15 mm/rev.

Keywords: strontium, surface roughness, chip, morphology, turning

Procedia PDF Downloads 364

Authors: M. Benghersallah, L. Boulanouar, G. List, G. Sutter

Abstract:

The present work is an experimental study on the dry high speed turning of Ti-6Al-4V titanium alloy. The objective of this study is to see for high cutting speeds, how wear occurs on the face of insert and how to evolve cutting forces and chip formation. Cutting speeds tested is 600, 800, 1000 and 1200 m / min in orthogonal turning with a carbide insert tool H13A uncoated on a cylindrical titanium alloy part. Investigation on the wear inserts with 3D scanning microscope revered the crater formation is instantaneous and a chip adhesion (welded chip) causes detachment of carbide particles. In these experiments, the chip shape was systematically investigated at each cutting conditions using optical microscopy. The chips produced were collected and polished to measure the thicknesses t2max and t2min, dch the distance between each segments and ɸseg the inclination angle As described in the introduction part, the shear angle f and the inclination angle of a segment ɸseg are differentiated. The angle ɸseg is actually measured on the collected chips while the shear angle f cannot be. The angle ɸ represents the initial shear similar to the one that describes the formation of a continuous chip in the primary shear zone. Cutting forces increase and stabilize before removing the tool. The chip reaches a very high temperature.

Keywords: dry high speed, orthogonal turning, chip formation, cutting speed, cutting forces

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Authors: Chien-Ju Chen, Chia-Jui Yu, Jyun-Hao Liao, Chia-Ching Wu, Meng-Chyi Wu

Abstract:

A 64 × 64 GaN-based micro-light-emitting diode array (μLEDA) with 20 μm in pixel size and 40 μm in pitch by flip-chip bonding (FCB) is demonstrated in this study. Besides, an underfilling (UF) technology is applied to the process for improving the uniformity of device. With those configurations, good characteristics are presented, operation voltage and series resistance of a pixel in the 450 nm flip chip μLEDA are 2.89 V and 1077Ω (4.3 mΩ-cm²) at 25 A/cm², respectively. The μLEDA can sustain higher current density compared to conventional LED, and the power of the device is 9.5 μW at 100 μA and 0.42 mW at 20 mA.

Keywords: GaN, micro-light-emitting diode array(μLEDA), flip-chip bonding, underfilling

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Authors: Longfei Wang, Selçuk Köse

Abstract:

Hardware Trojan becomes great concern as integrated circuit (IC) technology advances and not all manufacturing steps of an IC are accomplished within one company. Real-time hardware Trojan detection is proven to be a feasible way to detect randomly activated Trojans that cannot be detected at testing stage. On-chip sensors serve as a great candidate to implement real-time hardware Trojan detection, however, the optimization of on-chip sensors has not been thoroughly investigated and the location of Trojan has not been carefully explored. On-chip sensor ellipse distribution method and equivalent mapping technique are proposed based on the characteristics of on-chip power delivery network in this paper to address the optimization and distribution of on-chip sensors for real-time hardware Trojan detection as well as to estimate the location and current consumption of hardware Trojan. Simulation results verify that hardware Trojan activation can be effectively detected and the location of a hardware Trojan can be efficiently estimated with less than 5% error for a realistic power grid using our proposed methods. The proposed techniques therefore lay a solid foundation for isolation and even deactivation of hardware Trojans through accurate location of Trojans.

Keywords: hardware trojan, on-chip sensor, power distribution network, power/ground noise

Procedia PDF Downloads 376

Authors: M. Benghersallah, G. List, G. Sutter

Abstract:

The present work is an experimental study on the dry high speed turning of Ti-6Al-4V titanium alloy. The objective of this study is to see for high cutting speeds, how wear occurs on the face of insert and how to evolve cutting forces and chip formation. Cutting speeds tested is 600, 800, 1000, and 1200 m/min in orthogonal turning with a carbide insert tool H13A uncoated on a cylindrical titanium alloy part. Investigation on the wear inserts with 3D scanning microscope revered the crater formation is instantaneous and a chip adhesion (welded chip) causes detachment of carbide particles. Cutting forces increase and stabilize before removing the tool. The chip reaches a very high temperature.

Keywords: titanium alloy, dry hjgh speed turning, wear insert, MQL technique

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Authors: Moaz H. Ali, Ahmed H. Al-Saadi

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Most of the materials used in the industry of aero-engine components generally consist of titanium alloys. Advanced materials, because of their excellent combination of high specific strength, lightweight, and general corrosion resistance. In fact, chemical wear resistance of aero-engine alloy provide a serious challenge for cutting tool material during the machining process. The reduction in cutting temperature distributions leads to an increase in tool life and a decrease in wear rate. Hence, the chip morphology and segmentation play a predominant role in determining machinability and tool wear during the machining process. The result of low thermal conductivity and diffusivity of this alloy in the concentration of high temperatures at the tool-work-piece and tool-chip interface. Consequently, the chip morphology is very important in the study of machinability of metals as well as the study of cutting tool wear. Otherwise, the result will be accelerating tool wear, increasing manufacturing cost and time consuming.

Keywords: machinability, titanium alloy (ti-6al-4v), chip formation, milling process

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Authors: Qaisara Parveen, M. Imran Yousuf

Abstract:

The purpose of this study was to find the effectiveness of the use of advance organizer model for enhancing meta-cognition of students in the subject of science. It was hypothesized that the students of experimental group taught through advance organizer model would show the better cognition than the students of control group taught through traditional teaching. The population of the study consisted of all secondary school students studying in government high school located in Rawalpindi. The sample of the study consisted of 50 students of 9th class of humanities group. The sample was selected on the basis of their pretest scores through matching, and the groups were randomly assigned for the treatment. The experimental group was taught through advance organizer model while the control group was taught through traditional teaching. The self-developed achievement test was used for the purpose of pretest and posttest. After collecting the pre-test score and post-test score, the data was analyzed and interpreted by use of descriptive statistics as mean and standard deviation and inferential statistics t-test. The findings indicate that students taught using advance organizers had a higher level of meta-cognition as compared to control group. Further, meta cognition level of boys was found higher than that of girls students. This study also revealed the fact that though the students at different meta-cognition level approached learning situations in a different manner, Advance organizer model is far superior to Traditional method of teaching.

Keywords: descriptive, experimental, humanities, meta-cognition, statistics, science

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Authors: D. O. Ramadan, R. S. Dwyer-Joyce

Abstract:

The measurement of the interface conditions in a cutting tool contact is essential information for performance monitoring and control. This interface provides the path for the heat flux to the cutting tool. This elevate in the cutting tool temperature leads to motivate the mechanism of tool wear, thus affect the life of the cutting tool and the productivity. This zone is representative by the tool-chip interface. Therefore, understanding and monitoring this interface is considered an important issue in machining. In this paper, an acoustic emission (AE) technique was used to find the correlation between AE parameters and the tool-chip interface. For this reason, a response surface design (RSD) has been used to analyse and optimize the machining parameters. The experiment design was based on the face centered, central composite design (CCD) in the Minitab environment. According to this design, a series of orthogonal cutting experiments for different cutting conditions were conducted on a Triumph 2500 lathe machine to study the sensitivity of the acoustic emission (AE) signal to change in tool-chip contact length. The cutting parameters investigated were the cutting speed, depth of cut, and feed and the experiments were performed for 6082-T6 aluminium tube. All the orthogonal cutting experiments were conducted unlubricated. The tool-chip contact area was investigated using a scanning electron microscope (SEM). The results obtained in this paper indicate that there is a strong dependence of the root mean square (RMS) on the cutting speed, where the RMS increases with increasing the cutting speed. A dependence on the tool-chip contact length has been also observed. However there was no effect observed of changing the cutting depth and feed on the RMS. These dependencies have been clarified in terms of the strain and temperature in the primary and secondary shear zones, also the tool-chip sticking and sliding phenomenon and the effect of these mechanical variables on dislocation activity at high strain rates. In conclusion, the acoustic emission technique has the potential to monitor in situ the tool-chip interface in turning and consequently could indicate the approaching end of life of a cutting tool.

Keywords: Acoustic emission, tool-chip interface, orthogonal cutting, monitoring

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Authors: Junior Nomani

Abstract:

This paper presents a novel approach to modelling the metal cutting of duplex stainless steels, a two-phase alloy regarded as a difficult-to-machine material. Calculation and control of shear strain and stresses during cutting are essential to achievement of ideal cutting conditions. Too low or too high leads to higher required cutting force or excessive heat generation causing premature tool wear failure. A 2D finite element cutting model was created based on electron backscatter diffraction (EBSD) data imagery of duplex microstructure. A mesh was generated using ‘object-oriented’ software OOF2 version V2.1.11, converting microstructural images to quadrilateral elements. A virtual workpiece was created on ABAQUS modelling software where a rigid body toolpiece advanced towards workpiece simulating chip formation, generating serrated edge chip formation cutting. Model results found calculated stress strain contour plots correlated well with similar finite element models tied with austenite stainless steel alloys. Virtual chip form profile is also similar compared experimental frozen machining chip samples. The output model data provides new insight description of strain behavior of two phase material on how it transitions from workpiece into the chip.

Keywords: Duplex stainless steel, ABAQUS, OOF2, Chip formation

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Authors: Zhao Bin, Yan Dan Lei

Abstract:

In this paper, a multi-pattern parallel PRBS generator and a dedicated parallel BER tester is proposed for the 8-Gbps On-chip interconnection testing. A unique full-parallel PRBS checker is also proposed. The proposed design, together with the custom-designed high-speed parallel-to-serial and the serial-to-parallel circuit, will be used to test different on-chip interconnection transceivers. The design is implemented in TSMC 28nm CMOS technology with working voltage at 1.0 V. The serial to parallel ratio is 8:1 so the parallel PRBS generation and BER Tester can be run at lower speed.

Keywords: PRBS, BER, high speed, generator

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Authors: Rafiqul Tarefder, Mohiuddin Ahmad, Mohammad Hossain

Abstract:

While milling materials from old pavement surface can be an important component of cost effective maintenance operation, their use in maintenance projects are not uniform and well documented. This study documents the different maintenance practices followed by four transportation districts of New Mexico Department of Transportation (NMDOT) in an attempt to find whether millings are being used in maintenance projects by those districts. Based on existing literature, a questionnaire was developed related to six common maintenance practices. NMDOT district personal were interviewed face to face to discuss and get answers to that questionnaire. It revealed that NMDOT districts mainly use chip seal and patching. Other maintenance procedures such as sand seal, scrub seal, slurry seal, and thin overlay have limited use. Two out of four participating districts do not have any documents on chip sealing; rather they employ the experiences of the chip seal crew. All districts use polymer modified high float emulsion (HFE100P) for chip seal with an application rate ranging from 0.4 to 0.56 gallons per square yard. Chip application rate varies from 15 to 40 lb/ square yard. State wide, the thickness of chip seal varies from 3/8" to 1" and life varies from 3 to 10 years. NMDOT districts mainly use three type of patching: pothole, dig-out and blade patch. Pothole patches are used for small potholes and during emergency, dig-out patches are used for all type of potholes sometimes after pothole patching, and blade patch is used when a significant portion of the pavement is damaged. Pothole patches last as low as three days whereas, blade patch lasts as long as 3 years. It was observed that all participating districts use millings in maintenance projects.

Keywords: chip seal, sand seal, scrub seal, slurry seal, overlay, patching, millings

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Authors: Anil Kawan, Soon Jae Yu, Jong Min Park

Abstract:

GaN-based 365 nm wavelength ultraviolet (UV) light emitting diodes (LED) have various applications: curing, molding, purification, deodorization, and disinfection etc. However, their usage is limited by very low output power, because of the light absorption in the GaN layers. In this study, we demonstrate a method utilizing removal of 365 nm absorption layer buffer GaN and thinning the n-type GaN so as to improve the light extraction efficiency of the GaN-based 365 nm UV LED. The UV flip chip LEDs of chip size 1.3 mm x 1.3 mm were fabricated using GaN epilayers on a sapphire substrate. Via-hole n-type contacts and highly reflective Ag metal were used for efficient light extraction. LED wafer was aligned and bonded to AlN carrier wafer. To improve the extraction efficiency of the flip chip LED, sapphire substrate and absorption layer buffer GaN were removed by using laser lift-off and dry etching, respectively. To further increase the extraction efficiency of the LED, exposed n-type GaN thickness was reduced by using inductively coupled plasma etching.

Keywords: extraction efficiency, light emitting diodes, n-GaN thinning, ultraviolet

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Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm² and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: reconfigurable, fast Fourier transform (FFT), single-path delay feedback (SDF), 3GPP-LTE

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Authors: Farnaz Fotovvatikhah, Javad Akbari

Abstract:

Test time of a test architecture is an important factor which depends on the architecture's delay and test patterns. Here a new architecture to store the test results based on network on chip is presented. In addition, simple analytical model is proposed to calculate link test time for built in self-tester (BIST) and external tester (Ext) in multiprocessor systems. The results extracted from the model are verified using FPGA implementation and experimental measurements. Systems consisting 16, 25, and 36 processors are implemented and simulated and test time is calculated. In addition, BIST and Ext are compared in terms of test time at different conditions such as at different number of test patterns and nodes. Using the model the maximum frequency of testing could be calculated and the test structure could be optimized for high speed testing.

Keywords: test, nano on-chip network, JTAG, modelling

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Authors: Maryam Ghoreishi, Christian Larsen

Abstract:

In this paper, we investigate the effect of stochastic inputs on problem of joint optimal pricing and lot-sizing decisions where the inventory cycle is divided into advance and spot sales periods. During the advance sales period, customer can make reservations while customer with reservations can cancel their order. However, during the spot sales period customers receive the order as soon as the order is placed, but they cannot make any reservation or cancellation during that period. We assume that the inter arrival times during the advance sales and spot sales period are exponentially distributed where the arrival rate is decreasing function of price. Moreover, we assume that the number of cancelled reservations is binomially distributed. In addition, we assume that deterioration process follows an exponential distribution. We investigate two cases. First, we consider two-state case where we find the optimal price during the spot sales period and the optimal price during the advance sales period. Next, we develop a generalized case where we extend two-state case also to allow dynamic prices during the spot sales period. We apply the Markov decision theory in order to find the optimal solutions. In addition, for the generalized case, we apply the policy iteration algorithm in order to find the optimal prices, the optimal lot-size and maximum advance sales amount.

Keywords: inventory control, pricing, Markov decision theory, advance sales system

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Authors: Kadir Gök

Abstract:

In this study, a vacuum system was developed for orthopedic drilling processes, and the most efficient processing parameters were determined using statistical analysis of temperature rise. A reverse engineering technique was used to obtain a 3D model of the chip vacuum system, and the obtained point cloud data was transferred to Solidworks software in STL format. An experimental design method was performed by selecting different parameters and their levels, such as RPM, feed rate, and drill bit diameter, to determine the most efficient processing parameters in temperature rise using ANOVA. Additionally, the bone chip-vacuum device was developed and performed successfully to collect the whole chips and fragments in the bone drilling experimental tests, and the chip-collecting device was found to be useful in removing overheating from the drilling zone. The effects of processing parameters on the temperature levels during the chip-vacuuming were determined, and it was found that bone chips and fractures can be used as autograft and allograft for tissue engineering. Overall, this study provides significant insights into the development of a vacuum system for orthopedic drilling processes and the use of bone chips and fractures in tissue engineering applications.

Keywords: vacuum system, orthopedic drilling, temperature rise, bone chips

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Authors: M. K. Benhaoua, A. E. H. Benyamina, T. Djeradi, P. Boulet

Abstract:

In this paper, we propose adaptive routing that considers the routing of communications in order to optimize the overall performance. The routing technique uses a newly proposed Algorithm to route communications between the tasks. The routing we propose of the communications leads to a better optimization of several performance metrics (time and energy consumption). Experimental results show that the proposed routing approach provides significant performance improvements when compared to those using static routing.

Keywords: multi-processor systems-on-chip (mpsocs), network-on-chip (noc), heterogeneous architectures, adaptive routin

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Authors: Pisut Painmanakul, Thawatchai Chintateerachai, Supanid Lertlapwasin, Nusara Rojvilavan, Tanun Chalermsinsuwan, Nattawin Chawaloesphonsiya, Onanong Larpparisudthi

Abstract:

Conventional coagulation, advance oxidation process (AOPs), and the combined process were evaluated and compared for its suitability to treat the stabilized cutting-oil wastewater. The 90% efficiency was obtained from the coagulation at Al2(SO4)3 dosage of 150 mg/L and pH 7. On the other hands, efficiencies of AOPs for 30 minutes oxidation time were 10% for acoustic oxidation, 12% for acoustic oxidation with hydrogen peroxide, 76% for Fenton, and 92% sono-Fenton processes. The highest efficiency for effective oil removal of AOPs required large amount of chemical. Therefore, AOPs were studied as a post-treatment after conventional separation process. The efficiency was considerable as the effluent COD can pass the standard required for industrial wastewater discharge with less chemical and energy consumption.

Keywords: cutting oily-wastewater, advance oxidation process, sono-fenton, combined process

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Authors: Vinayaga Jagadessh Raja, R. Ganesan, S. Ramesh Kumar

Abstract:

An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC) based system on- chip (SoC) is due to the interconnection scheme. In information, as equipment shrinks, the power contributes of NoC links starts to compete with that of NoC routers. In this paper, we propose the use of clock gating in the data encoding techniques as a viable way to reduce both power dissipation and time consumption of NoC links. The projected scramble scheme exploits the wormhole switching techniques. That is, flits are scramble by the network interface (NI) before they are injected in the network and are decoded by the target NI. This makes the scheme transparent to the underlying network since the encoder and decoder logic is integrated in the NI and no modification of the routers structural design is required. We review the projected scramble scheme on a set of representative data streams (both synthetic and extracted from real applications) showing that it is possible to reduce the power contribution of both the self-switching activity and the coupling switching activity in inter-routers links.

Keywords: Xilinx 12.1, power consumption, Encoder, NOC

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Authors: M. S. Kaiser, S. Reaz Ahmed

Abstract:

Chip formation characteristics are investigated during surface finishing of high density polyethylene (HDPE) samples using a shaper machine. Both the cutting speed and depth of cut are varied continually to enable observations under various machining conditions. The generated chips are analyzed in terms of their shape, size, and deformation. Their physical appearances are also observed using digital camera and optical microscope. The investigation shows that continuous chips are obtained for all the cutting conditions. It is observed that cutting speed is more influential than depth of cut to cause dimensional changes of chips. Chips curl radius is also found to increase gradually with the increase of cutting speed. The length of continuous chips remains always smaller than the job length, and the corresponding discrepancies are found to be more prominent at lower cutting speed. Microstructures of the chips reveal that cracks are formed at higher cutting speeds and depth of cuts, which is not that significant at low depth of cut.

Keywords: HDPE, surface-finishing, chip formation, deformation, roughness

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Authors: Ying Li, Rui Hu, Shizhen Chen, Xin Zhou, Yunhuang Yang

Abstract:

Prostate cancer is one of the leading causes of cancer-related death among men. Prostate-specific antigen (PSA), a specific product of prostatic epithelial cells, is an important indicator of prostate cancer. Though PSA is not a specific serum biomarker for the screening of prostate cancer, it is recognized as an indicator for prostate cancer recurrence and response to therapy for patient’s post-prostatectomy. Since radical prostatectomy eliminates the source of PSA production, serum PSA levels fall below 50 pg/mL, and may be below the detection limit of clinical immunoassays (current clinical immunoassay lower limit of detection is around 10 pg/mL). Many clinical studies have shown that intervention at low PSA levels was able to improve patient outcomes significantly. Therefore, ultra-sensitive and precise assays that can accurately quantify extremely low levels of PSA (below 1-10 pg/mL) will facilitate the assessment of patients for the possibility of early adjuvant or salvage treatment. Currently, the commercially available ultra-sensitive ELISA kit (not used clinically) can only reach a detection limit of 3-10 pg/mL. Other platforms developed by different research groups could achieve a detection limit as low as 0.33 pg/mL, but they relied on sophisticated instruments to get the final readout. Herein we report a microfluidic platform for point-of-care (POC) detection of PSA with a detection limit of 0.5 pg/mL and without the assistance of any equipment. This platform is based on a previously reported volumetric-bar-chart chip (V-Chip), which applies platinum nanoparticles (PtNPs) as the ELISA probe to convert the biomarker concentration to the volume of oxygen gas that further pushes the red ink to form a visualized bar-chart. The length of each bar is used to quantify the biomarker concentration of each sample. We devised a long reading channel V-Chip (LV-Chip) in this work to achieve a wide detection window. In addition, LV-Chip employed a unique enzyme-free ELISA probe that enriched PtNPs significantly and owned 500-fold enhanced catalytic ability over that of previous V-Chip, resulting in a significantly improved detection limit. LV-Chip is able to complete a PSA assay for five samples in 20 min. The device was applied to detect PSA in 50 patient serum samples, and the on-chip results demonstrated good correlation with conventional immunoassay. In addition, the PSA levels in finger-prick whole blood samples from healthy volunteers were successfully measured on the device. This completely stand-alone LV-Chip platform enables convenient POC testing for patient follow-up in the physician’s office and is also useful in resource-constrained settings.

Keywords: point-of-care detection, microfluidics, PSA, ultra-sensitive

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Authors: M. K. Benhaoua, A. K. Singh, A. E. H. Benyamina

Abstract:

In this paper, we propose heuristic for dynamic communications mapping that considers the placement of communications in order to optimize the overall performance. The mapping technique uses a newly proposed Algorithm to place communications between the tasks. The placement we propose of the communications leads to a better optimization of several performance metrics (time and energy consumption). Experimental results show that the proposed mapping approach provides significant performance improvements when compared to those using static routing.

Keywords: Multi-Processor Systems-on-Chip (MPSoCs), Network-on-Chip (NoC), heterogeneous architectures, dynamic mapping heuristics

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Authors: Han-Bin Park, Taesam Kang, SunKi Hong, Jeong Hoi Gu

Abstract:

The piezoelectric material is being used widely for actuators due to its large power density with simple structure. It can generate a larger force than the conventional actuators with the same size. Furthermore, the response time of piezoelectric actuators is very short, and thus, it can be used for very fast system applications with compact size. To control the piezoelectric actuator, we need analog signal conditioning circuits as well as digital microcontrollers. Conventional microcontrollers are not equipped with analog parts and thus the control system becomes bulky compared with the small size of the piezoelectric devices. To overcome these weaknesses, we are developing one-chip micro controller that can handle analog and digital signals simultaneously using mixed signal FPGA technology. We used the SmartFusion™ FPGA device that integrates ARM®Cortex-M3, analog interface and FPGA fabric in a single chip and offering full customization. It gives more flexibility than traditional fixed-function microcontrollers with the excessive cost of soft processor cores on traditional FPGAs. In this paper we introduce the design of single chip controller using mixed signal FPGA, SmartFusion™[1] device. To demonstrate its performance, we implemented a PI controller for power driving circuit and a 5th order H-infinity controller for the system with piezoelectric actuator in the FPGA fabric. We also demonstrated the regulation of a power output and the operation speed of a 5th order H-infinity controller.

Keywords: mixed signal FPGA, PI control, piezoelectric actuator, SmartFusion™

Procedia PDF Downloads 506