Search results for: low voltage differential signaling

Authors: Monika Rawat, Rahul Kumar

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Input output Buffer Information Specification (IBIS) models are used for describing the analog behavior of the Input Output (I/O) buffers of a digital device. They are widely used to perform signal integrity analysis. Advantages of using IBIS models include simple structure, IP protection and fast simulation time with reasonable accuracy. As design complexity of driver and receiver increases, capturing exact behavior from transistor level model into IBIS model becomes an essential task to achieve better accuracy. In this paper, an improvement in existing methodology of generating IBIS model for complex I/O interfaces such as Inter-Integrated Circuit (I2C) and Low Voltage Differential Signaling (LVDS) is proposed. Furthermore, the accuracy and computational performance of standard method and proposed approach with respect to SPICE are presented. The investigations will be useful to further improve the accuracy of IBIS models and to enhance their wider acceptance.

Keywords: IBIS, signal integrity, open-drain buffer, low voltage differential signaling, behavior modelling, transient simulation

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Authors: Shih-Hao Chen, Chi-Wai Chow

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Visible light communication combined with spread spectrum modulation is demonstrated in this study. Differential signaling method also ensures the proposed system that can support high immunity to ambient light interference. Experiment result shows the proposed system has 6 dB gain comparing with the original On-Off Keying modulation scheme.

Keywords: Visible Light Communication (VLC), Spread Spectrum Modulation (SSM), On-Off Keying, visible light communication

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Authors: Chih-Hsiang Chang, I-Fan Ho

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This study examines the credibility of the signaling as explanation for IPO initial underpricing. Findings reveal the initial underpricing and the long-term underperformance of IPOs in Taiwan. However, we only find weak support for signaling as explanation of IPO underpricing.

Keywords: signaling, IPO initial underpricing, IPO long-term underperformance, Taiwan’s stock market

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Authors: Hafez Fouad

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Telemedicine applications have very low voltage which required High Precision Rectifier Design with high Sensitivity to operate at minimum input Voltage. In this work, we targeted 0.2V input voltage using 65 nm CMOS rectifier for Energy Harvesting Telemedicine application. The proposed rectifier which designed at 2.4GHz using two-stage structure found to perform in a better case where minimum operation voltage is lower than previous published paper and the rectifier can work at a wide range of low input voltage amplitude. The Performance Summary of Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2 V are 490.9 mV and 1.997 V, maximum VCE = 99.85 % and maximum PCE = 46.86 %. The Performance Summary of Differential drive CMOS rectifier with external bootstrapping circuit rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2V are 265.5 mV (0.265V) and 1.467 V respectively, maximum VCE = 93.9 % and maximum PCE= 15.8 %.

Keywords: energy harvesting, embedded system, IoT telemedicine system, threshold voltage minimization, differential drive cmos rectifier, full-wave fully gate cross-coupled rectifiers CMOS rectifier

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Authors: Hyeon Su Kim, Sungjin Park, Hae Ryung Chang, Hae Rim Jung, Young Zoo Ahn, Yon Hui Kim, Seungyoon Nam

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Ependymoma, one of the most common parenchymal spinal cord tumor, represents 3-6% of all CNS tumor. Especially intracranial ependymomas, which are more frequent in childhood, have a more poor prognosis and more malignant than spinal ependymomas. Although there are growing needs to understand pathogenesis, detailed molecular understanding of pathogenesis remains to be explored. A cancer cell is composed of complex signaling pathway networks, and identifying interaction between genes and/or proteins are crucial for understanding these pathways. Therefore, we explored each ependymoma in terms of differential expressed genes and signaling networks. We used Microsoft Excel™ to manipulate microarray data gathered from NCBI’s GEO Database. To analyze and visualize signaling network, we used web-based PATHOME algorithm and Cytoscape. We show HOX family and NEFL are down-regulated but SCL family is up-regulated in cerebrum and posterior fossa cancers over a spinal cancer, and JAK/STAT signaling pathway and Chemokine signaling pathway are significantly different in the both intracranial ependymoma comparing to spinal ependymoma. We are considering there may be an age-dependent mechanism under different histological pathogenesis. We annotated mutation data of each gene subsequently in order to find potential target genes.

Keywords: systems biology, ependymoma, deg, network analysis

Procedia PDF Downloads 277

Authors: D. J. Dahigaonkar, D. G. Wakde

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The performance analysis of low voltage low power CMOS OTA is presented in this paper. The differential input single output OTA is simulated in 180nm CMOS process technology. The simulation results indicate high bandwidth of the order of 7.04GHz with 0.766mW power consumption and transconductance of -71.20dB. The total harmonic distortion for 100mV input at a frequency of 1MHz is found to be 2.3603%. In addition to this, to establish comparative analysis of designed OTA and analyze effect of technology scaling, the differential input single output OTA is further simulated using 350nm CMOS process technology and the comparative analysis is presented in this paper.

Keywords: Operational Transconductance Amplifier, Total Harmonic Distortions, low voltage/low power, power dissipation

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Authors: Milad Kaboli

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A new CMOS low voltage current-mode four-quadrant analog multiplier based on the squarer circuit with voltage output is presented. The proposed circuit is composed of a pair of current subtractors, a pair differential-input V-I converters and a pair of voltage squarers. The circuit was simulated using HSPICE simulator in standard 0.18 μm CMOS level 49 MOSIS (BSIM3 V3.2 SPICE-based). Simulation results show the performance of the proposed circuit and experimental results are given to confirm the operation. This topology of multiplier results in a high-frequency capability with low power consumption. The multiplier operates for a power supply ±1.2V. The simulation results of analog multiplier demonstrate a THD of 0.65% in 10MHz, a −3dB bandwidth of 1.39GHz, and a maximum power consumption of 7.1mW.

Keywords: analog processing circuit, WTA, LTA, low voltage

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Authors: Bo Bae Song, Byung Seok Lee, Hyun young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3, and D4).

Keywords: ESD, SCR, holding voltage, latch-up

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Authors: Ibtisam Masmali, Edwin Beggs

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In this paper, we take example of differential calculi, on the finite group A4. Then, we apply methods of non-commutative of non-commutative differential geometry to this example, and see how similar the results are to those of classical differential geometry.

Keywords: differential calculi, finite group A4, Christoffel symbols, covariant derivative, torsion compatible

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Authors: Atabak Faramarzpour, Mohsen Mohammadian

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In this article, we introduce the stability of power system voltage and state DG power plants placement and its effect on improving voltage security margin in radial distribution networks. For this purpose, first, important definitions in voltage stability area such as small and big voltage disturbances, instability, and voltage collapse, and voltage security definitions are stated. Then, according to voltage collapse time, voltage stability is classified and each one's characteristics are stated.

Keywords: DG power plants, evaluation, voltage security, radial distribution networks

Procedia PDF Downloads 646

Authors: Maziar Yazdani, Ahmad Khodaee, Fatemeh Hajizadeh

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The purpose of this research was analysis of the reliability of the signaling system in the railway and planning repair and maintenance of its subsystems. For this purpose, it will be endeavored to introduce practical strategies for activities control and appropriate planning for repair and preventive maintenance by statistical modeling of reliability. Therefore, modeling, evaluation, and promotion of reliability of the signaling system appear very critical. Among the key goals of the railway is provision of quality service for passengers and this purpose is gained by increasing reliability, availability, maintainability and safety of (RAMS). In this research, data were analyzed, and the reliability of the subsystems and entire system was calculated and with emphasis on preservation of performance of each of the subsystems with a reliability of 80%, a plan for repair and preventive maintenance of the subsystems of the signaling system was introduced.

Keywords: reliability, modeling reliability, plan for repair and preventive maintenance, signaling system

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Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

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In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Mohammad Arif Sobhan Bhuiyan, Zainal Abidin Nordin, Mamun Bin Ibne Reaz

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A compact and power efficient high performance Voltage Controlled Oscillator (VCO) is a must in analog and digital circuits especially in the communication system, but the best trade-off among the performance parameters is a challenge for researchers. In this paper, a design of a compact 3-stage differential voltage controlled ring oscillator (VCRO) with low phase noise, low power and higher tuning bandwidth is proposed in 0.18 µm CMOS technology. The VCRO is designed with symmetric load and positive feedback techniques to achieve higher gain and minimum delay. The proposed VCRO can operate at tuning range of 3.9-5.0 GHz at 1.6 V supply voltage. The circuit consumes only 1.0757 mW of power and produces -129 dbc/Hz. The total active area of the proposed VCRO is only 11.74 x 37.73 µm2. Such a VCO can be the best choice for compact and low-power RF applications.

Keywords: CMOS, VCO, VCRO, oscillator

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Authors: Mamidi Ramakrishna Rao

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Doubly-fed induction generators (DFIG) due to their advantages like speed variation and four-quadrant operation, find its application in wind turbines. DFIG besides supplying power to the grid has to support reactive power (kvar) under grid voltage variations, should contribute minimum fault current during faults, have high efficiency, minimum weight, adequate rotor protection during crow-bar-operation from +20% to -20% of rated speed.  To achieve the optimum performance, a good electromagnetic design of DFIG is required. In this paper, a simple and heuristic global optimization – Differential Evolution has been used. Variables considered are lamination details such as slot dimensions, stack diameters, air gap length, and generator stator and rotor stack length. Two operating conditions have been considered - voltage and speed variations. Constraints included were reactive power supplied to the grid and limiting fault current and torque. The optimization has been executed separately for three objective functions - maximum efficiency, weight reduction, and grid fault stator currents. Subsequent calculations led to the conclusion that designs determined through differential evolution help in determining an optimum electrical design for each objective function.

Keywords: design optimization, performance, DFIG, differential evolution

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Authors: Mohd Ali Abbas Zaidi, Meenu Sachdeva, Jonaki Sen

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In the vertebrate embryo, the forebrain anlagen develops from the anterior-most region of the neural tube which is the precursor of the central nervous system (CNS). The roof plate located at the dorsal midline region of the forebrain anlagen, acts as a source of several secreted molecules involved in patterning and morphogenesis of the forebrain. One such key morphogenetic event is the invagination of the forebrain roof plate which results in separation of the single forebrain vesicle into two cerebral hemispheres. Retinoic acid (RA) signaling plays a key role in this process. Blocking RA signaling at the dorsal forebrain midline inhibits dorsal invagination and results in the absence of certain key features of this region, such as thinning of the neuroepithelium and a lowering of cell proliferation. At present we are investigating the possibility of other signaling pathways acting in concert with RA signaling to regulate this process. We have focused on BMP signaling, which we found to be active in a mutually exclusive domain to that of RA signaling within the roof plate. We have also observed that there is a change in BMP signaling activity on modulation of RA signaling indicating an antagonistic relationship between the two. Moreover, constitutive activation of BMP signaling seems to completely inhibit thinning and partially affect invagination, leaving the lowering of cell proliferation in the midline unaffected. We are employing in-silico modeling as well as molecular manipulations to investigate the relative contribution if any, of regional differences in rates of cell proliferation and thinning of the neuroepithelium towards the process of invagination. We have found expression of certain cell adhesion molecules in forebrain roof-plate whose mRNA localization across the thickness of neuroepithelium is influenced by Bmp and RA signaling, giving regional rigidity to roof plate and assisting invagination. We also found expression of certain cytoskeleton modifiers in a localized small domains in invaginating forebrain roof plate suggesting that midline invagination is under control of many factors.

Keywords: bone morphogenetic signaling, cytoskeleton, cell adhesion molecules, forebrain roof plate, retinoic acid signaling

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Authors: Sun-Ki Hong, Nam-HeeByeon, Jung-Seop Lee, Tae-Sam Kang

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For Common R or R-L load to apply arbitrary voltage, the bridge traditional inverters don’t have any difficulties by PWM method. However for driving some piezoelectric actuator, arbitrary voltage not a pulse but a steady voltage should be applied. Piezoelectric load is considered as R-C load and its voltage does not decrease even though the applied voltage decreases. Therefore it needs some special inverter with circuit that can discharge the capacitive energy. Especially for unidirectional arbitrary voltage driving like as sine wave, it becomes more difficult problem. In this paper, a charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator is proposed. The circuit has charging and discharging switches for increasing and decreasing output voltage. With the proposed simple circuit, the load voltage can have any unidirectional level with tens of bandwidth because the load voltage can be adjusted by switching the charging and discharging switch appropriately. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: DC-DC converter, analog output voltage, sinusoidal drive, piezoelectric load, discharging circuit

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Authors: Hyun Young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon Cho, Yong Seo Koo

Abstract:

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp

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Authors: Mohammad M. Aria, Fatma Öz, Yashar Esmaeilian, Marco Carofiglio, Valentina Cauda, Özlem Yalçın

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Photoelectrical stimulation of cells with semiconductor organic polymers have been shown promising applications in neuroprosthetics such as retinal prosthesis. Photoelectrical stimulation of the cell membranes can be induced through a photo-electric charge separation mechanism in the semiconductor materials, and it can alter intracellular calcium level through both stimulation of voltage-gated ion channels and increase of intracellular reactive oxygen species (ROS) level. On the other hand, targeting voltage-gated ion channels in cancer cells to induce cell apoptosis through calcium signaling alternation is an effective mechanism which has been explained before. In this regard, remote control of the voltage-gated ion channels aimed to alter intracellular calcium by using photo-active organic polymers can be novel technology in cancer therapy. In this study, we used P (ITO/Indium thin oxide)/P3HT(poly(3-hexylthiophene-2,5-diyl)) and PN (ITO/ZnO/P3HT) photovoltaic junctions to stimulate MDA-MB-231 breast cancer cells. We showed that the photo-stimulation of breast cancer cells through photo capacitive current generated by the photovoltaic junctions are able to excite the cells and alternate intracellular calcium based on the calcium imaging (at 8mW/cm² green light intensity and 10-50 ms light durations), which has been reported already to safety stimulate neurons. The control group did not undergo light treatment and was cultured in T-75 flasks. We detected 20-30% cell death for ITO/P3HT and 51-60% cell death for ITO/ZnO/P3HT samples in the light treated MDA-MB-231 cell group. Western blot analysis demonstrated poly(ADP-ribose) polymerase (PARP) activated cell death in the light treated group. Furthermore, Annexin V and PI fluorescent staining indicated both apoptosis and necrosis in treated cells. In conclusion, our findings revealed that the photoelectrical stimulation of cells (through long time overstimulation) can induce cell death in cancer cells.

Keywords: Ca²⁺ signaling, cancer therapy, electrically excitable cells, photoelectrical stimulation, voltage-gated ion channels

Procedia PDF Downloads 156

Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

Procedia PDF Downloads 357

Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

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In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Sun-Ki Hong, Yong-Ho Cho, Ki-Seok Kim, Tae-Sam Kang

Abstract:

Piezoelectric actuator is treated as RC load when it is modeled electrically. For some piezoelectric actuator applications, arbitrary voltage is required to actuate. Especially for unidirectional arbitrary voltage driving like as sine wave, some special inverter with circuit that can charge and discharge the capacitive energy can be used. In this case, the difference between power supply level and the object voltage level for RC load is varied. Because the control gain is constant, the controlled output is not uniform according to the voltage difference. In this paper, for charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator, the controller gain is controlled according to the voltage difference. With the proposed simple idea, the load voltage can have controlled smoothly although the voltage difference is varied. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: analog voltage inverter, capacitive load, gain control, dc-dc converter, piezoelectric, voltage waveform

Procedia PDF Downloads 632

Authors: H. H. Goh, Q. S. Chua, S. W. Lee, B. C. Kok, K. C. Goh, K. T. K. Teo

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At present, the evaluation of voltage stability assessment experiences sizeable anxiety in the safe operation of power systems. This is due to the complications of a strain power system. With the snowballing of power demand by the consumers and also the restricted amount of power sources, therefore, the system has to perform at its maximum proficiency. Consequently, the noteworthy to discover the maximum ability boundary prior to voltage collapse should be undertaken. A preliminary warning can be perceived to evade the interruption of power system’s capacity. The effectiveness of line voltage stability indices (LVSI) is differentiated in this paper. The main purpose of the indices is used to predict the proximity of voltage instability of the electric power system. On the other hand, the indices are also able to decide the weakest load buses which are close to voltage collapse in the power system. The line stability indices are assessed using the IEEE 14 bus test system to validate its practicability. Results demonstrated that the implemented indices are practically relevant in predicting the manifestation of voltage collapse in the system. Therefore, essential actions can be taken to dodge the incident from arising.

Keywords: critical line, line outage, line voltage stability indices (LVSI), maximum loadability, voltage collapse, voltage instability, voltage stability analysis

Procedia PDF Downloads 331

Authors: Kang Hyun Yi

Abstract:

This paper presents a new parallel output LLC DC/DC converter for electric vehicle. The electric vehicle has two batteries. One is a high voltage battery for the powertrain of the vehicle and the other is a low voltage battery for the vehicle electric system. The low voltage is charged from the high voltage battery and the high voltage input and the high current output DC/DC converter is needed. Therefore, the new LLC converter with the input voltage compensation is proposed for the high voltage input and the low voltage output DC/DC converter. The proposed circuit has two LLC converters with the series input voltage from the battery for the powertrain and the parallel output low battery voltage for the vehicle electric system because the battery voltage for the powertrain and the electric power for the vehicle become high. Also, the input series voltage compensation capacitor is used for balancing the input current in the two LLC converters. The proposed converter has an equal electric stress of the semiconductor parts and the reactive components, high efficiency and good heat dissipation.

Keywords: electric vehicle, LLC DC/DC converter, input voltage balancing, parallel output

Procedia PDF Downloads 1028

Authors: Fuziyah Ishak, Siti Norazura Ahmad

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Volterra integro-differential equations appear in many models for real life phenomena. Since analytical solutions for this type of differential equations are hard and at times impossible to attain, engineers and scientists resort to numerical solutions that can be made as accurately as possible. Conventionally, numerical methods for ordinary differential equations are adapted to solve Volterra integro-differential equations. In this paper, numerical solution for solving Volterra integro-differential equation using extended trapezoidal method is described. Formulae for the integral and differential parts of the equation are presented. Numerical results show that the extended method is suitable for solving first order Volterra integro-differential equations.

Keywords: accuracy, extended trapezoidal method, numerical solution, Volterra integro-differential equations

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Authors: A. C. Sarmah

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The Al-MoO3-P-CdTe-Al MOS sandwich structures were fabricated by vacuum deposition method on cleaned glass substrates. Capacitance versus voltage measurements were performed at different frequencies and sweep rates of applied voltages for oxide and semiconductor films of different thicknesses. In the negative voltage region of the C-V curve a high differential capacitance of the semiconductor was observed and at high frequencies (<10 kHz) the transition from accumulation to depletion and further to deep depletion was observed as the voltage was swept from negative to positive. A study have been undertaken to determine the value of acceptor density and some depletion layer parameters such as depletion layer capacitance, depletion width, impurity concentration, flat band voltage, Debye length, flat band capacitance, diffusion or built-in-potential, space charge per unit area etc. These were determined from C-V measurements for different oxide and semiconductor thicknesses.

Keywords: debye length, depletion width, flat band capacitance, impurity concentration

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Authors: Puneet Chawla, Balwinder Singh

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Recently, increased attention has been devoted to the voltage instability phenomenon in power systems. Many techniques have been proposed in the literature for evaluating and predicting voltage stability using steady state analysis methods. In this paper, P-V and Q-V curves have been generated for a 57 bus Patiala Rajpura circle of India. The power-flow program is developed in MATLAB using Newton-Raphson method. Using Q-V curves, the weakest bus of the power system and the maximum reactive power change permissible on that bus is calculated. STATCOMs are placed on the weakest bus to improve the voltage and hence voltage stability and also the power transmission capability of the line.

Keywords: voltage stability, reactive power, power flow, weakest bus, STATCOM

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Authors: A. Kojah, A. Nacaroğlu

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Single phase transmission lines are used to transfer data or energy between two users. Transient conditions such as switching operations and short circuit faults cause the generation of the fluctuation on the waveform to be transmitted. Spatial voltage distribution on the single phase transmission line may change owing to the position and duration of the short circuit fault in the system. In this paper, the state space representation of the single phase transmission line for short circuit fault and for various types of terminations is given. Since the transmission line is modeled in time domain using distributed parametric elements, the mathematical representation of the event is given in state space (time domain) differential equation form. It also makes easy to solve the problem because of the time and space dependent characteristics of the voltage variations on the distributed parametrically modeled transmission line.

Keywords: energy transmission, transient effects, transmission line, transient voltage, RLC short circuit, single phase

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Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

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This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, voltage transition, node stabilization, biasing circuits

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Authors: Amir Mahdavi

Abstract:

In this paper, a circuit topology of voltage-controlled oscillators (VCO) which is suitable for ultra-low-phase noise operations is introduced. To do so, a new low phase noise cross-coupled oscillator by using the general topology of cross-coupled oscillator and adding a differential stage for tail current shaping is designed. In addition, a tail current shaping technique to improve phase noise in differential LC VCOs is presented. The tail current becomes large when the oscillator output voltage arrives at the maximum or minimum value and when the sensitivity of the output phase to the noise is the smallest. Also, the tail current becomes small when the phase noise sensitivity is large. The proposed circuit does not use extra power and extra noisy active devices. Furthermore, this topology occupies small area. Simulation results show the improvement in phase noise by 2.5dB under the same conditions and at the carrier frequency of 1 GHz for GSM applications. The power consumption of the proposed circuit is 2.44 mW and the figure of merit (FOM) with -192.2 dBc/Hz is achieved for the new oscillator.

Keywords: LC oscillator, low phase noise, current shaping, diff mode

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Authors: A. Suresh, Sreehari Rao Patri, K. S. R. Krishnaprasad

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An ultra low power capacitor less low-dropout voltage regulator with improved transient response using gain enhanced feed forward path compensation is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor stage in the feed forward path with regular error amplifier to form a composite gain-enhanced feed forward stage. It broadens the gain bandwidth and thus improves the transient response without substantial increase in power consumption. The proposed LDO, designed for a maximum output current of 100 mA in UMC 180 nm, requires a quiescent current of 69 µA. An undershoot of 153.79mV for a load current changes from 0mA to 100mA and an overshoot of 196.24mV for current change of 100mA to 0mA. The settling time is approximately 1.1 µs for the output voltage undershoot case. The load regulation is of 2.77 µV/mA at load current of 100mA. Reference voltage is generated by using an accurate band gap reference circuit of 0.8V.The costly features of SOC such as total chip area and power consumption is drastically reduced by the use of only a total compensation capacitance of 6pF while consuming power consumption of 0.096 mW.

Keywords: capacitor-less LDO, frequency compensation, transient response, latch, self-biased differential amplifier

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