Search results for: FPGA (Field-Programmable Gate Array)

Authors: Nikhil Jain, Bin Yu

Abstract:

We explore the potential of using ultra-thin hexagonal boron nitride (h-BN) as both supporting substrate and gate dielectric for graphene-channel field effect transistors (GFETs). Different from commonly used oxide-based dielectric materials which are typically amorphous, very rough in surface, and rich with surface traps, h-BN is layered insulator free of dangling bonds and surface states, featuring atomically smooth surface. In a graphene-channel-last device structure with local buried metal gate electrode (TiN), thin h-BN multilayer is employed as both supporting “substrate” and gate dielectric for graphene active channel. We observed superior carrier mobility and electrical conduction, significantly improved from that in GFETs with SiO2 as substrate/gate insulator. In addition, we report excellent dielectric behavior of layered h-BN, including ultra-low leakage current and high critical electric field for breakdown.

Keywords: graphene, field-effect transistors, hexagonal boron nitride, dielectric strength, tunneling

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Authors: Jongbae Lee, Seongsoo Lee

Abstract:

Modern sensors often embed small-size digital controller for sensor control, value calibration, and signal processing. These sensors require digital data communication with host microprocessors, but conventional digital communication protocols are too heavy for price reduction. SAE J2716 SENT (single edge nibble transmission) protocol transmits direct digital waveforms instead of complicated analog modulated signals. In this paper, a SENT interface is designed in Verilog HDL (hardware description language) and implemented in FPGA (field-programmable gate array) evaluation board. The designed SENT interface consists of frame encoder/decoder, configuration register, tick period generator, CRC (cyclic redundancy code) generator/checker, and TX/RX (transmission/reception) buffer. Frame encoder/decoder is implemented as a finite state machine, and it controls whole SENT interface. Configuration register contains various parameters such as operation mode, tick length, CRC option, pause pulse option, and number of nibble data. Tick period generator generates tick signals from input clock. CRC generator/checker generates or checks CRC in the SENT data frame. TX/RX buffer stores transmission/received data. The designed SENT interface can send or receives digital data in 25~65 kbps at 3 us tick. Synthesized in 0.18 um fabrication technologies, it is implemented about 2,500 gates.

Keywords: digital sensor interface, SAE J2716, SENT, verilog HDL

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

Abstract:

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET

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Authors: Junhong Feng, Wenyu Lu, Xinhong Cheng, Li Zheng, Yuehui Yu

Abstract:

The effects of proton irradiation on the properties of gate oxide were evaluated by monitoring the static parameters (such as threshold voltage and on-resistance) and dynamic parameters (Miller plateau time) of 1700V SiC VDMOS before and after proton irradiation. The incident proton energy was 3MeV, and the doses were 5 × 10¹² P / cm², 1 × 10¹³ P / cm², respectively. The results show that the threshold voltage of MOS exhibits negative drift under proton irradiation, and the near-interface traps in the gate oxide layer are occupied by holes generated by the ionization effect of irradiation, thus forming more positive charges. The basis for selecting TMiller is that the change time of Vgs is the time when Vds just shows an upward trend until it rises to a stable value. The degradation of the turn-off time of the Miller platform verifies that the capacitance Cgd becomes larger, reflecting that the gate oxide layer is introduced into the trap by the displacement effect caused by proton irradiation, and the interface state deteriorates. As a more sensitive area in the irradiation process, the gate oxide layer will be optimized for its parameters (such as thickness, type, etc.) in subsequent studies.

Keywords: SiC VDMOS, proton radiation, Miller time, gate oxide

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Authors: A. E. El-Henawey, A. A. El-Kouny, M. M. Abd –El-Halim

Abstract:

Moving target indication (MTI) which is an anti-clutter technique that limits the display of clutter echoes. It uses the radar received information primarily to display moving targets only. The purpose of MTI is to discriminate moving targets from a background of clutter or slowly-moving chaff particles as shown in this paper. Processing system in these radars is so massive and complex; since it is supposed to perform a great amount of processing in very short time, in most radar applications the response of a single canceler is not acceptable since it does not have a wide notch in the stop-band. A double-delay canceler is an MTI delay-line canceler employing the two-delay-line configuration to improve the performance by widening the clutter-rejection notches, as compared with single-delay cancelers. This canceler is also called a double canceler, dual-delay canceler, or three-pulse canceler. In this paper, a double delay line canceler is chosen for study due to its simplicity in both concept and implementation. Discussing the implementation of a simple digital moving target indicator (DMTI) using FPGA which has distinct advantages compared to other application specific integrated circuit (ASIC) for the purposes of this work. The FPGA provides flexibility and stability which are important factors in the radar application.

Keywords: FPGA, MTI, double delay line canceler, Doppler Shift

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Authors: Tran Trong Thang, Nguyen Phan Kien, Trinh Quang Duc

Abstract:

The phased-array ultrasound transducer types are utilities for medical ultrasonography as well as optical imaging. However, their discontinuity characteristic limits the applications due to the artifacts contaminated into the reconstructed images. Because of the effects of the ultrasound pressure field pattern to the echo ultrasonic waves as well as the optical modulated signal, the side lobes of the focused ultrasound beam induced by discontinuity of the phased-array ultrasound transducer might the reason of the artifacts. In this paper, a simple method in approach of numerical simulation was used to investigate the limitation of discontinuity of the elements in phased-array ultrasound transducer and their effects to the ultrasound pressure field. Take into account the change of ultrasound pressure field patterns in the conditions of variation of the pitches between elements of the phased-array ultrasound transducer, the appropriated parameters for phased-array ultrasound transducer design were asserted quantitatively.

Keywords: phased-array ultrasound transducer, sound pressure pattern, discontinuous sound field, numerical visualization

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Authors: Olomon Wu, Hung Lu, Nick Wilkins, Daniel Kerr, Zekeriya Aliyazicioglu, H. K. Hwang

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Multiple Input Multiple Output (MIMO) radar has received increasing attention in recent years. MIMO radar has many advantages over conventional phased array radar such as target detection, resolution enhancement, and interference suppression. In this paper, the results are presented from a simulation study of MIMO Uniformly-Spaced Linear Array (ULA) antennas. The performance is investigated under varied parameters, including varied array size, Pseudo Random (PN) sequence length, number of snapshots, and Signal to Noise Ratio (SNR). The results of MIMO are compared to a traditional array antenna.

Keywords: MIMO radar, phased array antenna, target detection, radar signal processing

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Authors: Adhinarayanan Venkatasubramanian

Abstract:

For design of high speed digital circuit wave pipeline is the best approach this can be operated at higher operating frequencies by adjusting clock periods and skews so as latch the o/p of combinational logic circuit at the stable period. In this paper, there are two methods are proposed in automation task one is BIST (Built in self test) and second method is Reconfigurable technique. For the above two approaches dedicated AND gate (multiplier) by applying wave pipeline technique. BIST approach is implemented by Xilinx Spartan-II device. In reconfigurable technique done by ASIC. From the results, wave pipeline circuits are faster than nonpipeline circuit and area, power dissipation are reduced by reconfigurable technique.

Keywords: SOC, wave-pipelining, FPGA, self-testing, reconfigurable, ASIC

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Authors: Erwan Negre, Ewan J. O'Connor, Juha Toivonen

Abstract:

The need for CO2 monitoring technologies grows simultaneously with the worldwide concerns regarding environmental challenges. To that purpose, we developed a compact coherent all-fiber ranged-resolved Differential Absorption Lidar (RR-DIAL). It has been designed along a tunable 2x1fiber optic switch set to a frequency of 1 Hz between two Distributed FeedBack (DFB) lasers emitting in the continuous-wave mode at 1571.41 nm (absorption line of CO2) and 1571.25 nm (CO2 absorption-free line), with linewidth and tuning range of respectively 1 MHz and 3 nm over operating wavelength. A three stages amplification through Erbium and Erbium-Ytterbium doped fibers coupled to a Radio Frequency (RF) driven Acousto-Optic Modulator (AOM) generates 100 ns pulses at a repetition rate from 10 to 30 kHz with a peak power up to 2.5 kW and a spatial resolution of 15 m, allowing fast and highly resolved CO2 profiles. The same afocal collection system is used for the output of the laser source and the backscattered light which is then directed to a circulator before being mixed with the local oscillator for heterodyne detection. Packaged in an easily transportable box which also includes a server and a Field Programmable Gate Array (FPGA) card for on-line data processing and storing, our setup allows an effective and quick deployment for versatile in-situ analysis, whether it be vertical atmospheric monitoring, large field mapping or sequestration site continuous oversight. Setup operation and results from initial field measurements will be discussed.

Keywords: CO2 profiles, coherent DIAL, in-situ atmospheric sensing, near infrared fiber source

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Authors: M. Y. Ismail, M. Inam, A. F. M. Zain, N. Misran

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Progressive phase distribution is an important consideration in reflect array antenna design which is required to form a planar wave in front of the reflect array aperture. This paper presents a detailed mathematical model in order to determine the required reflection phase values from individual element of a reflect array designed in Ku-band frequency range. The proposed technique of obtaining reflection phase can be applied for any geometrical design of elements and is independent of number of array elements. Moreover the model also deals with the solution of reflect array antenna design with both centre and off-set feed configurations. The theoretical modeling has also been implemented for reflect arrays constructed on 0.508 mm thickness of different dielectric substrates. The results show an increase in the slope of the phase curve from 4.61°/mm to 22.35°/mm by varying the material properties.

Keywords: mathematical modeling, progressive phase distribution, reflect array antenna, reflection phase

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Authors: Rawad Asfour, Salam Khamas, Edward A. Ball

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This paper is focused on the design of an mm-wave phased array. To date, linear polarization is adapted in the reported designs of phased arrays. However, linear polarization faces several well-known challenges. As such, an advanced design for phased array antennas is required that offers circularly polarized (CP) radiation. A feasible solution for achieving CP phased array antennas is proposed using open-circular loop antennas. To this end, a 3-element circular loop phased array antenna is designed to operate at 28GHz. In addition, the array ability to control the direction of the main lobe is investigated. The results show that the highest achievable field of view (FOV) is 100°, i.e., 50° to the left and 50° to the right-hand side directions. The results are achieved with a CP bandwidth of 15%. Furthermore, the results demonstrate that a high broadside gain of circa 11 dBi can be achieved for the steered beam. Besides, a radiation efficiency of 97 % can also be achieved based on the proposed design.

Keywords: loop antenna, phased array, beam steering, wide bandwidth, circular polarization, CST

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Authors: Vinay Kumar K. S., Shravani V., Spoorthi G., Udith K. S., Divya T. M., Venkatesha M.

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In this work, the mathematical modeling, design and analysis of a 2×2 microstrip patch antenna array (MSPA) antenna configuration is presented. Array utilizes a tiny strip antenna module with two vertical slots for 5G applications at an operating frequency of 5.3 GHz. The proposed array of antennas where the phased array antenna systems (PAAS) are used ubiquitously everywhere, from defense radar applications to commercial applications like 5G/6G. Microstrip patch antennae with slot arrays for linear polarisation parallel and perpendicular to the axis, respectively, are fed through transverse slots in the side wall of the circular waveguide and fed through longitudinal slots in the small wall of the rectangular waveguide. The microstrip patch antenna is developed using Ansys HFSS (High-Frequency Structure Simulator), this simulation tool. The maximum gain of 6.14 dB is achieved at 5.3 GHz for a single MSPA. For 2×2 array structure, a gain of 7.713 dB at 5.3 GHz is observed. Such antennas find many applications in 5G devices and technology.

Keywords: Ansys HFSS, gain, return loss, slot array, microstrip patch antenna, 5G antenna

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Authors: Kaivan Karami, Sahalu Hassan, Sanna Taking, Afesome Ofiare, Aniket Dhongde, Abdullah Al-Khalidi, Edward Wasige

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We have made a comparative study on the influence of Al₂O₃ and HfO₂ grown using atomic layer deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of Al₂O₃ and HfO₂ respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al₂O₃ gate dielectric layers respectively. The negative shift for the 20 nm HfO2 and 20 nm Al₂O₃ were 1.2 V and 4.9 V respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO₂ than Al₂O₃. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 10^4 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Mohamad Khairi Ishak

Abstract:

Conventional public key crypto systems such as RSA (Ron Rivest, Adi Shamir and Leonard Adleman), DSA (Digital Signature Algorithm), and Elgamal are no longer efficient to be implemented in the small, memory constrained devices. Elliptic Curve Cryptography (ECC), which allows smaller key length as compared to conventional public key crypto systems, has thus become a very attractive choice for many applications. This paper describes implementation of an elliptic curve cryptography (ECC) encryption engine on a FPGA. The system has been implemented in 2 different key sizes, which are 131 bits and 163 bits. Area and timing analysis are provided for both key sizes for comparison. The crypto system, which has been implemented on Altera’s EPF10K200SBC600-1, has a hardware size of 5945/9984 and 6913/9984 of logic cells for 131 bits implementation and 163 bits implementation respectively. The crypto system operates up to 43 MHz, and performs point multiplication operation in 11.3 ms for 131 bits implementation and 14.9 ms for 163 bits implementation. In terms of speed, our crypto system is about 8 times faster than the software implementation of the same system.

Keywords: elliptic curve cryptography, FPGA, key sizes, memory

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Authors: Yuji Kageyama, Shin Nagata, Tatsuya Takino, Izuru Nomura, Hiroyuki Kamata

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In previous study, technique to estimate a self-location by using a lunar image is proposed. We consider the improvement of the conventional method in consideration of FPGA implementation in this paper. Specifically, we introduce Artificial Bee Colony algorithm for reduction of search time. In addition, we use fixed point arithmetic to enable high-speed operation on FPGA.

Keywords: SLIM, Artificial Bee Colony Algorithm, location estimate, evolutional triangle similarity

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Authors: Noha M. Rashad, W. Swelam, M. H. Abd ElAzeem

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A simple design of array antenna is presented in this paper, supporting millimeter wave applications which can be used in short range wireless communications such as 5G applications. This design enhances the use of V-band, according to IEEE standards, as the antenna works in the 70 GHz band with bandwidth more than 11 GHz and peak gain more than 13 dBi. The design is simulated using different numerical techniques achieving a very good agreement.

Keywords: 5G technology, array antenna, microstrip, millimeter wave

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Authors: Mahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Henk Corporaal

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Recently, Statistic Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in aeronautics and space systems where high dependability is demanded and considered as a mandatory requirement. Since design’s circuit is stored in configuration memory in SRAM-based FPGAs; they are very sensitive to Single Event Upsets (SEUs). In addition, the adverse effects of SEUs on the electronics used in space are much higher than in the Earth. Thus, developing fault tolerant techniques play crucial roles for the use of SRAM-based FPGAs in space. However, fault tolerance techniques introduce additional penalties in system parameters, e.g., area, power, performance and design time. In this paper, an accurate estimation of configuration memory vulnerability to SEUs is proposed for approximate-tolerant applications. This vulnerability estimation is highly required for compromising between the overhead introduced by fault tolerance techniques and system robustness. In this paper, we study applications in which the exact final output value is not necessarily always a concern meaning that some of the SEU-induced changes in output values are negligible. We therefore define and propose Approximate-based Configuration Memory Vulnerability Factor (ACMVF) estimation to avoid overestimating configuration memory vulnerability to SEUs. In this paper, we assess the vulnerability of configuration memory by injecting SEUs in configuration memory bits and comparing the output values of a given circuit in presence of SEUs with expected correct output. In spite of conventional vulnerability factor calculation methods, which accounts any deviations from the expected value as failures, in our proposed method a threshold margin is considered depending on user-case applications. Given the proposed threshold margin in our model, a failure occurs only when the difference between the erroneous output value and the expected output value is more than this margin. The ACMVF is subsequently calculated by acquiring the ratio of failures with respect to the total number of SEU injections. In our paper, a test-bench for emulating SEUs and calculating ACMVF is implemented on Zynq-7000 FPGA platform. This system makes use of the Single Event Mitigation (SEM) IP core to inject SEUs into configuration memory bits of the target design implemented in Zynq-7000 FPGA. Experimental results for 32-bit adder show that, when 1% to 10% deviation from correct output is considered, the counted failures number is reduced 41% to 59% compared with the failures number counted by conventional vulnerability factor calculation. It means that estimation accuracy of the configuration memory vulnerability to SEUs is improved up to 58% in the case that 10% deviation is acceptable in output results. Note that less than 10% deviation in addition result is reasonably tolerable for many applications in approximate computing domain such as Convolutional Neural Network (CNN).

Keywords: fault tolerance, FPGA, single event upset, approximate computing

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Authors: Ju-Hong Lee, Ching-Wei Liao, Kun-Che Lee

Abstract:

This paper deals with the problem of using antenna sensors for adaptive beamforming in the presence of random steering mismatch. We present an efficient adaptive array beamformer with robustness to deal with the considered problem. The robustness of the proposed beamformer comes from the efficient designation of the steering vector. Using the received array data vector, we construct an appropriate correlation matrix associated with the received array data vector and a correlation matrix associated with signal sources. Then, the eigenvector associated with the largest eigenvalue of the constructed signal correlation matrix is designated as an appropriate estimate of the steering vector. Finally, the adaptive weight vector required for adaptive beamforming is obtained by using the estimated steering vector and the constructed correlation matrix of the array data vector. Simulation results confirm the effectiveness of the proposed method.

Keywords: adaptive beamforming, antenna array, linearly constrained minimum variance, robustness, steering vector

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Authors: Olesya Bolkhovskaya, Alexey Davydov, Alexander Maltsev

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In this paper approach to incoherent signal detection in multi-element antenna array are researched and modeled. Two types of useful signals with unknown wavefront were considered. First one is deterministic (Barker code), the second one is random (Gaussian distribution). The derivation of the sufficient statistics took into account the linearity of the antenna array. The performance characteristics and detecting curves are modeled and compared for different useful signals parameters and for different number of elements of the antenna array. Results of researches in case of some additional conditions can be applied to a digital communications systems.

Keywords: antenna array, detection curves, performance characteristics, quadrature processing, signal detection

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Authors: Somayeh Komeylian

Abstract:

Array signal processing techniques have been recently developing in a variety application of the performance enhancement of receivers by refraining the power of jamming and interference signals. In this scenario, biases induced to the antenna array receiver degrade significantly the accurate estimation of the carrier phase. Owing to the integration of frequency becomes the carrier phase, we have obtained the unbiased doppler frequency for the high precision estimation of carrier phase. The unbiased characteristic of Doppler frequency to the power jamming and the other interference signals allows achieving the highly accurate estimation of phase carrier. In this study, we have rigorously investigated the unbiased characteristic of Doppler frequency to the variation of the antenna array geometries. The simulation results have efficiently verified that the Doppler frequency remains also unbiased and accurate to the variation of antenna array geometries.

Keywords: array signal processing, unbiased doppler frequency, GNSS, carrier phase, and slowly fluctuating point target

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Authors: Shiksha Jain, Ramesh Mishra

Abstract:

One of the most widely used complex signals processing operation is filtering. The most important FIR digital filter are widely used in DSP for filtering to alter the spectrum according to some given specifications. Power consumption and Area complexity in the algorithm of Finite Impulse Response (FIR) filter is mainly caused by multipliers. So we present a multiplier less technique (DA technique). In this technique, precomputed value of inner product is stored in LUT. Which are further added and shifted with number of iterations equal to the precision of input sample. But the exponential growth of LUT with the order of FIR filter, in this basic structure, makes it prohibitive for many applications. The significant area and power reduction over traditional Distributed Arithmetic (DA) structure is presented in this paper, by the use of slicing of LUT to the desired length. An architecture of 16 tap FIR filter is presented, with different length of slice of LUT. The result of FIR Filter implementation on Xilinx ISE synthesis tool (XST) vertex-4 FPGA Tool by using proposed method shows the increase of the maximum frequency, the decrease of the resources as usage saving in area with more number of slices and the reduction dynamic power.

Keywords: multiplier less technique, linear phase symmetric FIR filter, FPGA tool, look up table

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Authors: P. Geetha, R. S. D. Wahida Banu

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The crowning advances in Silicon based electronic technology have dominated the computation world for the past decades. The captivating performance of Si devices lies in sustainable scaling down of the physical dimensions, by that increasing device density and improved performance. But, the fundamental limitations due to physical, technological, economical, and manufacture features restrict further miniaturization of Si based devices. The pit falls are due to scaling down of the devices such as process variation, short channel effects, high leakage currents, and reliability concerns. To fix the above-said problems, it is needed either to follow a new concept that will manage the current hitches or to support the available concept with different materials. The new concept is to design spintronics, quantum computation or two terminal molecular devices. Otherwise, presently used well known three terminal devices can be modified with different materials that suits to address the scaling down difficulties. The first approach will occupy in the far future since it needs considerable effort; the second path is a bright light towards the travel. Modelling paves way to know not only the current-voltage characteristics but also the performance of new devices. So, it is desirable to model a new device of suitable gate control and project the its abilities towards capability of handling high current, high power, high frequency, short delay, and high velocity with excellent electronic and optical properties. Carbon nanotube became a thriving material to replace silicon in nano devices. A well-planned optimized utilization of the carbon material leads to many more advantages. The unique nature of this organic material allows the recent developments in almost all fields of applications from an automobile industry to medical science, especially in electronics field-on which the automation industry depends. More research works were being done in this area. This paper reviews the carbon nanotube field effect transistor with various gate configurations, number of channel element, CNT wall configurations and different modelling techniques.

Keywords: array of channels, carbon nanotube field effect transistor, double gate transistor, gate wrap around transistor, modelling, multi-walled CNT, single-walled CNT

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Authors: N. Massoum, B. Bouazza

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In this paper, we have developed a numerical simulation model to describe the electrical properties of GaInP MESFET with submicron gate (Lg = 0.5 µm). This model takes into account the three-dimensional (3D) distribution of the load in the short channel and the law effect of mobility as a function of electric field. Simulation software based on a stochastic method such as Monte Carlo has been established. The results are discussed and compared with those of the experiment. The result suggests experimentally that, in a very small gate length in our devices (smaller than 40 nm), short-channel tunneling explains the degradation of transistor performance, which was previously enhanced by velocity overshoot.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, simulation software

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Authors: Dia I. Abu-Al-Nadi, M. J. Mismar, T. H. Ismail

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A technique for estimating the direction-of-arrival (DOA) of unknown number of source signals is presented using the eigen-approach. The eigenvector corresponding to the minimum eigenvalue of the autocorrelation matrix yields the minimum output power of the array. Also, the array polynomial with this eigenvector possesses roots on the unit circle. Therefore, the pseudo-spectrum is found by perturbing the phases of the roots one by one and calculating the corresponding array output power. The results indicate that the DOAs and the number of source signals are estimated accurately in the presence of a wide range of input noise levels.

Keywords: array signal processing, direction-of-arrival, antenna arrays, Eigenvalues, Eigenvectors, Lagrange multiplier

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Authors: Le Chen

Abstract:

This paper presents an efficient tool platform scheme to ensure quality protection throughout the software development process. The main principle is to manage the information of requirements, design, development, testing, operation and maintenance process with proper tools, and to set up the quality standards of each process. Through the tools’ display and summary of quality standards, the quality standards can be visualizad and ready for policy decision, which is called Quality Gate in this paper. In addition, the tools are also integrated to achieve the exchange and relation of information which highly improving operational efficiency. In this paper, the feasibility of the scheme is verified by practical application of development projects, and the overall information display and data mining are proposed to be further improved.

Keywords: efficiency, quality gate, software process, tools

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Authors: V. Monisha, D. Sindhuja, M. Sowmiya

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Over the decade, the applications about multimedia have been developed rapidly. The advancement in the communication field at the faster pace, it is necessary to protect the data during transmission. Thus, security of multimedia contents becomes a vital issue, and it is a need for protecting the digital content against malfunctions. Digital watermarking becomes the solution for the copyright protection and authentication of data in the network. In multimedia applications, embedded watermarks should be robust, and imperceptible. For improving robustness, the discrete wavelet transform is used. Both encoding and extraction algorithm can be done using MATLAB R2012a. In this Discrete wavelet transform (DWT) domain of digital image, watermarking algorithm is used, and hardware implementation can be done on Xilinx based FPGA.

Keywords: digital watermarking, DWT, robustness, FPGA

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Authors: Dibyendu Roy, V. Ramu Reddy, Parijat Deshpande, Ranjan Dasgupta

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Imaging of underwater objects is primarily conducted by acoustic imagery due to the severe attenuation of electro-magnetic waves in water. Acoustic imagery underwater has varied range of significant applications such as side-scan sonar, mine hunting sonar. It also finds utility in other domains such as imaging of body tissues via ultrasonography and non-destructive testing of objects. In this paper, we explore the feasibility of using active acoustic imagery in air and simulate phased array beamforming techniques available in literature for various array designs to achieve a suitable acoustic sensor array design for a portable mobile robot which can be applied to detect the presence/absence of anomalous objects in a room. The multi-path reflection effects especially in enclosed rooms and environmental noise factors are currently not simulated and will be dealt with during the experimental phase. The related hardware is designed with the same feasibility criterion that the developed system needs to be deployed on a portable mobile robot. There is a trade of between image resolution and range with the array size, number of elements and the imaging frequency and has to be iteratively simulated to achieve the desired acoustic sensor array design. The designed acoustic imaging array system is to be mounted on a portable mobile robot and targeted for use in surveillance missions for intruder alerts and imaging objects during dark and smoky scenarios where conventional optic based systems do not function well.

Keywords: acoustic sensor array, acoustic imagery, anomaly detection, phased array beamforming

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Authors: Tayab D. Memon, Shahji Farooque, Marvi Deshi, Imtiaz Hussain Kalwar, B. S. Chowdhry

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Recently single-bit ternary FIR-like filter (SBTFF) hardware synthesize in FPGA is reported and compared with multi-bit FIR filter on similar spectral characteristics. Results shows that SBTFF dominates upon multi-bit filter overall. In this paper, an optimized adder module for ternary quantized sigma-delta modulated signal is presented. The adder is simulated using ModelSim for functional verification the area-performance of the proposed adder were obtained through synthesis in Xilinx and compared to conventional adder trees. The synthesis results show that the proposed adder tree achieves higher clock rates and lower chip area at higher inputs to the adder block; whereas conventional adder tree achieves better performance and lower chip area at lower number of inputs to the same adder block. These results enhance the usefulness of existing short word length DSP algorithms for fast and efficient mobile communication.

Keywords: short word length (SWL), DSP algorithms, FPGA, SBTFF, VHDL

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Authors: Meiling Yang, Shuguo Xie, Yilong Zhu

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Nowadays, due to diverse electric products and complex electromagnetic environment, the localization and troubleshooting of the electromagnetic radiation source is urgent and necessary especially on the condition of far field. However, based on the existing DOA positioning method, the system or devices are complex, bulky and expensive. To address this issue, this paper proposes a single antenna radiation source localization method. A single antenna moves to form a virtual antenna array combined with DOA and MUSIC algorithm to position accurately, meanwhile reducing the cost and simplify the equipment. As shown in the results of simulations and experiments, the virtual antenna array DOA estimation modeling is correct and its positioning is credible.

Keywords: virtual antenna array, DOA, localization, far field

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Authors: Ashfaque Hossain Khan, Brian Thomson, Ratan Debnath, Abhishek Motayed, Mulpuri V. Rao

Abstract:

Though the efforts had been made, the problem of cross-sensitivity for a single metal oxide-based sensor can’t be fully eliminated. In this work, a sensor array has been designed and fabricated comprising of platinum (Pt), copper (Cu), and silver (Ag) decorated TiO2 and ZnO functionalized GaN nanowires using industry-standard top-down fabrication approach. The metal/metal-oxide combinations within the array have been determined from prior molecular simulation study using first principle calculations based on density functional theory (DFT). The gas responses were obtained for both single and mixture of NO2, SO2, ethanol, and H2 in the presence of H2O and O2 gases under UV light at room temperature. Each gas leaves a unique response footprint across the array sensors by which precise discrimination of cross-sensitive gases has been achieved. An unsupervised principal component analysis (PCA) technique has been implemented on the array response. Results indicate that each gas forms a distinct cluster in the score plot for all the target gases and their mixtures, indicating a clear separation among them. In addition, the developed array device consumes very low power because of ultra-violet (UV) assisted sensing as compared to commercially available metal-oxide sensors. The nanowire sensor array, in combination with PCA, is a potential approach for precise real-time gas monitoring applications.

Keywords: cross-sensitivity, gas sensor, principle component analysis (PCA), sensor array

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