Search results for: high-k gate dielectrics
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 282

Search results for: high-k gate dielectrics

132 A New Full Adder Cell for High Performance Low Power Applications

Authors: Mahdiar Hosseighadiry, Farnaz Fotovatikhah, Razali Ismail, Mohsen Khaledian, Mehdi Saeidemanesh

Abstract:

In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles.

Keywords: full adders, low-power, high-performance, VLSI design

Procedia PDF Downloads 362
131 Design and Implementation of Testable Reversible Sequential Circuits Optimized Power

Authors: B. Manikandan, A. Vijayaprabhu

Abstract:

The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area.

Keywords: DET, QCA, reversible logic gates, POS, SOP, latches, flip flops

Procedia PDF Downloads 280
130 An Embedded High Speed Adder for Arithmetic Computations

Authors: Kala Bharathan, R. Seshasayanan

Abstract:

In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

Procedia PDF Downloads 426
129 A Study of the Carbon Footprint from a Liquid Silicone Rubber Compounding Facility in Malaysia

Authors: Q. R. Cheah, Y. F. Tan

Abstract:

In modern times, the push for a low carbon footprint entails achieving carbon neutrality as a goal for future generations. One possible step towards carbon footprint reduction is the use of more durable materials with longer lifespans, for example, silicone data cableswhich show at least double the lifespan of similar plastic products. By having greater durability and longer lifespans, silicone data cables can reduce the amount of trash produced as compared to plastics. Furthermore, silicone products don’t produce micro contamination harmful to the ocean. Every year the electronics industry produces an estimated 5 billion data cables for USB type C and lightning data cables for tablets and mobile phone devices. Material usage for outer jacketing is 6 to 12 grams per meter. Tests show that the product lifespan of a silicone data cable over plastic can be doubled due to greater durability. This can save at least 40,000 tonnes of material a year just on the outer jacketing of the data cable. The facility in this study specialises in compounding of liquid silicone rubber (LSR) material for the extrusion process in jacketing for the silicone data cable. This study analyses the carbon emissions from the facility, which is presently capable of producing more than 1,000 tonnes of LSR annually. This study uses guidelines from the World Business Council for Sustainable Development (WBCSD) and World Resources Institute (WRI) to define the boundaries of the scope. The scope of emissions is defined as 1. Emissions from operations owned or controlled by the reporting company, 2. Emissions from the generation of purchased or acquired energy such as electricity, steam, heating, or cooling consumed by the reporting company, and 3. All other indirect emissions occurring in the value chain of the reporting company, including both upstream and downstream emissions. As the study is limited to the compounding facility, the system boundaries definition according to GHG protocol is cradle-to-gate instead of cradle-to-grave exercises. Malaysia’s present electricity generation scenario was also used, where natural gas and coal constitute the bulk of emissions. Calculations show the LSR produced for the silicone data cable with high fire retardant capability has scope 1 emissions of 0.82kg CO2/kg, scope 2 emissions of 0.87kg CO2/kg, and scope 3 emissions of 2.76kg CO2/kg, with a total product carbon footprint of 4.45kg CO2/kg. This total product carbon footprint (Cradle-to-gate) is comparable to the industry and to plastic materials per tonne of material. Although per tonne emission is comparable to plastic material, due to greater durability and longer lifespan, there can be significantly reduced use of LSR material. Suggestions to reduce the calculated product carbon footprint in the scope of emissions involve 1. Incorporating the recycling of factory silicone waste into operations, 2. Using green renewable energy for external electricity sources and 3. Sourcing eco-friendly raw materials with low GHG emissions.

Keywords: carbon footprint, liquid silicone rubber, silicone data cable, Malaysia facility

Procedia PDF Downloads 75
128 Saturation Misbehavior and Field Activation of the Mobility in Polymer-Based OTFTs

Authors: L. Giraudet, O. Simonetti, G. de Tournadre, N. Dumelié, B. Clarenc, F. Reisdorffer

Abstract:

In this paper we intend to give a comprehensive view of the saturation misbehavior of thin film transistors (TFTs) based on disordered semiconductors, such as most organic TFTs, and its link to the field activation of the mobility. Experimental evidence of the field activation of the mobility is given for disordered semiconductor based TFTs, when reducing the gate length. Saturation misbehavior is observed simultaneously. Advanced transport models have been implemented in a quasi-2D numerical TFT simulation software. From the numerical simulations it is clearly established that field activation of the mobility alone cannot explain the saturation misbehavior. Evidence is given that high longitudinal field gradient at the drain end of the channel is responsible for an excess charge accumulation, preventing saturation. The two combined effects allow reproducing the experimental output characteristics of short channel TFTs, with S-shaped characteristics and saturation failure.

Keywords: mobility field activation, numerical simulation, OTFT, saturation failure

Procedia PDF Downloads 495
127 A Smart Visitors’ Notification System with Automatic Secure Door Lock Using Mobile Communication Technology

Authors: Rabail Shafique Satti, Sidra Ejaz, Madiha Arshad, Marwa Khalid, Sadia Majeed

Abstract:

The paper presents the development of an automated security system to automate the entry of visitors, providing more flexibility of managing their record and securing homes or workplaces. Face recognition is part of this system to authenticate the visitors. A cost effective and SMS based door security module has been developed and integrated with the GSM network and made part of this system to allow communication between system and owner. This system functions in real time as when the visitor’s arrived it will detect and recognizes his face and on the result of face recognition process it will open the door for authorized visitors or notifies and allows the owner’s to take further action in case of unauthorized visitor. The proposed system is developed and it is successfully ensuring security, managing records and operating gate without physical interaction of owner.

Keywords: SMS, e-mail, GSM modem, authenticate, face recognition, authorized

Procedia PDF Downloads 760
126 Low-Cost Reversible Logic Serial Multipliers with Error Detection Capability

Authors: Mojtaba Valinataj

Abstract:

Nowadays reversible logic has received many attentions as one of the new fields for reducing the power consumption. On the other hand, the processing systems have weaknesses against different external effects. In this paper, some error detecting reversible logic serial multipliers are proposed by incorporating the parity-preserving gates. This way, the new designs are presented for signed parity-preserving serial multipliers based on the Booth's algorithm by exploiting the new arrangements of existing gates. The experimental results show that the proposed 4×4 multipliers in this paper reach up to 20%, 35%, and 41% enhancements in the number of constant inputs, quantum cost, and gate count, respectively, as the reversible logic criteria, compared to previous designs. Furthermore, all the proposed designs have been generalized for n×n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size.

Keywords: Booth’s algorithm, error detection, multiplication, parity-preserving gates, quantum computers, reversible logic

Procedia PDF Downloads 199
125 Environmental Potentials within the Production of Asphalt Mixtures

Authors: Florian Gschösser, Walter Purrer

Abstract:

The paper shows examples for the (environmental) optimization of production processes for asphalt mixtures applied for typical road pavements in Austria and Switzerland. The conducted “from-cradle-to-gate” LCA firstly analyzes the production one cubic meter of asphalt and secondly all material production processes for exemplary highway pavements applied in Austria and Switzerland. It is shown that environmental impacts can be reduced by the application of reclaimed asphalt pavement (RAP) and by the optimization of specific production characteristics, e.g. the reduction of the initial moisture of the mineral aggregate and the reduction of the mixing temperature by the application of low-viscosity and foam bitumen. The results of the LCA study demonstrate reduction potentials per cubic meter asphalt of up to 57 % (Global Warming Potential–GWP) and 77 % (Ozone depletion–ODP). The analysis per square meter of asphalt pavement determined environmental potentials of up to 40 % (GWP) and 56 % (ODP).

Keywords: asphalt mixtures, environmental potentials, life cycle assessment, material production

Procedia PDF Downloads 510
124 Etude 3D Quantum Numerical Simulation of Performance in the HEMT

Authors: A. Boursali, A. Guen-Bouazza

Abstract:

We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/m, a peak extrinsic transconductance of 0.59S/m at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, leakage current density IFuite=1 x 10-26 A, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, silvaco, field plate, genetic algorithm, quantum

Procedia PDF Downloads 328
123 3D Quantum Simulation of a HEMT Device Performance

Authors: Z. Kourdi, B. Bouazza, M. Khaouani, A. Guen-Bouazza, Z. Djennati, A. Boursali

Abstract:

We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/mm, a peak extrinsic transconductance of 590 mS/mm at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, Silvaco, field plate, genetic algorithm, quantum

Procedia PDF Downloads 444
122 The Journey of a Malicious HTTP Request

Authors: M. Mansouri, P. Jaklitsch, E. Teiniker

Abstract:

SQL injection on web applications is a very popular kind of attack. There are mechanisms such as intrusion detection systems in order to detect this attack. These strategies often rely on techniques implemented at high layers of the application but do not consider the low level of system calls. The problem of only considering the high level perspective is that an attacker can circumvent the detection tools using certain techniques such as URL encoding. One technique currently used for detecting low-level attacks on privileged processes is the tracing of system calls. System calls act as a single gate to the Operating System (OS) kernel; they allow catching the critical data at an appropriate level of detail. Our basic assumption is that any type of application, be it a system service, utility program or Web application, “speaks” the language of system calls when having a conversation with the OS kernel. At this level we can see the actual attack while it is happening. We conduct an experiment in order to demonstrate the suitability of system call analysis for detecting SQL injection. We are able to detect the attack. Therefore we conclude that system calls are not only powerful in detecting low-level attacks but that they also enable us to detect high-level attacks such as SQL injection.

Keywords: Linux system calls, web attack detection, interception, SQL

Procedia PDF Downloads 328
121 Performance Evaluation of Different Technologies of PV Modules in Algeria

Authors: Amira Balaska, Ali Tahri, Amine Boudghene Stambouli, Takashi Oozeki

Abstract:

This paper is dealing with the evaluation of photovoltaic modules as part of the Sahara Solar Breeder project (SSB), five different photovoltaic module technologies which are: m-si, CIS, HIT, Back Contact, a-si_μc -si and a weather station recently installed at the University of Saida (Tahar Moulay) in Saida city located at the gate of the great southern Algeria’s Sahara. The objective of the present work is the study of solar photovoltaic capacity and performance parameters of each PV module technology. The goal of the study is to compare the five different PV technologies in order to find which technologies are suitable for the climate conditions of Algeria’s desert. Measurements of various parameters as irradiance, temperature, humidity and so on by the weather station and I-V curves were performed outdoors at the location without shadow. Finally performance parameters as performance ratio, energy yield and temperature losses are given and analyzed.

Keywords: photovoltaic modules, performance ratio, energy yield, sahara solar breeder, outdoor conditions

Procedia PDF Downloads 639
120 FPGA Implementation of Novel Triangular Systolic Array Based Architecture for Determining the Eigenvalues of Matrix

Authors: Soumitr Sanjay Dubey, Shubhajit Roy Chowdhury, Rahul Shrestha

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In this paper, we have presented a novel approach of calculating eigenvalues of any matrix for the first time on Field Programmable Gate Array (FPGA) using Triangular Systolic Arra (TSA) architecture. Conventionally, additional computation unit is required in the architecture which is compliant to the algorithm for determining the eigenvalues and this in return enhances the delay and power consumption. However, recently reported works are only dedicated for symmetric matrices or some specific case of matrix. This works presents an architecture to calculate eigenvalues of any matrix based on QR algorithm which is fully implementable on FPGA. For the implementation of QR algorithm we have used TSA architecture, which is further utilising CORDIC (CO-ordinate Rotation DIgital Computer) algorithm, to calculate various trigonometric and arithmetic functions involved in the procedure. The proposed architecture gives an error in the range of 10−4. Power consumption by the design is 0.598W. It can work at the frequency of 900 MHz.

Keywords: coordinate rotation digital computer, three angle complex rotation, triangular systolic array, QR algorithm

Procedia PDF Downloads 386
119 Voltage and Current Control of Microgrid in Grid Connected and Islanded Modes

Authors: Megha Chavda, Parth Thummar, Rahul Ghetia

Abstract:

This paper presents the voltage and current control of microgrid accompanied by the synchronization of microgrid with the main utility grid in both islanded and grid-connected modes. Distributed Energy Resources (DERs) satisfy the wide-spread power demand of consumer by behaving as a micro source for a low voltage (LV) grid or microgrid. Synchronization of the microgrid with the main utility grid is done using PLL and PWM gate pulse generation technique is used for the Voltage Source Converter. Potential Function method achieves the voltage and current control of this microgrid in both islanded and grid-connected modes. A low voltage grid consisting of three distributed generators (DG) is considered for the study and is simulated in time-domain using PSCAD/EMTDC software. The simulation results depict the appropriateness of voltage and current control of microgrid and synchronization of microgrid with the medium voltage (MV) grid.

Keywords: microgrid, distributed energy resources, voltage and current control, voltage source converter, pulse width modulation, phase locked loop

Procedia PDF Downloads 391
118 Energy Dynamics of Solar Thermionic Power Conversion with Emitter of Graphene

Authors: Olukunle C. Olawole, Dilip K. De, Moses Emetere, Omoje Maxwell

Abstract:

Graphene can stand very high temperature up to 4500 K in vacuum and has potential for application in thermionic energy converter. In this paper, we discuss the application of energy dynamics principles and the modified Richardson-Dushman Equation, to estimate the efficiency of solar power conversion to electrical power by a solar thermionic energy converter (STEC) containing emitter made of graphene. We present detailed simulation of power output for different solar insolation, diameter of parabolic concentrator, area of the graphene emitter (same as that of the collector), temperature of the collector, physical dimensions of the emitter-collector etc. After discussing possible methods of reduction or elimination of space charge problem using magnetic field and gate, we finally discuss relative advantages of using emitters made of graphene, carbon nanotube and metals respectively in a STEC.

Keywords: graphene, high temperature, modified Richardson-Dushman equation, solar thermionic energy converter

Procedia PDF Downloads 281
117 Performance Analysis of Arithmetic Units for IoT Applications

Authors: Nithiya C., Komathi B. J., Praveena N. G., Samuda Prathima

Abstract:

At present, the ultimate aim in digital system designs, especially at the gate level and lower levels of design abstraction, is power optimization. Adders are a nearly universal component of today's integrated circuits. Most of the research was on the design of high-speed adders to execute addition based on various adder structures. This paper discusses the ideal path for selecting an arithmetic unit for IoT applications. Based on the analysis of eight types of 16-bit adders, we found out Carry Look-ahead (CLA) produces low power. Additionally, multiplier and accumulator (MAC) unit is implemented with the Booth multiplier by using the low power adders in the order of preference. The design is synthesized and verified using Synopsys Design Compiler and VCS. Then it is implemented by using Cadence Encounter. The total power consumed by the CLA based booth multiplier is 0.03527mW, the total area occupied is 11260 um², and the speed is 2034 ps.

Keywords: carry look-ahead, carry select adder, CSA, internet of things, ripple carry adder, design rule check, power delay product, multiplier and accumulator

Procedia PDF Downloads 99
116 Economic Loss due to Ganoderma Disease in Oil Palm

Authors: K. Assis, K. P. Chong, A. S. Idris, C. M. Ho

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Oil palm or Elaeis guineensis is considered as the golden crop in Malaysia. But oil palm industry in this country is now facing with the most devastating disease called as Ganoderma Basal Stem Rot disease. The objective of this paper is to analyze the economic loss due to this disease. There were three commercial oil palm sites selected for collecting the required data for economic analysis. Yield parameter used to measure the loss was the total weight of fresh fruit bunch in six months. The predictors include disease severity, change in disease severity, number of infected neighbor palms, age of palm, planting generation, topography, and first order interaction variables. The estimation model of yield loss was identified by using backward elimination based regression method. Diagnostic checking was conducted on the residual of the best yield loss model. The value of mean absolute percentage error (MAPE) was used to measure the forecast performance of the model. The best yield loss model was then used to estimate the economic loss by using the current monthly price of fresh fruit bunch at mill gate.

Keywords: ganoderma, oil palm, regression model, yield loss, economic loss

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115 3 Phase Induction Motor Control Using Single Phase Input and GSM

Authors: Pooja S. Billade, Sanjay S. Chopade

Abstract:

This paper focuses on the design of three phase induction motor control using single phase input and GSM.The controller used in this work is a wireless speed control using a GSM technique that proves to be very efficient and reliable in applications.The most common principle is the constant V/Hz principle which requires that the magnitude and frequency of the voltage applied to the stator of a motor maintain a constant ratio. By doing this, the magnitude of the magnetic field in the stator is kept at an approximately constant level throughout the operating range. Thus, maximum constant torque producing capability is maintained. The energy that a switching power converter delivers to a motor is controlled by Pulse Width Modulated signals applied to the gates of the power transistors in H-bridge configuration. PWM signals are pulse trains with fixed frequency and magnitude and variable pulse width. When a PWM signal is applied to the gate of a power transistor, it causes the turn on and turns off intervals of the transistor to change from one PWM period.

Keywords: index terms— PIC, GSM (global system for mobile), LCD (Liquid Crystal Display), IM (Induction Motor)

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114 Investigation of Maritime Accidents with Exploratory Data Analysis in the Strait of Çanakkale (Dardanelles)

Authors: Gizem Kodak

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The Strait of Çanakkale, together with the Strait of Istanbul and the Sea of Marmara, form the Turkish Straits System. In other words, the Strait of Çanakkale is the southern gate of the system that connects the Black Sea countries with the other countries of the world. Due to the heavy maritime traffic, it is important to scientifically examine the accident characteristics in the region. In particular, the results indicated by the descriptive statistics are of critical importance in order to strengthen the safety of navigation. At this point, exploratory data analysis offers strategic outputs in terms of defining the problem and knowing the strengths and weaknesses against possible accident risk. The study aims to determine the accident characteristics in the Strait of Çanakkale with temporal and spatial analysis of historical data, using Exploratory Data Analysis (EDA) as the research method. The study's results will reveal the general characteristics of maritime accidents in the region and form the infrastructure for future studies. Therefore, the text provides a clear description of the research goals and methodology, and the study's contributions are well-defined.

Keywords: maritime accidents, EDA, Strait of Çanakkale, navigational safety

Procedia PDF Downloads 64
113 Approximate-Based Estimation of Single Event Upset Effect on Statistic Random-Access Memory-Based Field-Programmable Gate Arrays

Authors: Mahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Henk Corporaal

Abstract:

Recently, Statistic Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in aeronautics and space systems where high dependability is demanded and considered as a mandatory requirement. Since design’s circuit is stored in configuration memory in SRAM-based FPGAs; they are very sensitive to Single Event Upsets (SEUs). In addition, the adverse effects of SEUs on the electronics used in space are much higher than in the Earth. Thus, developing fault tolerant techniques play crucial roles for the use of SRAM-based FPGAs in space. However, fault tolerance techniques introduce additional penalties in system parameters, e.g., area, power, performance and design time. In this paper, an accurate estimation of configuration memory vulnerability to SEUs is proposed for approximate-tolerant applications. This vulnerability estimation is highly required for compromising between the overhead introduced by fault tolerance techniques and system robustness. In this paper, we study applications in which the exact final output value is not necessarily always a concern meaning that some of the SEU-induced changes in output values are negligible. We therefore define and propose Approximate-based Configuration Memory Vulnerability Factor (ACMVF) estimation to avoid overestimating configuration memory vulnerability to SEUs. In this paper, we assess the vulnerability of configuration memory by injecting SEUs in configuration memory bits and comparing the output values of a given circuit in presence of SEUs with expected correct output. In spite of conventional vulnerability factor calculation methods, which accounts any deviations from the expected value as failures, in our proposed method a threshold margin is considered depending on user-case applications. Given the proposed threshold margin in our model, a failure occurs only when the difference between the erroneous output value and the expected output value is more than this margin. The ACMVF is subsequently calculated by acquiring the ratio of failures with respect to the total number of SEU injections. In our paper, a test-bench for emulating SEUs and calculating ACMVF is implemented on Zynq-7000 FPGA platform. This system makes use of the Single Event Mitigation (SEM) IP core to inject SEUs into configuration memory bits of the target design implemented in Zynq-7000 FPGA. Experimental results for 32-bit adder show that, when 1% to 10% deviation from correct output is considered, the counted failures number is reduced 41% to 59% compared with the failures number counted by conventional vulnerability factor calculation. It means that estimation accuracy of the configuration memory vulnerability to SEUs is improved up to 58% in the case that 10% deviation is acceptable in output results. Note that less than 10% deviation in addition result is reasonably tolerable for many applications in approximate computing domain such as Convolutional Neural Network (CNN).

Keywords: fault tolerance, FPGA, single event upset, approximate computing

Procedia PDF Downloads 163
112 Synthesis and Characterization of Ferromagnetic Ni-Cu Alloys for Thermal Rectification Applications

Authors: Josue Javier Martinez Flores, Jaime Alvarez Quintana

Abstract:

A thermal rectifier consists of a device which can load a different heat flow which depends on the direction of that flow. That device is a thermal diode. It is well known that heat transfer in solids basically depends on the electrical, magnetic and crystalline nature of materials via electrons, magnons and phonons as thermal energy carriers respectively. In the present research, we have synthesized polycrystalline Ni-Cu alloys and identified the Curie temperatures; and we have observed that by way of secondary phase transitions, it is possible manipulate the heat conduction in solid state thermal diodes via transition temperature. In this sense, we have succeeded in developing solid state thermal diodes with a control gate through the Curie temperature via the activation and deactivation of magnons in Ni-Cu ferromagnetic alloys at room temperature. Results show thermal diodes with thermal rectification factors up to 1.5. Besides, the performance of the electrical rectifiers can be controlled by way of alloy Cu content; hence, lower Cu content alloys present enhanced thermal rectifications factors than higher ones.

Keywords: thermal rectification, Curie temperature, ferromagnetic alloys, magnons

Procedia PDF Downloads 221
111 Optimization of Plastic Injection Molding Parameters by Altering Gate and Runner of Feeding System

Authors: Ali Ramezani

Abstract:

Balancing feeding system of plastic injection molding has overriding importance as it minimizes the process’s product defects such as weld line, shrinkage, sink marks and warpage. This article presents the difference between optimization of feeding system in identical multi-cavity molding and family molding using Moldflow Plastic Insight software. In this work, the effect of dimension, shape, position and type of gates and runners on the products quality was studied. The optimization was carried out by analyzing plastic injection molding process parameters, including melt temperature, mold temperature, cooling time, cooling temperature packing time and packing pressure. It was found that symmetrical feeding system is the most efficient shape for diminishing defects in identical multi-cavity molding. However, the same results were not concluded for family molding due to the differences between volume, mass, thickness and shape of cavities.

Keywords: balancing feeding system, family molding, multi-cavity, Moldflow, plastic injection

Procedia PDF Downloads 108
110 Analytical Terahertz Characterization of In0.53Ga0.47As Transistors and Homogenous Diodes

Authors: Abdelmadjid Mammeri, Fatima Zohra Mahi, Luca Varani, H. Marinchoi

Abstract:

We propose an analytical model for the admittance and the noise calculations of the InGaAs transistor and diode. The development of the small-signal admittance takes into account the longitudinal and transverse electric fields through a pseudo two-dimensional approximation of the Poisson equation. The frequency-dependent of the small-signal admittance response is determined by the total currents and the potentials matrix relation between the gate and the drain terminals. The noise is evaluated by using the real part of the transistor/diode admittance under a small-signal perturbation. The analytical results show that the admittance spectrum exhibits a series of resonant peaks corresponding to the excitation of plasma waves. The appearance of the resonance is discussed and analyzed as functions of the channel length and the temperature. The model can be used, on one hand; to control the appearance of the plasma resonances, and on other hand; can give significant information about the noise frequency dependence in the InGaAs transistor and diode.

Keywords: InGaAs transistors, InGaAs diode, admittance, resonant peaks, plasma waves, analytical model

Procedia PDF Downloads 284
109 Equivalent Electrical Model of a Shielded Pulse Planar Transformer in Isolated Gate Drivers for SiC MOSFETs

Authors: Loreine Makki, Marc Anthony Mannah, Christophe Batard, Nicolas Ginot, Julien Weckbrodt

Abstract:

Planar transformers are extensively utilized in high-frequency, high power density power electronic converters. The breakthrough of wide-bandgap technology compelled power electronic system miniaturization while inducing pivotal effects on system modeling and manufacturing within the power electronics industry. A significant consideration to simulate and model the unanticipated parasitic parameters emerges with the requirement to mitigate electromagnetic disturbances. This paper will present an equivalent circuit model of a shielded pulse planar transformer quantifying leakage inductance and resistance in addition to the interwinding capacitance of the primary and secondary windings. ANSYS Q3D Extractor was utilized to model and simulate the transformer, intending to study the immunity of the simulated equivalent model to high dv/dt occurrences. A convenient correlation between simulation and experimental results is presented.

Keywords: Planar transformers, wide-band gap, equivalent circuit model, shielded, ANSYS Q3D Extractor, dv/dt

Procedia PDF Downloads 184
108 Design and Field Programmable Gate Array Implementation of Radio Frequency Identification for Boosting up Tag Data Processing

Authors: G. Rajeshwari, V. D. M. Jabez Daniel

Abstract:

Radio Frequency Identification systems are used for automated identification in various applications such as automobiles, health care and security. It is also called as the automated data collection technology. RFID readers are placed in any area to scan large number of tags to cover a wide distance. The placement of the RFID elements may result in several types of collisions. A major challenge in RFID system is collision avoidance. In the previous works the collision was avoided by using algorithms such as ALOHA and tree algorithm. This work proposes collision reduction and increased throughput through reading enhancement method with tree algorithm. The reading enhancement is done by improving interrogation procedure and increasing the data handling capacity of RFID reader with parallel processing. The work is simulated using Xilinx ISE 14.5 verilog language. By implementing this in the RFID system, we can able to achieve high throughput and avoid collision in the reader at a same instant of time. The overall system efficiency will be increased by implementing this.

Keywords: antenna, anti-collision protocols, data management system, reader, reading enhancement, tag

Procedia PDF Downloads 270
107 Prevalence of Depression among Post Stroke Survivors in South Asian Region: A Systematic Review and Meta-Analysis

Authors: Roseminu Varghese, Laveena Anitha Barboza, Jyothi Chakrabarty, Ravishankar

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Depression among post-stroke survivors is prevalent, but it is unidentified. The purpose of this review was to determine the pooled prevalence of depression among post-stroke survivors in the South Asian region from all published health sciences research articles. The review also aimed to analyze the disparities in the prevalence of depression among the post-stroke survivors from different study locations. Data search to identify the relevant research articles published from 2005 to 2016 was done by using mesh terms and keywords in Web of Science, PubMed Medline, CINAHL, Scopus, J gate, IndMED databases. The final analysis comprised of 9 studies, including a population of 1,520 men and women. Meta-analysis was performed in STATA version 13.0. The overall pooled post-stroke depression prevalence was 0.46, 95% (CI), (0.3- 0.62). The prevalence rate in this systematic review is evident of depression among post-stroke survivors in the South Asian Region. Identifying the prevalence of post-stroke depression at an early stage is important to improve outcomes of the rehabilitative process of stroke survivors and for its early intervention.

Keywords: depression, post stroke survivors, prevalence, systematic review

Procedia PDF Downloads 134
106 Small Fixed-Wing UAV Physical Based Modeling, Simulation, and Validation

Authors: Ebrahim H. Kapeel, Ehab Safwat, Hossam Hendy, Ahmed M. Kamel, Yehia Z. Elhalwagy

Abstract:

Motivated by the problem of the availability of high-fidelity flight simulation models for small unmanned aerial vehicles (UAVs). This paper focuses on the geometric-mass inertia modeling and the actuation system modeling for the small fixed-wing UAVs. The UAV geometric parameters for the body, wing, horizontal and vertical tail are physically measured. Pendulum experiment with high-grade sensors and data analysis using MATLAB is used to estimate the airplane moment of inertia (MOI) model. Finally, UAV’s actuation system is modeled by estimating each servo transfer function by using the system identification, which uses experimental measurement for input and output angles through using field-programmable gate array (FPGA). Experimental results for the designed models are given to illustrate the effectiveness of the methodology. It also gives a very promising result to finalize the open-loop flight simulation model through modeling the propulsion system and the aerodynamic system.

Keywords: unmanned aerial vehicle, geometric-mass inertia model, system identification, Simulink

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105 Effect of Oxidative Stress from Smoking on Erythrocyte Phosphatidylserine Externalization

Authors: Ratchaneewan Maneemaroj, Paveena Noisuwan, Chonlada Lakhonphon

Abstract:

The smoking is one of the major risk factors in Non-Communicable Disease. Free radicals from cigarette smoke can cause oxidative stress. The oxidative insults can lead to red blood cell (RBC) senescence and are involved in the clearance of red blood cells. The objective of the present study is to assess the association between smoke, oxidative stress evaluated with serum Malondialdehyde (MDA) level and phosphatidylserine (PS) externalization (biomarker of RBC senescence) evaluated with annexin V binding. A total of sixty-four male volunteers aged 25-60 years old were recruited in this study. MDA was measured by colorimetric method. Annexin V binding was detected by flow cytometry. Our results show that there was a significant increase in MDA levels in cigarette smokers as compared to non-smokers (p < 0.001). However, there was no significant different between annexin V binding (% gate) in cigarette smokers and non-smokers (p = 0.978). These results provide evidence of free radical from smoking is associated with oxidative damage to erythrocytes. However, our results suggest that PS externalization is unlikely to have a role in RBC senescence pathway of stressed erythrocytes from cigarette smoke. The other biomarker of RBC senescence should be determined on cigarette smoker erythrocytes.

Keywords: malondialdehyde, phosphatidylserine, RBC senescence, annexin V

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104 Digital Encoder Based Power Frequency Deviation Measurement

Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: frequency measurement, digital control, phase locked loop, encoder, Verilog HDL

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103 Integration of a Load Switch with DC/DC Buck Converter for Power Distribution in Low Cost Educational Nanosatellite

Authors: Bentoutou Houari, Boutte Aissa, Belaidi El Yazid, Limam Lakhdar

Abstract:

The integration of a load switch with a DC/DC buck converter using LM2596 for power distribution in low-cost educational nanosatellites is a technique that aims to efficiently manage the power distribution system in these small spacecraft. The converter is based on the LM2596 regulator and designed to step down the input voltage of +16.8V to +12V, +5V, and +3.3V output, which are suitable for the nanosatellite's various subsystems. The load switch is based on MOSFET and is used to turn on or off the power supply to a particular load and protect the nanosatellite from power surges. A prototype of a +12V DC/DC buck converter with a high side load switch has been realized and tested, which meets our requirements and shows a good efficiency of 89%. In addition, the prototype features a capacitor between the source and gate of the MOSFET, which has effectively reduced the inrush current, demonstrating the effectiveness of this approach in reducing surges of current when the load is connected. The output current and voltage were measured at 0.7A and 11.89V, respectively, making this design suitable for use in low-cost educational nanosatellites.

Keywords: DC/DC buck converter, load switch, LM2596, electrical power subsystems, nanosatellite, inrush current

Procedia PDF Downloads 74