Search results for: reconfigurable FPGA

Authors: S. S. Kenny Lee, C. C. Kong, S. K. Ting

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Teaching engineering lab provides opportunity for students to practice theories learned through physical experiment in the laboratory. However, building laboratories to accommodate increased number of students are expensive, making it impossible for an educational institution to afford the high expenses. In this paper, we develop a low cost and remote platform to aid teaching undergraduate students. The platform is constructed where the real experiment setting up in laboratory can be reconfigure and accessed remotely, the aim is to increase student’s desire to learn at which they can interact with the physical experiment using network enabled devices at anywhere in the campus. The platform is constructed with Raspberry Pi as a main control board that provides communication between computer interfaces to the actual experiment preset in the laboratory. The interface allows real-time remote viewing and triggering the physical experiment in the laboratory and also provides instructions and learning guide about the experimental.

Keywords: engineering lab, low cost, network, remote platform, reconfigure, real-time

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Authors: Hanan Mikhael Dawood, Haider Salim, Jafar Al-Wash

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This paper presents Proportional-Integral (PI) controller to improve the system performance which gives better torque and flux response. In addition, it reduces the undesirable torque ripple. The conventional DTC controller approach for induction machines, based on an improved torque and stator flux estimator, is implemented using Xilinx System Generator (XSG) for MATLAB/Simulink environment through Xilinx blocksets. The design was achieved in VHDL which is based on a MATLAB/Simulink simulation model. The hardware in the loop results are obtained considering the implementation of the proposed model on the Xilinx NEXYS2 Spartan 3E1200 FG320 Kit.

Keywords: induction motor, Direct Torque Control (DTC), Xilinx FPGA, motor drive

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Authors: G. R. Kavitha, T. S. Indumathi

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With the constantly rising demands of the multimedia services, the requirements of long haul transport network are constantly changing in the area of optical network. Maximum data transmission using optimization of the communication channel poses the biggest challenge. Although there has been a constant focus on this area from the past decade, there was no evidence of a significant result that has been accomplished. Hence, after reviewing some potential design of optical network from literatures, it was understood that optical signal to noise ratio was one of the elementary attributes that can define the performance of the optical network. In this paper, we propose a framework termed as ECON (Enhanced Constraint-based Optical Network) that primarily optimize the optical signal to noise ratio using ROADM. The simulation is performed in Matlab and optical signal to noise ratio is extracted considering the system matrix. The outcome of the proposed study shows that optimized OSNR as compared to the existing studies.

Keywords: component, optical network, reconfigurable optical add-drop multiplexer, optical signal-to-noise ratio

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Authors: Mohamad Baqer Heidari, Hefzollah.Mohammadian

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This brief presents two original implementations of improved accuracy current-mode multiplier/divider circuits. Besides the advantage of their simplicity, these original multiplier/divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.75% and 0.9%, respectively, for an extended range of the input currents). The original multiplier/divider circuits permit a facile reconfiguration, the presented structures representing the functional basis for implementing complex function synthesizer circuits. The proposed computational structures are designed for implementing in 0.18-µm CMOS technology, with a low-voltage operation (a supply voltage of 1.2 V). The circuits’ power consumptions are 60 and 75 µW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

Keywords: analog signal processing, current-mode operation, functional core, multiplier, reconfigurable circuits, industrial package systems

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Authors: Farnaz Fotovvatikhah, Javad Akbari

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Test time of a test architecture is an important factor which depends on the architecture's delay and test patterns. Here a new architecture to store the test results based on network on chip is presented. In addition, simple analytical model is proposed to calculate link test time for built in self-tester (BIST) and external tester (Ext) in multiprocessor systems. The results extracted from the model are verified using FPGA implementation and experimental measurements. Systems consisting 16, 25, and 36 processors are implemented and simulated and test time is calculated. In addition, BIST and Ext are compared in terms of test time at different conditions such as at different number of test patterns and nodes. Using the model the maximum frequency of testing could be calculated and the test structure could be optimized for high speed testing.

Keywords: test, nano on-chip network, JTAG, modelling

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Authors: Tomasz Grzes, Maciej Kopczynski, Jaroslaw Stepaniuk

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The rough sets theory developed by Prof. Z. Pawlak is one of the tools that can be used in the intelligent systems for data analysis and processing. Banking, medicine, image recognition and security are among the possible fields of utilization. In all these fields, the amount of the collected data is increasing quickly, but with the increase of the data, the computation speed becomes the critical factor. Data reduction is one of the solutions to this problem. Removing the redundancy in the rough sets can be achieved with the reduct. A lot of algorithms of generating the reduct were developed, but most of them are only software implementations, therefore have many limitations. Microprocessor uses the fixed word length, consumes a lot of time for either fetching as well as processing of the instruction and data; consequently, the software based implementations are relatively slow. Hardware systems don’t have these limitations and can process the data faster than a software. Reduct is the subset of the decision attributes that provides the discernibility of the objects. For the given decision table there can be more than one reduct. Core is the set of all indispensable condition attributes. None of its elements can be removed without affecting the classification power of all condition attributes. Moreover, every reduct consists of all the attributes from the core. In this paper, the hardware implementation of the two-stage greedy algorithm to find the one reduct is presented. The decision table is used as an input. Output of the algorithm is the superreduct which is the reduct with some additional removable attributes. First stage of the algorithm is calculating the core using the discernibility matrix. Second stage is generating the superreduct by enriching the core with the most common attributes, i.e., attributes that are more frequent in the decision table. Described above algorithm has two disadvantages: i) generating the superreduct instead of reduct, ii) additional first stage may be unnecessary if the core is empty. But for the systems focused on the fast computation of the reduct the first disadvantage is not the key problem. The core calculation can be achieved with a combinational logic block, and thus add respectively little time to the whole process. Algorithm presented in this paper was implemented in Field Programmable Gate Array (FPGA) as a digital device consisting of blocks that process the data in a single step. Calculating the core is done by the comparators connected to the block called 'singleton detector', which detects if the input word contains only single 'one'. Calculating the number of occurrences of the attribute is performed in the combinational block made up of the cascade of the adders. The superreduct generation process is iterative and thus needs the sequential circuit for controlling the calculations. For the research purpose, the algorithm was also implemented in C language and run on a PC. The times of execution of the reduct calculation in a hardware and software were considered. Results show increase in the speed of data processing.

Keywords: data reduction, digital systems design, field programmable gate array (FPGA), reduct, rough set

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Authors: Boudjedra Abderrahim, Toumi Salah, Boutalbi Mostefa, Frihi Mohammed

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Nowadays, using the advancement of technology in semiconductor device fabrication, many transistors can be integrated to a single chip (VLSI). Although the growth chip density potentially eases systems-on-chip (SoCs) integrating thousands of processing element (PE) such as memory, processor, interfaces cores, system complexity, high-performance interconnect and scalable on-chip communication architecture become most challenges for many digital and embedded system designers. Networks-on-chip (NoCs) becomes a new paradigm that makes possible integrating heterogeneous devices and allows many communication constraints and performances. In this paper, we are interested for good performance and low area for implementation and a behavioral modeling of network on chip mesh topology design using VHDL hardware description language with performance evaluation and FPGA implementation results.

Keywords: design, implementation, communication system, network on chip, VHDL

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Authors: Belkacem Benadda, Adil Benabdellah, Boutheyna Souna

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The Internet of Things (IoT) is an unprecedented creation. Electronics objects are now able to interact, share, respond and adapt to their environment on a much larger basis. Actual spread of these modern means of connectivity and solutions with high data volume exchange are affecting our ways of life. Accommodation is becoming an intelligent living space, not only suited to the people circumstances and desires, but also to systems constraints to make daily life simpler, cheaper, increase possibilities and achieve a higher level of services and luxury. In this paper we are as Internet access, teleworking, consumption monitoring, information search, etc.). This paper addresses the design and integration of a smart home, it also purposes an IoT solution that allows smart power consumption based on measurements from power-grid and deep learning analysis.

Keywords: array sensors, IoT, power grid, FPGA, embedded

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Authors: L. Hassaine, A. Mraoui, M. R. Bengourina

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In photovoltaic system, connected to the grid, the main goal is to control the power that the inverter injects into the grid from the energy provided by the photovoltaic generator. This paper proposes a control technique for a photovoltaic system connected to the grid based on the digital pulse-width modulation (DSPWM) which can synchronise a sinusoidal current output with a grid voltage and generate power at unity power factor. This control is based on H-Bridge inverter controlled by bipolar PWM Switching. The electrical scheme of the system is presented. Simulations results of output voltage and current validate the impact of this method to determinate the appropriate control of the system. A digital design of a generator PWM using VHDL is proposed and implemented on a Xilinx FPGA.

Keywords: grid connected photovoltaic system, H-Bridge inverter, control, bipolar PWM

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Authors: Jorge Sandoval Lezama, Arturo Ivan Sandoval Rodriguez, Jose Arturo Correa Arredondo

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This work aims to share innovative educational experiences at IPN Mexico, that involve collaborative learning at institutional and global level through course competition and global collaboration projects. Students from universities in China, USA, South Korea, Canada and Mexico collaborate to design electric vehicles to solve global urban mobility problems. The participation of IPN students in the 2015-2016 global competition (São Paolo, Brazil and Cincinnati, USA) Reconfigurable Shared-Use Mobility Systems allowed to apply pedagogical strategies of groups of collaboration and of learning based on projects where they shared activities, commitments and goals, demonstrating that students were motivated to develop / self-generate their knowledge with greater meaning and understanding. One of the most evident achievements is that the students are self-managed, so the most advanced students train the students who join the project with CAD, CAE, CAM tools. Likewise, the motivation achieved is evident since in 2014 there were 12 students involved in the project, and there are currently more than 70 students.

Keywords: collaboration projects, global competency, course competition, active learning

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Authors: M. F. Haroun, T. A. Gulliver

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In this paper, an encryption algorithm is proposed for real-time image encryption. The scheme employs a dual chaotic generator based on a three dimensional (3D) discrete Lorenz attractor. Encryption is achieved using non-autonomous modulation where the data is injected into the dynamics of the master chaotic generator. The second generator is used to permute the dynamics of the master generator using the same approach. Since the data stream can be regarded as a random source, the resulting permutations of the generator dynamics greatly increase the security of the transmitted signal. In addition, a technique is proposed to mitigate the error propagation due to the finite precision arithmetic of digital hardware. In particular, truncation and rounding errors are eliminated by employing an integer representation of the data which can easily be implemented. The simple hardware architecture of the algorithm makes it suitable for secure real-time applications.

Keywords: chaotic systems, image encryption, non-autonomous modulation, FPGA

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Authors: Yusri Yusof, Kamran Latif

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Computer Numeric Control (CNC) machine has been widely used in the industries since its inception. Currently, in CNC technology has been used for various operations like milling, drilling, packing and welding etc. with the rapid growth in the manufacturing world the demand of flexibility in the CNC machines has rapidly increased. Previously, the commercial CNC failed to provide flexibility because its structure was of closed nature that does not provide access to the inner features of CNC. Also CNC’s operating ISO data interface model was found to be limited. Therefore, to overcome that problem, Open Architecture Control (OAC) technology and STEP-NC data interface model are introduced. At present the Personal Computer (PC) has been the best platform for the development of open-CNC systems. In this paper, both ISO data interface model interpretation, its verification and execution has been highlighted with the introduction of the new techniques. The proposed is composed of ISO data interpretation, 3D simulation and machine motion control modules. The system is tested on an old 3 axis CNC milling machine. The results are found to be satisfactory in performance. This implementation has successfully enabled sustainable manufacturing environment.

Keywords: CNC, ISO 6983, ISO 14649, LabVIEW, open architecture control, reconfigurable manufacturing systems, sustainable manufacturing, Soft-CNC

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Authors: Ghofrane Rehaiem, Hamza Gharsellaoui, Samir Benahmed

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In this study, Artificial Neural Networks (ANNs) were used for modeling the parameters that allow the real-time scheduling of embedded systems under resources constraints designed for real-time applications running. The objective of this work is to implement a neural networks based approach for real-time scheduling of embedded systems in order to handle real-time constraints in execution scenarios. In our proposed approach, many techniques have been proposed for both the planning of tasks and reducing energy consumption. In fact, a combination of Dynamic Voltage Scaling (DVS) and time feedback can be used to scale the frequency dynamically adjusting the operating voltage. Indeed, we present in this paper a hybrid contribution that handles the real-time scheduling of embedded systems, low power consumption depending on the combination of DVS and Neural Feedback Scheduling (NFS) with the energy Priority Earlier Deadline First (PEDF) algorithm. Experimental results illustrate the efficiency of our original proposed approach.

Keywords: optimization, neural networks, real-time scheduling, low-power consumption

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Authors: Caje F. Pinto, Jivan S. Parab, Gourish M. Naik

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This paper is about the development of non-invasive heart rate and oxygen saturation in human blood using Altera NIOS II soft-core processor system. In today's world, monitoring oxygen saturation and heart rate is very important in hospitals to keep track of low oxygen levels in blood. We have designed an Embedded System On Peripheral Chip (SOPC) reconfigurable system by interfacing two LED’s of different wavelengths (660 nm/940 nm) with a single photo-detector to measure the absorptions of hemoglobin species at different wavelengths. The implementation of the interface with Finger Probe and Liquid Crystal Display (LCD) was carried out using NIOS II soft-core system running on Altera NANO DE0 board having target as Cyclone IVE. This designed system is used to monitor oxygen saturation in blood and heart rate for different test subjects. The designed NIOS II processor based non-invasive heart rate and oxygen saturation was verified with another Operon Pulse oximeter for 50 measurements on 10 different subjects. It was found that the readings taken were very close to the Operon Pulse oximeter.

Keywords: heart rate, NIOS II, oxygen saturation, photoplethysmography, soft-core, SOPC

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Authors: Yang Luo, Beibei Wang

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In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: side-channel analysis, hardware Trojan, register transfer level, dynamic power

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Authors: Wenxuan Li, Lei Li, Jin Li, Yuanhang He

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This paper designed a secure chip for IoT communication security integrated with the PUF-based firmware protection scheme. Then, the Xilinx Kintex-7 and STM-32 were used for the prototype verification. Firmware protection worked well on FPGA and embedded platforms. For the ASIC implementation of the PUF module, contact PUF is chosen. The post-processing method and its improvement are analyzed with emphasis. This paper proposed a more efficient post-processing method for contact PUF named SXOR, which has practical value for realizing lightweight security modules in IoT devices. The analysis was carried out under the hypothesis that the contact holes are independent and combine the existing data in the open literature. The post-processing effects of SXOR and XOR are basically the same under the condition that the proposed post-processing circuit occupies only 50.6% of the area of XOR. The average Hamming weight of the PUF output bit sequence obtained by the proposed post-processing method is 0.499735, and the average Hamming weight obtained by the XOR-based post-processing method is 0.499999.

Keywords: PUF, IoT, authentication, secure communication, encryption, XOR

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

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The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: hardware scheduler, nMPRA processor, real-time systems, scheduling methods

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Authors: Mansouri Nabila, Ben Jemaa Yousra, Motamed Cina, Watelain Eric

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Research and development efforts in intelligent Advanced Driver Assistance Systems (ADAS) seek to save lives and reduce the number of on-road fatalities. For traffic and emergency monitoring, the essential but challenging task is vehicle detection and tracking in reasonably short time. This purpose needs first of all a powerful dynamic car detector model. In fact, this paper presents an optimized HOG process based on shape and motion parameters fusion. Our proposed approach mains to compute HOG by bloc feature from foreground blobs using configurable research window and pathway in order to overcome the shortcoming in term of computing time of HOG descriptor and improve their dynamic application performance. Indeed we prove in this paper that HOG by bloc descriptor combined with motion parameters is a very suitable car detector which reaches in record time a satisfactory recognition rate in dynamic outside area and bypasses several popular works without using sophisticated and expensive architectures such as GPU and FPGA.

Keywords: car-detector, HOG, motion, computing time

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Authors: Pierobon Enrico, Missiaggia Marta, Castelluzzo Michele, Tommasino Francesco, Ricci Leonardo, Scifoni Emanuele, Vincezo Monaco, Boscardin Maurizio, La Tessa Chiara

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Clinical outcomes collected over the past three decades have suggested that ion therapy has the potential to be a treatment modality superior to conventional radiation for several types of cancer, including recurrences, as well as for other diseases. Although the results have been encouraging, numerous treatment uncertainties remain a major obstacle to the full exploitation of particle radiotherapy. To overcome therapy uncertainties optimizing treatment outcome, the best possible radiation quality description is of paramount importance linking radiation physical dose to biological effects. Microdosimetry was developed as a tool to improve the description of radiation quality. By recording the energy deposition at the micrometric scale (the typical size of a cell nucleus), this approach takes into account the non-deterministic nature of atomic and nuclear processes and creates a direct link between the dose deposited by radiation and the biological effect induced. Microdosimeters measure the spectrum of lineal energy y, defined as the energy deposition in the detector divided by most probable track length travelled by radiation. The latter is provided by the so-called “Mean Chord Length” (MCL) approximation, and it is related to the detector geometry. To improve the characterization of the radiation field quality, we define a new quantity replacing the MCL with the actual particle track length inside the microdosimeter. In order to measure this new quantity, we propose a two-stage detector consisting of a commercial Tissue Equivalent Proportional Counter (TEPC) and 4 layers of Low Gain Avalanche Detectors (LGADs) strips. The TEPC detector records the energy deposition in a region equivalent to 2 um of tissue, while the LGADs are very suitable for particle tracking because of the thickness thinnable down to tens of micrometers and fast response to ionizing radiation. The concept of HDM has been investigated and validated with Monte Carlo simulations. Currently, a dedicated readout is under development. This two stages detector will require two different systems to join complementary information for each event: energy deposition in the TEPC and respective track length recorded by LGADs tracker. This challenge is being addressed by implementing SoC (System on Chip) technology, relying on Field Programmable Gated Arrays (FPGAs) based on the Zynq architecture. TEPC readout consists of three different signal amplification legs and is carried out thanks to 3 ADCs mounted on a FPGA board. LGADs activated strip signal is processed thanks to dedicated chips, and finally, the activated strip is stored relying again on FPGA-based solutions. In this work, we will provide a detailed description of HDM geometry and the SoC solutions that we are implementing for the readout.

Keywords: particle tracking, ion therapy, low gain avalanche diode, tissue equivalent proportional counter, microdosimetry

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

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Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circuit. The nMPRA concept is a hardware processor with the scheduler implemented at the processor level; this is done without affecting a possible bus communication, as is the case with the other CPU solutions. The implementation of static or dynamic scheduling operations in hardware and the improvement of handling interrupts and events by the real-time executive described in the present article represent a key solution for eliminating the overhead of the operating system functions. The nMPRA processor is capable of executing a preemptive scheduling, using various algorithms without a software scheduler. Therefore, we have also presented various scheduling methods and algorithms used in scheduling the real-time tasks.

Keywords: nMPRA architecture, pipeline processor, preemptive scheduling, real-time system

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Authors: M. Y. Ismail, M. Inam

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This paper presents the design and analysis of Liquid Crystal (LC) based tunable reflectarray antenna with slot embedded patch element configurations within X-band frequency range. The slots are shown to modify the surface current distribution on the patch element of reflectarray which causes the resonant patch element to provide different resonant frequencies depending on the slot dimensions. The simulated results are supported and verified by waveguide scattering parameter measurements of different reflectarray unit cells. Different rectangular slots on patch element have been fabricated and a change in resonant frequency from 10.46GHz to 8.78GHz has been demonstrated as the width of the rectangular slot is varied from 0.2W to 0.6W. The rectangular slot in the center of the patch element has also been utilized for the frequency tunable reflectarray antenna design based on K-15 Nematic LC. For the active reflectarray antenna design, a frequency tunability of 1.2% from 10GHz to 9.88GHz has been demonstrated with a dynamic phase range of 103° provided by the measured scattering parameter results. Time consumed by liquid crystals for reconfiguration, which is one of the drawback of LC based design, has also been disused in this paper.

Keywords: liquid crystal, tunable reflectarray, frequency tunability, dynamic phase range

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Authors: Larissa Negris de Souza, Ana Regina Mizrahy Cuperschmid, Daniel de Carvalho Moreira

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Augmented Reality (AR) alters the elaboration of the architectural project, which relates to project cognition: representation, visualization, and perception of information. Understanding these features from the earliest stages of the design can facilitate the study of relationships, zoning, and overall dimensions of the forms. This paper’s goal was to explore a new approach for information visualization during the early stages of architectural design using Augmented Reality (AR). A three-dimensional marker inspired by the Rubik’s Cube was developed, and its performance, evaluated. This investigation interwovens the acquired knowledge of traditional briefing methods and contemporary technology. We considered the concept of patterns (Alexander et al. 1977) to outline geometric forms and associations using visual programming. The Design Science Research was applied to develop the study. An SDK was used in a game engine to generate the AR app. The tool's functionality was assessed by verifying the readability and precision of the reconfigurable 3D marker. The results indicated an inconsistent response. To use AR in the early stages of architectural design the system must provide consistent information and appropriate feedback. Nevertheless, we conclude that our framework sets the ground for looking deep into AR tools for briefing design.

Keywords: augmented reality, cuboid marker, early design stages, graphic representation, patterns

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Authors: Farzad Yavari, Fereydoun Ohadi

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Today, with the development and growth of technology and extreme environmental changes, organizations need to identify opportunities and create creativity and innovation in order to be able to maintain or improve their position in competition with others. In this regard, it is necessary that the resources and assets of the organization are coordinated and reviewed in accordance with the orientation of the strategy. One of the competitive advantages of the present age is knowledge management, which is to equip the organization with the knowledge of the day and disseminate among employees and use it in the development of products and services. Therefore, in the forthcoming research, the impact of dynamic capabilities components (sense, seize, and reconfiguration) has been investigated on knowledge management processes (acquisition, integration and knowledge utilization) in the MAPNA Engineering and Construction Company using a field survey and applied research method. For this purpose, a questionnaire was filled out in the form of 15 questions for dynamic components and 15 questions for measuring knowledge management components and distributed among 46 employees of the knowledge management organization. Validity of the questionnaire was evaluated through content validity and its reliability with Cronbach's coefficient. Pearson correlation test and structural equation technique were used to analyze the data. The results of the research indicate a positive significant correlation between the components of dynamic capabilities and knowledge management.

Keywords: dynamic capabilities, knowledge management, sense capability, seize capability, reconfigurable capability, knowledge acquisition, knowledge integrity, knowledge utilization

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Authors: Hazem Abd El Megeed, Mohamed El-Refaay, Norhan Magdi Osman

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Spectrum scarcity is a challenging obstacle in wireless communications systems. It hinders the introduction of innovative wireless services and technologies that require larger bandwidth comparing to legacy technologies. In addition, the current worldwide allocation of radio spectrum bands is already congested and can not afford additional squeezing or optimization to accommodate new wireless technologies. This challenge is a result of accumulative contributions from different factors that will be discussed later in this paper. One of these factors is the radio spectrum allocation policy governed by national regulatory authorities nowadays. The framework for this policy allocates specified portion of radio spectrum to a particular wireless service provider on exclusive utilization basis. This allocation is executed according to technical specification determined by the standard bodies of each Radio Access Technology (RAT). Dynamic access of spectrum is a framework for flexible utilization of radio spectrum resources. In this framework there is no exclusive allocation of radio spectrum and even the public safety agencies can share their spectrum bands according to a governing policy and service level agreements. In this paper, we explore different methods for accessing the spectrum dynamically and its associated implementation challenges.

Keywords: licensed shared access, cognitive radio, spectrum sharing, spectrum congestion, dynamic spectrum access, spectrum database, spectrum trading, reconfigurable radio systems, opportunistic spectrum allocation (OSA)

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Authors: Ebrahim H. Kapeel, Ehab Safwat, Hossam Hendy, Ahmed M. Kamel, Yehia Z. Elhalwagy

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Motivated by the problem of the availability of high-fidelity flight simulation models for small unmanned aerial vehicles (UAVs). This paper focuses on the geometric-mass inertia modeling and the actuation system modeling for the small fixed-wing UAVs. The UAV geometric parameters for the body, wing, horizontal and vertical tail are physically measured. Pendulum experiment with high-grade sensors and data analysis using MATLAB is used to estimate the airplane moment of inertia (MOI) model. Finally, UAV’s actuation system is modeled by estimating each servo transfer function by using the system identification, which uses experimental measurement for input and output angles through using field-programmable gate array (FPGA). Experimental results for the designed models are given to illustrate the effectiveness of the methodology. It also gives a very promising result to finalize the open-loop flight simulation model through modeling the propulsion system and the aerodynamic system.

Keywords: unmanned aerial vehicle, geometric-mass inertia model, system identification, Simulink

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

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In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: frequency measurement, digital control, phase locked loop, encoder, Verilog HDL

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Authors: H.-H. Doh, J.-M. Yu, Y.-J. Kwon, J.-H. Shin, H.-W. Kim, S.-H. Nam, D.-H. Lee

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This paper suggests a decision tree based approach for flexible job shop scheduling with multiple process plans, i. e. each job can be processed through alternative operations, each of which can be processed on alternative machines. The main decision variables are: (a) selecting operation/machine pair; and (b) sequencing the jobs assigned to each machine. As an extension of the priority scheduling approach that selects the best priority rule combination after many simulation runs, this study suggests a decision tree based approach in which a decision tree is used to select a priority rule combination adequate for a specific system state and hence the burdens required for developing simulation models and carrying out simulation runs can be eliminated. The decision tree based scheduling approach consists of construction and scheduling modules. In the construction module, a decision tree is constructed using a four-stage algorithm, and in the scheduling module, a priority rule combination is selected using the decision tree. To show the performance of the decision tree based approach suggested in this study, a case study was done on a flexible job shop with reconfigurable manufacturing cells and a conventional job shop, and the results are reported by comparing it with individual priority rule combinations for the objectives of minimizing total flow time and total tardiness.

Keywords: flexible job shop scheduling, decision tree, priority rules, case study

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Authors: Ghodbane Azeddine, Saad Maarouf, Boland Jean-Francois, Thibeault Claude

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This paper proposes a new design of an active fault-tolerant flight control system against abrupt actuator faults. This overall system combines a multiple time scale sliding mode controller for fault compensation and a geometric approach for fault detection and diagnosis. The proposed control system is able to accommodate several kinds of partial and total actuator failures, by using available healthy redundancy actuators. The overall system first estimates the correct fault information using the geometric approach. Then, and based on that, a new reconfigurable control law is designed based on the multiple time scale sliding mode technique for on-line compensating the effect of such faults. This approach takes advantages of the fact that there are significant difference between the time scales of aircraft states that have a slow dynamics and those that have a fast dynamics. The closed-loop stability of the overall system is proved using Lyapunov technique. A case study of the non-linear model of the F16 fighter, subject to the rudder total loss of control confirms the effectiveness of the proposed approach.

Keywords: actuator faults, fault detection and diagnosis, fault tolerant flight control, sliding mode control, multiple time scale approximation, geometric approach for fault reconstruction, lyapunov stability

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Authors: A. Ghodbane, M. Saad, J. F. Boland, C. Thibeault

Abstract:

Historically, actuators’ redundancy was used to deal with faults occurring suddenly in flight systems. This technique was generally expensive, time consuming and involves increased weight and space in the system. Therefore, nowadays, the on-line fault diagnosis of actuators and accommodation plays a major role in the design of avionic systems. These approaches, known as Fault Tolerant Flight Control systems (FTFCs) are able to adapt to such sudden faults while keeping avionics systems lighter and less expensive. In this paper, a (FTFC) system based on the Geometric Approach and a Reconfigurable Flight Control (RFC) are presented. The Geometric approach is used for cosmic ray fault reconstruction, while Sliding Mode Control (SMC) based on Lyapunov stability theory is designed for the reconfiguration of the controller in order to compensate the fault effect. Matlab®/Simulink® simulations are performed to illustrate the effectiveness and robustness of the proposed flight control system against actuators’ faulty signal caused by cosmic rays. The results demonstrate the successful real-time implementation of the proposed FTFC system on a non-linear 6 DOF aircraft model.

Keywords: actuators’ faults, fault detection and diagnosis, fault tolerant flight control, sliding mode control, geometric approach for fault reconstruction, Lyapunov stability

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Authors: M. Iruleswari, A. Jeyapaul Murugan

Abstract:

Most fundamental part used in many Digital Signal Processing (DSP) application is a Finite Impulse Response (FIR) filter because of its linear phase, stability and regular structure. Designing a high-speed and hardware efficient FIR filter is a very challenging task as the complexity increases with the filter order. In most applications the higher order filters are required but the memory usage of the filter increases exponentially with the order of the filter. Using multipliers occupy a large chip area and need high computation time. Multiplier-less memory-based techniques have gained popularity over past two decades due to their high throughput processing capability and reduced dynamic power consumption. This paper describes the design and implementation of highly efficient Look-Up Table (LUT) based circuit for the implementation of FIR filter using Distributed arithmetic algorithm. It is a multiplier less FIR filter. The LUT can be subdivided into a number of LUT to reduce the memory usage of the LUT for higher order filter. Analysis on the performance of various filter orders with different address length is done using Xilinx 14.5 synthesis tool. The proposed design provides less latency, less memory usage and high throughput.

Keywords: finite impulse response, distributed arithmetic, field programmable gate array, look-up table

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