Search results for: silicon controlled rectifier (SCR)

Authors: Kyoung-Il Do, Jun-Geol Park, Hee-Guk Chae, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

A SCR stacking structure is proposed to have improved Latch-up immunity. In comparison with conventional SCR (Silicon Controlled Rectifier), the proposed Electrostatic Discharge (ESD) protection circuit has a lower trigger characteristic by using the LVTSCR (Low Voltage Trigger) structure. Also the proposed ESD protection circuit has improved Holding Voltage Characteristic by using N-stack technique. These characteristics enable to have latch-up immunity in operating conditions. The simulations are accomplished by using the Synopsys TCAD. It has a trigger voltage of 8.9V and a holding voltage of 1.8V in a single structure. And when applying the stack technique, 2-stack has the holding voltage of 3.8V and 3-stack has the holding voltage of 5.1 V.

Keywords: electrostatic discharge (ESD), low voltage trigger silicon controlled rectifier (LVTSCR), MVTSCR, power clamp, silicon controlled rectifier (SCR), latch-up

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Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

Abstract:

In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

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Authors: Jun-Geol Park, Kyoung-Il Do, Min-Ju Kwon, Kyung-Hyun Park, Yong-Seo Koo

Abstract:

This paper analyzed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuits with the turn-on time characteristics. The structures are the LVTSCR (Low Voltage Triggered SCR), the ZTSCR (Zener Triggered SCR) and the PTSCR (P-Substrate Triggered SCR). The three structures are for the 5V power clamp. In general, the structures with the low trigger voltage structure can have the fast turn-on characteristics than other structures. All the ESD protection circuits have the low trigger voltage by using the N+ bridge region of LVTSCR, by using the zener diode structure of ZTSCR, by increasing the trigger current of PTSCR. The simulation for the comparison with the turn-on time was conducted by the Synopsys TCAD simulator. As the simulation results, the LVTSCR has the turn-on time of 2.8 ns, ZTSCR of 2.1 ns and the PTSCR of 2.4 ns. The HBM simulation results, however, show that the PTSCR is the more robust structure of 430K in HBM 8kV standard than 450K of LVTSCR and 495K of ZTSCR. Therefore the PTSCR is the most effective ESD protection circuit for the 5V power clamp.

Keywords: ESD, SCR, turn-on time, trigger voltage, power clamp

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Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao

Abstract:

A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.

Keywords: bridgeless boost (BLB), boost converter, power factor correction (PFC), hold-up time

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Authors: Hafez Fouad

Abstract:

Telemedicine applications have very low voltage which required High Precision Rectifier Design with high Sensitivity to operate at minimum input Voltage. In this work, we targeted 0.2V input voltage using 65 nm CMOS rectifier for Energy Harvesting Telemedicine application. The proposed rectifier which designed at 2.4GHz using two-stage structure found to perform in a better case where minimum operation voltage is lower than previous published paper and the rectifier can work at a wide range of low input voltage amplitude. The Performance Summary of Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2 V are 490.9 mV and 1.997 V, maximum VCE = 99.85 % and maximum PCE = 46.86 %. The Performance Summary of Differential drive CMOS rectifier with external bootstrapping circuit rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2V are 265.5 mV (0.265V) and 1.467 V respectively, maximum VCE = 93.9 % and maximum PCE= 15.8 %.

Keywords: energy harvesting, embedded system, IoT telemedicine system, threshold voltage minimization, differential drive cmos rectifier, full-wave fully gate cross-coupled rectifiers CMOS rectifier

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Authors: Jonas Kristiansen Nøland, Karina Hjelmervik, Urban Lundin

Abstract:

The thyristor bridge rectifier is often used for control of excitation equipment for synchronous generators. However, on the rotating shaft of brushless exciters, the diode bridge rectifier is mostly used. The step response of a conventional brushless rotating excitation system is slow compared to static excitation systems. This paper investigates the performance of different thyristor-controlled rectification topologies applied on the shaft of a 6-phase PMG exciter connected to a synchronous generator. One of the important issues is the steady-state torque ripple produced by the thyristor bridges.

Keywords: brushless exciters, rotating exciters, permanent magnet machines, synchronous generators

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Authors: Rawaa Maher, Ahmed Allam, Haruichi Kanaya, Adel B. Abdelrahman

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In this paper, a compact, high-efficiency integrated rectenna is presented to operate in the 2.45 GHz band. A comparison between two rectifier topologies is performed to verify the benefits of removing the matching network from the rectifier. A rectifier high conversion efficiency of 74.1% is achieved. To complete the rectenna system, a novel omnidirectional antenna with high gain (3.72 dB) and compact size (25 mm * 29 mm) is designed and fabricated. The same antenna is used with a reflector for raising the gain to nearly 8.3 dB. The simulation and measurement results of the antenna are in good agreement.

Keywords: internet of things, integrated rectenna, rectenna, RF energy harvesting, wireless sensor networks(WSN)

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Authors: Amirouche Hammouda, Nacer Boucherou, Aicha Ziouche, Hayet Boudjellal

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Silicon has excellent physical and electrical properties for optoelectronics industry. It is a promising material with many advantages. On Raman characterization of thin films deposited on crystalline silicon substrate, the signal Raman of amorphous silicon is often disturbed by the Raman signal of the crystalline silicon substrate. In this paper, we propose to characterize thin layers of amorphous silicon deposited on crystalline silicon substrates. The results obtained have shown the possibility to bring out the Raman spectrum of deposited layers by optimizing experimental parameters.

Keywords: raman scattering, amorphous silicon, crystalline silicon, thin films

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Authors: Gu Zhonghua

Abstract:

Control method of bulk silicon dioxide etching process to approach then expose silicon waveguide has been developed. It has been demonstrated by silicon waveguide of photonics devices. It is also able to generalize other applications. Use plasma dry etching to etch bulk silicon dioxide and approach oxide-silicon interface accurately, then use dilute HF wet etching to etch silicon dioxide residue layer to expose the silicon waveguide as soft landing. Plasma dry etch macro loading effect and endpoint technology was used to determine dry etch time accurately with a low wafer expose ratio.

Keywords: waveguide, etch, control, silicon loss

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Authors: Ashot Navasardian, Mariam Vardanian, Vladik Vardanian

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The photovoltaic and the semiconductor industries are in growth and it is necessary to supply a large amount of silicon to maintain this growth. Since silicon is still the best material for the manufacturing of solar cells and semiconductor components so the pure silicon like solar grade and semiconductor grade materials are demanded. There are two main routes for silicon production: metallurgical and chemical. In this article, we reviewed the electrotecnological installations and systems for semiconductor manufacturing. The main task is to design the installation which can produce SOG Silicon from river sand by one work unit.

Keywords: metallurgical grade silicon, solar grade silicon, impurity, refining, plasma

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Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

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In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Jun-Geol Park, Kyoung-Il Do, Min-Ju Kwon, Kyung-Hyun Park, Yong-Seo Koo

Abstract:

In this paper, we proposed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuit for latch-up immunity. The proposed circuit has a lower trigger voltage and a higher holding voltage characteristic by using the zener diode structure. These characteristics prevent latch-up problem in normal operating conditions. The proposed circuit was analyzed to figure out the electrical characteristics by the variations of design parameters D1, D2 and stack technology to obtain the n-fold electrical characteristics. The simulations are accomplished by using the Synopsys TCAD simulator. When using the stack technology, 2-stack has the holding voltage of 6.9V and 3-stack has the holding voltage of 10.9V.

Keywords: ESD, SCR, trigger voltage, holding voltage

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Authors: Alexey P. Antropov, Alexander V. Ragutkin, Nicolay A. Yashtulov

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The original controlled technology for power active nanocomposite membrane-electrode assembly engineering on the basis of porous silicon is presented. The functional nanocomposites were studied by electron microscopy and cyclic voltammetry methods. The application possibility of the obtained nanocomposites as high performance renewable energy sources for micro-power electronic devices is demonstrated.

Keywords: cyclic voltammetry, electron microscopy, nanotechnology, platinum-palladium nanocomposites, porous silicon, power activity, renewable energy sources

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Authors: Ahmad Shah Irshad, Naqibullah Kargar, Wais Samadi

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Building an integrated photovoltaic (BIPV) system is a new and modern technique for solar energy production in Kandahar. Due to its location, Kandahar has abundant sources of solar energy. People use both monocrystalline and polycrystalline silicon solar PV modules for the grid-connected solar PV system, and they don’t know which technology performs better for the BIPV system. This paper analyses the parameters described by IEC61724, “Photovoltaic System Performance Monitoring Guidelines for Measurement, Data Exchange and Analysis,” to evaluate which technology shows better performance for the BIPV system. The monocrystalline silicon BIPV system has a 3.1% higher array yield than the polycrystalline silicon BIPV system. The final yield is 0.2%, somewhat higher for monocrystalline silicon than polycrystalline silicon. Monocrystalline silicon has 0.2% and 4.5% greater yearly yield factor and capacity factors than polycrystalline silicon, respectively. Monocrystalline silicon shows 0.3% better performance than polycrystalline silicon. With 1.7% reduction and 0.4% addition in collection losses and useful energy produced, respectively, monocrystalline silicon solar PV system shows good performance than polycrystalline silicon solar PV system. But system losses are the same for both technologies. The monocrystalline silicon BIPV system injects 0.2% more energy into the grid than the polycrystalline silicon BIPV system.

Keywords: photovoltaic technologies, performance analysis, solar energy, solar irradiance, performance ratio

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Authors: Amirhossein Hasani, Shamin Houshmand Sharifi

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In this work, we investigate humidity sensing behavior of the graphene oxide with porous silicon substrate. By evaporation method, aluminum interdigital electrodes have been deposited onto porous silicon substrate. Then, by drop-casting method graphene oxide solution was deposited onto electrodes. The porous silicon was formed by electrochemical etching. The experimental results showed that using porous silicon substrate, we obtained two times larger sensitivity and response time compared with the results obtained with silicon substrate without porosity.

Keywords: graphene oxide, porous silicon, humidity sensor, electrochemical

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Authors: T. Mohammed Chikouche, K. Hartani

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In order to solve the instantaneous power ripple and achieve better performance of direct power control (DPC) for a three-phase PWM rectifier, a control method is proposed in this paper. This control method is applied to overcome the instantaneous power ripple, to eliminate line current harmonics and therefore reduce the total harmonic distortion and to improve the power factor. A switching table is based on the analysis on the change of instantaneous active and reactive power, to select the optimum switching state of the three-phase PWM rectifier. The simulation result shows feasibility of this control method.

Keywords: power quality, direct power control, power ripple, switching table, unity power factor

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Authors: Noor Leha Abdul Rahman, Koay Mei Hyie, Anizah Kalam, Husna Elias, Teng Wang Dung

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Dark Red Meranti and Kapur, kinds of important type of wood in Malaysia were used as a precursor to fabricate porous silicon carbide. A carbon template is produced by pyrolysis at 850°C in an oxygen free atmosphere. The carbon template then further subjected to infiltration with silicon by silicon melt infiltration method. The infiltration process was carried out in tube furnace in argon flow at 1500°C, at two different holding time; 2 hours and 3 hours. Thermo gravimetric analysis was done to investigate the decomposition behavior of two species of plants. The resulting silicon carbide was characterized by XRD which was found the formation of silicon carbide and also excess silicon. The microstructure was characterized by scanning electron microscope (SEM) and the density was determined by the Archimedes method. An increase in holding time during infiltration will increased the density as well as formation of silicon carbide. Dark Red Meranti precursor is likely suitable for production of silicon carbide compared to Kapur.

Keywords: density, SEM, silicon carbide, XRD

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Authors: Tarik Ouslimane, Abdenour Lami, Salaheddine Aoudj, Mouna Hecini, Ouahiba Bouchelaghem, Nadjib Drouiche

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Slurry waste is a byproduct generated from the slicing process of multi-crystalline silicon ingots. This waste can be used as a secondary resource to recover high purity silicon which has a great economic value. From the management perspective, the ever increasing generation of kerf slurry waste loss leads to significant challenges for the photovoltaic industry due to the current low use of slurry waste for silicon recovery. Slurry waste, in most cases, contains silicon, silicon carbide, metal fragments and mineral-oil-based or glycol-based slurry vehicle. As a result, of the global scarcity of high purity silicon supply, the high purity silicon content in slurry has increasingly attracted interest for research. This paper presents a critical overview of the current techniques employed for high purity silicon recovery from kerf slurry waste. Hydrometallurgy is continuously a matter of study and research. However, in this review paper, several new techniques about the process of high purity silicon recovery from slurry waste are introduced. The purpose of the information presented is to improve the development of a clean and effective recovery process of high purity silicon from slurry waste.

Keywords: Kerf-loss, slurry waste, silicon carbide, silicon recovery, photovoltaic, high purity silicon, polyethylen glycol

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Authors: Mohamed Ben Rabha

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In this paper, we report on the effect of porous silicon (PS) treatment on the surface passivation of monocrystalline silicon (c-Si). PS film with a thickness of 80 nm was deposited by stain etching. It was demonstrated that PS coating is a very interesting solution for surface passivation. The level of surface passivation is determined by techniques based on photoconductance and FTIR. As a results, the effective minority carrier lifetime increase from 2 µs to 7 µs at ∆n=1015 cm-3 and the reflectivity reduce from 28 % to about 7 % after PS coating.

Keywords: porous silicon, effective minority carrier lifetime, reflectivity

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Authors: Ching-Hua Li, Sheng-Hui Chen

Abstract:

Sputtering is a popular technique with many advantages for thin film deposition. To fabricate a hydrogenated silicon thin film using sputtering process for solar cell applications, the ion bombardment during sputtering will generate microstructures (voids and columnar structures) to form silicon dihydride bodings as defects. The properties of heterojunction silicon solar cells were studied by using boron grains and silicon-boron targets. Finally, an 11.7% efficiency of solar cell was achieved by using all sputtering process.

Keywords: solar cell, sputtering process, pvd, alloy target

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Authors: Juntao Li

Abstract:

The metasurfaces for beam deflecting with gradient silicon posts in the square lattices were fabricated on the thin film crystal silicon with quartz substrate. By using the crystals silicon with high refractive index and high transmission to control the phase over 2π coverage, we demonstrated the polarization independent beam deflecting at wavelength of 532nm with 45% transmission in experiment and 70% in simulation into the desired angle. This simulation efficiency is almost close to the TiO2 metasurfaces but has higher refractive index and lower aspect ratio to reduce fabrication complexity. The result can extend the application of silicon metalsurfaces from 700 nm to 500 nm hence open a new way to use metasurfaces efficiently in visible light regime.

Keywords: metasurfaces, crystal silicon, light deflection, visible light

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Authors: M. R. Gad El- Kareem, A. M. K. Abdel Aal, A. Y. Mohamed

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During 2011 and 2012 seasons, Zaghloul date palms received four sprays of silicon (Si) at 0.05 to 0.1% and selenium (Se) at 0.01 to 0.02%. Growths, nutritional status, yield as well as physical and chemical characteristics of the fruits in response to application of silicon and selenium were investigated. Single and combined applications of silicon at 0.05 to 0.1% and selenium at 0.01 to 0.02% was very effective in enhancing the leaf area, total chlorophylls, percentages of N, P, and K in the leaves, yield, bunch weight as well as physical and chemical characteristics of the fruits in relative to the check treatment. Silicon was superior to selenium in this respect. Combined application was favourable than using each alone in this connection. Treating Zaghloul date palms four times with a mixture of silicon at 0.05% + selenium at 0.01% resulted in an economical yield and producing better fruit quality.

Keywords: date palms, Zaghloul, silicon, selenium, leaf area

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Authors: Hyun Young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon Cho, Yong Seo Koo

Abstract:

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp

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Authors: Luc Conti, Dimitry Dumont-Fillon, Harald van Lintel, Eric Chappel

Abstract:

Flow control valves comprise a silicon flexible membrane that deflects against a substrate, usually made of glass, containing pillars, an outlet hole, and anti-stiction features. However, there is a strong interest in using silicon instead of glass as substrate material, as it would simplify the process flow by allowing the use of well controlled anisotropic etching. Moreover, specific devices demanding a bending of the substrate would also benefit from the inherent outstanding mechanical strength of monocrystalline silicon. Unfortunately, direct Si-Si bonding is not easily achieved with highly structured wafers since residual stress may prevent the good adhesion between wafers. Using a thermoplastic polymer, such as parylene, as intermediate layer is not well adapted to this design as the wafer-to-wafer alignment is critical. An alternative anodic bonding method using an intermediate borosilicate layer has been successfully tested. This layer has been deposited onto the silicon substrate. The bonding recipe has been adapted to account for the presence of the SOI buried oxide and intermediate glass layer in order not to exceed the breakdown voltage. Flow control valves dedicated to infusion of viscous fluids at very high pressure have been made and characterized. The results are compared to previous data obtained using the standard anodic bonding method.

Keywords: anodic bonding, evaporated glass, flow control valve, drug delivery

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Authors: Madina Alimova, Margulan Ibraimov, Ayan Tileu

Abstract:

The paper describes methods for obtaining porous structures with the properties of a silicon-based memristor and explains the electrical properties of porous silicon films. Based on the results, there is a positive shift in the current-voltage characteristics (CVC) after each measurement, i.e., electrical properties depend not only on the applied voltage but also on the previous state. After 3 minutes of rest, the film returns to its original state (reset). The method for obtaining a porous silicon nanofilm with the properties of a memristor is simple and does not require additional effort. Based on the measurement results, the typical memristive behavior of the porous silicon nanofilm is analyzed.

Keywords: porous silicon, current-voltage characteristics, memristor, nanofilms

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Authors: M. Barbouche, M. Hajji, H. Ezzaouia

Abstract:

This project is a step to manufacture solar grade silicon. It consists in designing an electrical arc furnace in order to produce metallurgical silicon Mg-Si with mutually carbon and high purity of silica. It concerns, first, the development of a functional analysis, a mechanical design and thermodynamic study. Our study covers also, the design of the temperature control system and the design of the electric diagrams. The furnace works correctly. A Labview interface was developed to control all parameters and to supervise the operation of furnace. Characterization tests with X-ray technique and Raman spectroscopy allow us to confirm the metallurgical silicon production.

Keywords: arc furnace, electrical design, silicon manufacturing, regulation, x-ray characterization

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Authors: N. I. Kargin, G. K. Safaraliev, A. S. Gusev, A. O. Sultanov, N. V. Siglovaya, S. M. Ryndya, A. A. Timofeev

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In this paper, an experimental and theoretical study of the processes of mesoporous silicon carbonization during the formation of buffer layers for the subsequent epitaxy of 3C-SiC films and related wide-band-gap semiconductors is performed. Experimental samples were obtained by the method of chemical vapor deposition and investigated by scanning electron microscopy. Analytic expressions were obtained for the effective diffusion factor and carbon atoms diffusion length in a porous system. The proposed model takes into account the processes of Knudsen diffusion, coagulation and overgrowing of pores during the formation of a silicon carbide layer.

Keywords: silicon carbide, porous silicon, carbonization, electrochemical etching, diffusion

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Authors: Dimassi Wissem

Abstract:

In this work, we investigate the effect of combination between the porous silicon (PS) layer passivized with Lithium Bromide (LiBr) and grooving of grain boundaries (GB) in multi crystalline silicon. The grain boundaries were grooved in order to reduce the area of these highly recombining regions. Using optimized conditions, grooved GB's enable deep phosphorus diffusion and deep metallic contacts. We have evaluated the effects of LiBr on the surface properties of porous silicon on the performance of silicon solar cells. The results show a significant improvement of the internal quantum efficiency, which is strongly related to the photo-generated current. We have also shown a reduction of the surface recombination velocity and an improvement of the diffusion length after the LiBr process. As a result, the I–V characteristics under the dark and AM1.5 illumination were improved. It was also observed a reduction of the GB recombination velocity, which was deduced from light-beam-induced-current (LBIC) measurements. Such grooving in multi crystalline silicon enables passivization of GB-related defects. These results are discussed and compared to solar cells based on untreated multi crystalline silicon wafers.

Keywords: Multicrystalline silicon, LiBr, porous silicon, passivation

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Authors: Yodai Ashikubo, Toshiaki Suzuki, Satoshi Kouya, Mitsuya Motohashi

Abstract:

Functional microstructures such as wires, fins, needles, and rolls are currently being applied to variety of high-performance devices. Under these conditions, a roll structure (silicon micro-nanoroll) was formed on the surface of the silicon substrate via fine bubbles during anodization using an extremely diluted hydrofluoric acid (HF + H₂O). The as-formed roll had a microscale length and width of approximately 1 µm. The number of rolls was 3-10 times and the thickness of the film forming the rolls was about 10 nm. Thus, it is promising for applications as a distinct device material. These rolls functioned as capsules and/or pipelines. To date, number of rolls and roll length have been controlled by anodization conditions. In general, controlling the position and roll winding state is required for device applications. However, it has not been discussed. Grooves formed on silicon surface before anodization might be useful control the bubbles. In this study, we investigated the effect of the grooves on the position and shape of the roll. The surfaces of the silicon wafers were anodized. The starting material was p-type (100) single-crystalline silicon wafers. The resistivity of the wafer is 5-20 ∙ cm. Grooves were formed on the surface of the substrate before anodization using sandpaper and diamond pen. The average width and depth of the grooves were approximately 1 µm and 0.1 µm, respectively. The HF concentration {HF/ (HF + C₂H5OH + H₂O)} was 0.001 % by volume. The C2H5OH concentration {C₂H5OH/ (HF + C₂H5OH + H₂O)} was 70 %. A vertical single-tank cell and Pt cathode were used for anodization. The silicon roll was observed by field-emission scanning electron microscopy (FE-SEM; JSM-7100, JEOL). The atomic bonding state of the rolls was evaluated using X-ray photoelectron spectroscopy (XPS; ESCA-3400, Shimadzu). For straight groove, the rolls were formed along the groove. This indicates that the orientation of the rolls can be controlled by the grooves. For lattice-like groove, the rolls formed inside the lattice and along the long sides. In other words, the aspect ratio of the lattice is very important for the roll formation. In addition, many rolls were formed and winding states were not uniform when the lattice size is too large. On the other hand, no rolls were formed for small lattice. These results indicate that there is the optimal size of lattice for roll formation. In the future, we are planning on formation of rolls using groove formed by lithography technique instead of sandpaper and the pen. Furthermore, the rolls included nanoparticles will be formed for nanodevices.

Keywords: silicon roll, anodization, fine bubble, microstructure

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