Search results for: SOI-TRI Gate FinFET

Authors: Mojtaba Valinataj

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Nowadays reversible logic has received many attentions as one of the new fields for reducing the power consumption. On the other hand, the processing systems have weaknesses against different external effects. In this paper, some error detecting reversible logic serial multipliers are proposed by incorporating the parity-preserving gates. This way, the new designs are presented for signed parity-preserving serial multipliers based on the Booth's algorithm by exploiting the new arrangements of existing gates. The experimental results show that the proposed 4×4 multipliers in this paper reach up to 20%, 35%, and 41% enhancements in the number of constant inputs, quantum cost, and gate count, respectively, as the reversible logic criteria, compared to previous designs. Furthermore, all the proposed designs have been generalized for n×n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size.

Keywords: Booth’s algorithm, error detection, multiplication, parity-preserving gates, quantum computers, reversible logic

Procedia PDF Downloads 228

Authors: Florian Gschösser, Walter Purrer

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The paper shows examples for the (environmental) optimization of production processes for asphalt mixtures applied for typical road pavements in Austria and Switzerland. The conducted “from-cradle-to-gate” LCA firstly analyzes the production one cubic meter of asphalt and secondly all material production processes for exemplary highway pavements applied in Austria and Switzerland. It is shown that environmental impacts can be reduced by the application of reclaimed asphalt pavement (RAP) and by the optimization of specific production characteristics, e.g. the reduction of the initial moisture of the mineral aggregate and the reduction of the mixing temperature by the application of low-viscosity and foam bitumen. The results of the LCA study demonstrate reduction potentials per cubic meter asphalt of up to 57 % (Global Warming Potential–GWP) and 77 % (Ozone depletion–ODP). The analysis per square meter of asphalt pavement determined environmental potentials of up to 40 % (GWP) and 56 % (ODP).

Keywords: asphalt mixtures, environmental potentials, life cycle assessment, material production

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Authors: A. Boursali, A. Guen-Bouazza

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We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/m, a peak extrinsic transconductance of 0.59S/m at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, leakage current density IFuite=1 x 10-26 A, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, silvaco, field plate, genetic algorithm, quantum

Procedia PDF Downloads 349

Authors: Z. Kourdi, B. Bouazza, M. Khaouani, A. Guen-Bouazza, Z. Djennati, A. Boursali

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We present a simulation of a HEMT (high electron mobility transistor) structure with and without a field plate. We extract the device characteristics through the analysis of DC, AC and high frequency regimes, as shown in this paper. This work demonstrates the optimal device with a gate length of 15 nm, InAlN/GaN heterostructure and field plate structure, making it superior to modern HEMTs when compared with otherwise equivalent devices. This improves the ability to bear the burden of the current density passes in the channel. We have demonstrated an excellent current density, as high as 2.05 A/mm, a peak extrinsic transconductance of 590 mS/mm at VDS=2 V, and cutting frequency cutoffs of 638 GHz in the first HEMT and 463 GHz for Field plate HEMT., maximum frequency of 1.7 THz, maximum efficiency of 73%, maximum breakdown voltage of 400 V, DIBL=33.52 mV/V and an ON/OFF current density ratio higher than 1 x 1010. These values were determined through the simulation by deriving genetic and Monte Carlo algorithms that optimize the design and the future of this technology.

Keywords: HEMT, Silvaco, field plate, genetic algorithm, quantum

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Authors: M. Mansouri, P. Jaklitsch, E. Teiniker

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SQL injection on web applications is a very popular kind of attack. There are mechanisms such as intrusion detection systems in order to detect this attack. These strategies often rely on techniques implemented at high layers of the application but do not consider the low level of system calls. The problem of only considering the high level perspective is that an attacker can circumvent the detection tools using certain techniques such as URL encoding. One technique currently used for detecting low-level attacks on privileged processes is the tracing of system calls. System calls act as a single gate to the Operating System (OS) kernel; they allow catching the critical data at an appropriate level of detail. Our basic assumption is that any type of application, be it a system service, utility program or Web application, “speaks” the language of system calls when having a conversation with the OS kernel. At this level we can see the actual attack while it is happening. We conduct an experiment in order to demonstrate the suitability of system call analysis for detecting SQL injection. We are able to detect the attack. Therefore we conclude that system calls are not only powerful in detecting low-level attacks but that they also enable us to detect high-level attacks such as SQL injection.

Keywords: Linux system calls, web attack detection, interception, SQL

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Authors: Amira Balaska, Ali Tahri, Amine Boudghene Stambouli, Takashi Oozeki

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This paper is dealing with the evaluation of photovoltaic modules as part of the Sahara Solar Breeder project (SSB), five different photovoltaic module technologies which are: m-si, CIS, HIT, Back Contact, a-si_μc -si and a weather station recently installed at the University of Saida (Tahar Moulay) in Saida city located at the gate of the great southern Algeria’s Sahara. The objective of the present work is the study of solar photovoltaic capacity and performance parameters of each PV module technology. The goal of the study is to compare the five different PV technologies in order to find which technologies are suitable for the climate conditions of Algeria’s desert. Measurements of various parameters as irradiance, temperature, humidity and so on by the weather station and I-V curves were performed outdoors at the location without shadow. Finally performance parameters as performance ratio, energy yield and temperature losses are given and analyzed.

Keywords: photovoltaic modules, performance ratio, energy yield, sahara solar breeder, outdoor conditions

Procedia PDF Downloads 662

Authors: Soumitr Sanjay Dubey, Shubhajit Roy Chowdhury, Rahul Shrestha

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In this paper, we have presented a novel approach of calculating eigenvalues of any matrix for the first time on Field Programmable Gate Array (FPGA) using Triangular Systolic Arra (TSA) architecture. Conventionally, additional computation unit is required in the architecture which is compliant to the algorithm for determining the eigenvalues and this in return enhances the delay and power consumption. However, recently reported works are only dedicated for symmetric matrices or some specific case of matrix. This works presents an architecture to calculate eigenvalues of any matrix based on QR algorithm which is fully implementable on FPGA. For the implementation of QR algorithm we have used TSA architecture, which is further utilising CORDIC (CO-ordinate Rotation DIgital Computer) algorithm, to calculate various trigonometric and arithmetic functions involved in the procedure. The proposed architecture gives an error in the range of 10−4. Power consumption by the design is 0.598W. It can work at the frequency of 900 MHz.

Keywords: coordinate rotation digital computer, three angle complex rotation, triangular systolic array, QR algorithm

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Authors: Megha Chavda, Parth Thummar, Rahul Ghetia

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This paper presents the voltage and current control of microgrid accompanied by the synchronization of microgrid with the main utility grid in both islanded and grid-connected modes. Distributed Energy Resources (DERs) satisfy the wide-spread power demand of consumer by behaving as a micro source for a low voltage (LV) grid or microgrid. Synchronization of the microgrid with the main utility grid is done using PLL and PWM gate pulse generation technique is used for the Voltage Source Converter. Potential Function method achieves the voltage and current control of this microgrid in both islanded and grid-connected modes. A low voltage grid consisting of three distributed generators (DG) is considered for the study and is simulated in time-domain using PSCAD/EMTDC software. The simulation results depict the appropriateness of voltage and current control of microgrid and synchronization of microgrid with the medium voltage (MV) grid.

Keywords: microgrid, distributed energy resources, voltage and current control, voltage source converter, pulse width modulation, phase locked loop

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Authors: Olukunle C. Olawole, Dilip K. De, Moses Emetere, Omoje Maxwell

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Graphene can stand very high temperature up to 4500 K in vacuum and has potential for application in thermionic energy converter. In this paper, we discuss the application of energy dynamics principles and the modified Richardson-Dushman Equation, to estimate the efficiency of solar power conversion to electrical power by a solar thermionic energy converter (STEC) containing emitter made of graphene. We present detailed simulation of power output for different solar insolation, diameter of parabolic concentrator, area of the graphene emitter (same as that of the collector), temperature of the collector, physical dimensions of the emitter-collector etc. After discussing possible methods of reduction or elimination of space charge problem using magnetic field and gate, we finally discuss relative advantages of using emitters made of graphene, carbon nanotube and metals respectively in a STEC.

Keywords: graphene, high temperature, modified Richardson-Dushman equation, solar thermionic energy converter

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Authors: Nithiya C., Komathi B. J., Praveena N. G., Samuda Prathima

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At present, the ultimate aim in digital system designs, especially at the gate level and lower levels of design abstraction, is power optimization. Adders are a nearly universal component of today's integrated circuits. Most of the research was on the design of high-speed adders to execute addition based on various adder structures. This paper discusses the ideal path for selecting an arithmetic unit for IoT applications. Based on the analysis of eight types of 16-bit adders, we found out Carry Look-ahead (CLA) produces low power. Additionally, multiplier and accumulator (MAC) unit is implemented with the Booth multiplier by using the low power adders in the order of preference. The design is synthesized and verified using Synopsys Design Compiler and VCS. Then it is implemented by using Cadence Encounter. The total power consumed by the CLA based booth multiplier is 0.03527mW, the total area occupied is 11260 um², and the speed is 2034 ps.

Keywords: carry look-ahead, carry select adder, CSA, internet of things, ripple carry adder, design rule check, power delay product, multiplier and accumulator

Procedia PDF Downloads 118

Authors: K. Assis, K. P. Chong, A. S. Idris, C. M. Ho

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Oil palm or Elaeis guineensis is considered as the golden crop in Malaysia. But oil palm industry in this country is now facing with the most devastating disease called as Ganoderma Basal Stem Rot disease. The objective of this paper is to analyze the economic loss due to this disease. There were three commercial oil palm sites selected for collecting the required data for economic analysis. Yield parameter used to measure the loss was the total weight of fresh fruit bunch in six months. The predictors include disease severity, change in disease severity, number of infected neighbor palms, age of palm, planting generation, topography, and first order interaction variables. The estimation model of yield loss was identified by using backward elimination based regression method. Diagnostic checking was conducted on the residual of the best yield loss model. The value of mean absolute percentage error (MAPE) was used to measure the forecast performance of the model. The best yield loss model was then used to estimate the economic loss by using the current monthly price of fresh fruit bunch at mill gate.

Keywords: ganoderma, oil palm, regression model, yield loss, economic loss

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Authors: Pooja S. Billade, Sanjay S. Chopade

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This paper focuses on the design of three phase induction motor control using single phase input and GSM.The controller used in this work is a wireless speed control using a GSM technique that proves to be very efficient and reliable in applications.The most common principle is the constant V/Hz principle which requires that the magnitude and frequency of the voltage applied to the stator of a motor maintain a constant ratio. By doing this, the magnitude of the magnetic field in the stator is kept at an approximately constant level throughout the operating range. Thus, maximum constant torque producing capability is maintained. The energy that a switching power converter delivers to a motor is controlled by Pulse Width Modulated signals applied to the gates of the power transistors in H-bridge configuration. PWM signals are pulse trains with fixed frequency and magnitude and variable pulse width. When a PWM signal is applied to the gate of a power transistor, it causes the turn on and turns off intervals of the transistor to change from one PWM period.

Keywords: index terms— PIC, GSM (global system for mobile), LCD (Liquid Crystal Display), IM (Induction Motor)

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Authors: Gizem Kodak

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The Strait of Çanakkale, together with the Strait of Istanbul and the Sea of Marmara, form the Turkish Straits System. In other words, the Strait of Çanakkale is the southern gate of the system that connects the Black Sea countries with the other countries of the world. Due to the heavy maritime traffic, it is important to scientifically examine the accident characteristics in the region. In particular, the results indicated by the descriptive statistics are of critical importance in order to strengthen the safety of navigation. At this point, exploratory data analysis offers strategic outputs in terms of defining the problem and knowing the strengths and weaknesses against possible accident risk. The study aims to determine the accident characteristics in the Strait of Çanakkale with temporal and spatial analysis of historical data, using Exploratory Data Analysis (EDA) as the research method. The study's results will reveal the general characteristics of maritime accidents in the region and form the infrastructure for future studies. Therefore, the text provides a clear description of the research goals and methodology, and the study's contributions are well-defined.

Keywords: maritime accidents, EDA, Strait of Çanakkale, navigational safety

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Authors: Mahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Henk Corporaal

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Recently, Statistic Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in aeronautics and space systems where high dependability is demanded and considered as a mandatory requirement. Since design’s circuit is stored in configuration memory in SRAM-based FPGAs; they are very sensitive to Single Event Upsets (SEUs). In addition, the adverse effects of SEUs on the electronics used in space are much higher than in the Earth. Thus, developing fault tolerant techniques play crucial roles for the use of SRAM-based FPGAs in space. However, fault tolerance techniques introduce additional penalties in system parameters, e.g., area, power, performance and design time. In this paper, an accurate estimation of configuration memory vulnerability to SEUs is proposed for approximate-tolerant applications. This vulnerability estimation is highly required for compromising between the overhead introduced by fault tolerance techniques and system robustness. In this paper, we study applications in which the exact final output value is not necessarily always a concern meaning that some of the SEU-induced changes in output values are negligible. We therefore define and propose Approximate-based Configuration Memory Vulnerability Factor (ACMVF) estimation to avoid overestimating configuration memory vulnerability to SEUs. In this paper, we assess the vulnerability of configuration memory by injecting SEUs in configuration memory bits and comparing the output values of a given circuit in presence of SEUs with expected correct output. In spite of conventional vulnerability factor calculation methods, which accounts any deviations from the expected value as failures, in our proposed method a threshold margin is considered depending on user-case applications. Given the proposed threshold margin in our model, a failure occurs only when the difference between the erroneous output value and the expected output value is more than this margin. The ACMVF is subsequently calculated by acquiring the ratio of failures with respect to the total number of SEU injections. In our paper, a test-bench for emulating SEUs and calculating ACMVF is implemented on Zynq-7000 FPGA platform. This system makes use of the Single Event Mitigation (SEM) IP core to inject SEUs into configuration memory bits of the target design implemented in Zynq-7000 FPGA. Experimental results for 32-bit adder show that, when 1% to 10% deviation from correct output is considered, the counted failures number is reduced 41% to 59% compared with the failures number counted by conventional vulnerability factor calculation. It means that estimation accuracy of the configuration memory vulnerability to SEUs is improved up to 58% in the case that 10% deviation is acceptable in output results. Note that less than 10% deviation in addition result is reasonably tolerable for many applications in approximate computing domain such as Convolutional Neural Network (CNN).

Keywords: fault tolerance, FPGA, single event upset, approximate computing

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Authors: Josue Javier Martinez Flores, Jaime Alvarez Quintana

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A thermal rectifier consists of a device which can load a different heat flow which depends on the direction of that flow. That device is a thermal diode. It is well known that heat transfer in solids basically depends on the electrical, magnetic and crystalline nature of materials via electrons, magnons and phonons as thermal energy carriers respectively. In the present research, we have synthesized polycrystalline Ni-Cu alloys and identified the Curie temperatures; and we have observed that by way of secondary phase transitions, it is possible manipulate the heat conduction in solid state thermal diodes via transition temperature. In this sense, we have succeeded in developing solid state thermal diodes with a control gate through the Curie temperature via the activation and deactivation of magnons in Ni-Cu ferromagnetic alloys at room temperature. Results show thermal diodes with thermal rectification factors up to 1.5. Besides, the performance of the electrical rectifiers can be controlled by way of alloy Cu content; hence, lower Cu content alloys present enhanced thermal rectifications factors than higher ones.

Keywords: thermal rectification, Curie temperature, ferromagnetic alloys, magnons

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Authors: Ali Ramezani

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Balancing feeding system of plastic injection molding has overriding importance as it minimizes the process’s product defects such as weld line, shrinkage, sink marks and warpage. This article presents the difference between optimization of feeding system in identical multi-cavity molding and family molding using Moldflow Plastic Insight software. In this work, the effect of dimension, shape, position and type of gates and runners on the products quality was studied. The optimization was carried out by analyzing plastic injection molding process parameters, including melt temperature, mold temperature, cooling time, cooling temperature packing time and packing pressure. It was found that symmetrical feeding system is the most efficient shape for diminishing defects in identical multi-cavity molding. However, the same results were not concluded for family molding due to the differences between volume, mass, thickness and shape of cavities.

Keywords: balancing feeding system, family molding, multi-cavity, Moldflow, plastic injection

Procedia PDF Downloads 135

Authors: Abdelmadjid Mammeri, Fatima Zohra Mahi, Luca Varani, H. Marinchoi

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We propose an analytical model for the admittance and the noise calculations of the InGaAs transistor and diode. The development of the small-signal admittance takes into account the longitudinal and transverse electric fields through a pseudo two-dimensional approximation of the Poisson equation. The frequency-dependent of the small-signal admittance response is determined by the total currents and the potentials matrix relation between the gate and the drain terminals. The noise is evaluated by using the real part of the transistor/diode admittance under a small-signal perturbation. The analytical results show that the admittance spectrum exhibits a series of resonant peaks corresponding to the excitation of plasma waves. The appearance of the resonance is discussed and analyzed as functions of the channel length and the temperature. The model can be used, on one hand; to control the appearance of the plasma resonances, and on other hand; can give significant information about the noise frequency dependence in the InGaAs transistor and diode.

Keywords: InGaAs transistors, InGaAs diode, admittance, resonant peaks, plasma waves, analytical model

Procedia PDF Downloads 316

Authors: Loreine Makki, Marc Anthony Mannah, Christophe Batard, Nicolas Ginot, Julien Weckbrodt

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Planar transformers are extensively utilized in high-frequency, high power density power electronic converters. The breakthrough of wide-bandgap technology compelled power electronic system miniaturization while inducing pivotal effects on system modeling and manufacturing within the power electronics industry. A significant consideration to simulate and model the unanticipated parasitic parameters emerges with the requirement to mitigate electromagnetic disturbances. This paper will present an equivalent circuit model of a shielded pulse planar transformer quantifying leakage inductance and resistance in addition to the interwinding capacitance of the primary and secondary windings. ANSYS Q3D Extractor was utilized to model and simulate the transformer, intending to study the immunity of the simulated equivalent model to high dv/dt occurrences. A convenient correlation between simulation and experimental results is presented.

Keywords: Planar transformers, wide-band gap, equivalent circuit model, shielded, ANSYS Q3D Extractor, dv/dt

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Authors: Khuram Shahzad, Omar Usman Khan

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Quantum bit string comparators (QBSC) operate on two sequences of n-qubits, enabling the determination of their relationships, such as equality, greater than, or less than. This is analogous to the way conditional statements are used in programming languages. Consequently, QBSCs play a crucial role in various algorithms that can be executed or adapted for quantum computers. The development of efficient and generalized comparators for any n-qubit length has long posed a challenge, as they have a high-cost footprint and lead to quantum delays. Comparators that are efficient are associated with inputs of fixed length. As a result, comparators without a generalized circuit cannot be employed at a higher level, though they are well-suited for problems with limited size requirements. In this paper, we introduce a generalized design for the comparison of two n-qubit logic states using just two ancillary bits. The design is examined on the basis of qubit requirements, ancillary bit usage, quantum cost, quantum delay, gate operations, and circuit complexity and is tested comprehensively on various input lengths. The work allows for sufficient flexibility in the design of quantum algorithms, which can accelerate quantum algorithm development.

Keywords: quantum comparator, quantum algorithm, space-efficient comparator, comparator

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Authors: G. Rajeshwari, V. D. M. Jabez Daniel

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Radio Frequency Identification systems are used for automated identification in various applications such as automobiles, health care and security. It is also called as the automated data collection technology. RFID readers are placed in any area to scan large number of tags to cover a wide distance. The placement of the RFID elements may result in several types of collisions. A major challenge in RFID system is collision avoidance. In the previous works the collision was avoided by using algorithms such as ALOHA and tree algorithm. This work proposes collision reduction and increased throughput through reading enhancement method with tree algorithm. The reading enhancement is done by improving interrogation procedure and increasing the data handling capacity of RFID reader with parallel processing. The work is simulated using Xilinx ISE 14.5 verilog language. By implementing this in the RFID system, we can able to achieve high throughput and avoid collision in the reader at a same instant of time. The overall system efficiency will be increased by implementing this.

Keywords: antenna, anti-collision protocols, data management system, reader, reading enhancement, tag

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Authors: Roseminu Varghese, Laveena Anitha Barboza, Jyothi Chakrabarty, Ravishankar

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Depression among post-stroke survivors is prevalent, but it is unidentified. The purpose of this review was to determine the pooled prevalence of depression among post-stroke survivors in the South Asian region from all published health sciences research articles. The review also aimed to analyze the disparities in the prevalence of depression among the post-stroke survivors from different study locations. Data search to identify the relevant research articles published from 2005 to 2016 was done by using mesh terms and keywords in Web of Science, PubMed Medline, CINAHL, Scopus, J gate, IndMED databases. The final analysis comprised of 9 studies, including a population of 1,520 men and women. Meta-analysis was performed in STATA version 13.0. The overall pooled post-stroke depression prevalence was 0.46, 95% (CI), (0.3- 0.62). The prevalence rate in this systematic review is evident of depression among post-stroke survivors in the South Asian Region. Identifying the prevalence of post-stroke depression at an early stage is important to improve outcomes of the rehabilitative process of stroke survivors and for its early intervention.

Keywords: depression, post stroke survivors, prevalence, systematic review

Procedia PDF Downloads 158

Authors: Ebrahim H. Kapeel, Ehab Safwat, Hossam Hendy, Ahmed M. Kamel, Yehia Z. Elhalwagy

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Motivated by the problem of the availability of high-fidelity flight simulation models for small unmanned aerial vehicles (UAVs). This paper focuses on the geometric-mass inertia modeling and the actuation system modeling for the small fixed-wing UAVs. The UAV geometric parameters for the body, wing, horizontal and vertical tail are physically measured. Pendulum experiment with high-grade sensors and data analysis using MATLAB is used to estimate the airplane moment of inertia (MOI) model. Finally, UAV’s actuation system is modeled by estimating each servo transfer function by using the system identification, which uses experimental measurement for input and output angles through using field-programmable gate array (FPGA). Experimental results for the designed models are given to illustrate the effectiveness of the methodology. It also gives a very promising result to finalize the open-loop flight simulation model through modeling the propulsion system and the aerodynamic system.

Keywords: unmanned aerial vehicle, geometric-mass inertia model, system identification, Simulink

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Authors: Ratchaneewan Maneemaroj, Paveena Noisuwan, Chonlada Lakhonphon

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The smoking is one of the major risk factors in Non-Communicable Disease. Free radicals from cigarette smoke can cause oxidative stress. The oxidative insults can lead to red blood cell (RBC) senescence and are involved in the clearance of red blood cells. The objective of the present study is to assess the association between smoke, oxidative stress evaluated with serum Malondialdehyde (MDA) level and phosphatidylserine (PS) externalization (biomarker of RBC senescence) evaluated with annexin V binding. A total of sixty-four male volunteers aged 25-60 years old were recruited in this study. MDA was measured by colorimetric method. Annexin V binding was detected by flow cytometry. Our results show that there was a significant increase in MDA levels in cigarette smokers as compared to non-smokers (p < 0.001). However, there was no significant different between annexin V binding (% gate) in cigarette smokers and non-smokers (p = 0.978). These results provide evidence of free radical from smoking is associated with oxidative damage to erythrocytes. However, our results suggest that PS externalization is unlikely to have a role in RBC senescence pathway of stressed erythrocytes from cigarette smoke. The other biomarker of RBC senescence should be determined on cigarette smoker erythrocytes.

Keywords: malondialdehyde, phosphatidylserine, RBC senescence, annexin V

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

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In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: frequency measurement, digital control, phase locked loop, encoder, Verilog HDL

Procedia PDF Downloads 178

Authors: Bentoutou Houari, Boutte Aissa, Belaidi El Yazid, Limam Lakhdar

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The integration of a load switch with a DC/DC buck converter using LM2596 for power distribution in low-cost educational nanosatellites is a technique that aims to efficiently manage the power distribution system in these small spacecraft. The converter is based on the LM2596 regulator and designed to step down the input voltage of +16.8V to +12V, +5V, and +3.3V output, which are suitable for the nanosatellite's various subsystems. The load switch is based on MOSFET and is used to turn on or off the power supply to a particular load and protect the nanosatellite from power surges. A prototype of a +12V DC/DC buck converter with a high side load switch has been realized and tested, which meets our requirements and shows a good efficiency of 89%. In addition, the prototype features a capacitor between the source and gate of the MOSFET, which has effectively reduced the inrush current, demonstrating the effectiveness of this approach in reducing surges of current when the load is connected. The output current and voltage were measured at 0.7A and 11.89V, respectively, making this design suitable for use in low-cost educational nanosatellites.

Keywords: DC/DC buck converter, load switch, LM2596, electrical power subsystems, nanosatellite, inrush current

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Authors: Edemealem Desalegn Kingawa, Kafte Tasew Timkete, Mekashaw Girmaw Abebe, Terefe Feyisa, Abiyot Bitew Mihretie, Senait Teklemarkos Haile

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Currently, hate speech is a growing challenge for society, individuals, policymakers, and researchers, as social media platforms make it easy to anonymously create and grow online friends and followers and provide an online forum for debate about specific issues of community life, culture, politics, and others. Despite this, research on identifying and detecting hate speech is not satisfactory performance, and this is why future research on this issue is constantly called for. This paper provides a systematic review of the literature in this field, with a focus on approaches like word embedding techniques, machine learning, deep learning technologies, hate speech terminology, and other state-of-the-art technologies with challenges. In this paper, we have made a systematic review of the last six years of literature from Research Gate and Google Scholar. Furthermore, limitations, along with algorithm selection and use challenges, data collection, and cleaning challenges, and future research directions, are discussed in detail.

Keywords: Amharic hate speech, deep learning approach, hate speech detection review, Afaan Oromo hate speech detection

Procedia PDF Downloads 177

Authors: Seyed Abbas Tabatabaei, Marjan Naderan Tahan, Arman Kadkhodai

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An efficient optimization approach, called feasible gate (FG), is developed to enhance the computation efficiency and solution quality of the previously developed highway alignment optimization (HAO) model. This approach seeks to realistically represent various user preferences and environmentally sensitive areas and consider them along with geometric design constraints in the optimization process. This is done by avoiding the generation of infeasible solutions that violate various constraints and thus focusing the search on the feasible solutions. The proposed method is simple, but improves significantly the model’s computation time and solution quality. On the other, highway alignment optimization through Feasible Gates, eventuates only economic model by considering minimum design constrains includes minimum reduce of circular curves, minimum length of vertical curves and road maximum gradient. This modelling can reduce passenger comfort and road safety. In most of highway optimization models, by adding penalty function for each constraint, final result handles to satisfy minimum constraint. In this paper, we want to propose a safety-function solution by introducing gift function.

Keywords: safety, highway geometry, optimization, alignment

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Authors: M. Iruleswari, A. Jeyapaul Murugan

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Most fundamental part used in many Digital Signal Processing (DSP) application is a Finite Impulse Response (FIR) filter because of its linear phase, stability and regular structure. Designing a high-speed and hardware efficient FIR filter is a very challenging task as the complexity increases with the filter order. In most applications the higher order filters are required but the memory usage of the filter increases exponentially with the order of the filter. Using multipliers occupy a large chip area and need high computation time. Multiplier-less memory-based techniques have gained popularity over past two decades due to their high throughput processing capability and reduced dynamic power consumption. This paper describes the design and implementation of highly efficient Look-Up Table (LUT) based circuit for the implementation of FIR filter using Distributed arithmetic algorithm. It is a multiplier less FIR filter. The LUT can be subdivided into a number of LUT to reduce the memory usage of the LUT for higher order filter. Analysis on the performance of various filter orders with different address length is done using Xilinx 14.5 synthesis tool. The proposed design provides less latency, less memory usage and high throughput.

Keywords: finite impulse response, distributed arithmetic, field programmable gate array, look-up table

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Authors: Sarah M. Schoellhammer, Stephen Gibb

Abstract:

Bureaucracy, in particular, its core element, a formal and stable hierarchy of authority, is proving less and less appropriate under the conditions of today’s knowledge economy. Centralization and formalization were consistently found to hinder innovation, undermining cross-functional collaboration, personal responsibility, and flexibility. With its focus on systematical planning, controlling and monitoring the development of new or improved solutions for customers, even innovation management as a discipline is to a significant extent based on a mechanistic understanding of organizations. The most important drivers of innovation, human creativity, and initiative, however, can be more hindered than supported by central elements of classic innovation management, such as predefined innovation strategies, rigid stage gate processes, and decisions made in management gate meetings. Heterarchy, as an alternative network form of organization, is essentially characterized by its dynamic influence structures, whereby the biggest influence is allocated by the collective to the persons perceived the most competent in a certain issue. Theoretical arguments that the non-hierarchical concept better supports innovation than bureaucracy have been supported by empirical research. These prior studies either focus on the structure and general functioning of non-hierarchical organizations or on their innovativeness, that means innovation as an outcome. Complementing classic innovation management approaches, this work aims to shed light on how innovations are initiated and realized in heterarchies in order to identify alternative solutions practiced under conditions of the post-bureaucratic organization. Through an initial individual case study, which is part of a multiple-case project, the innovation practices of an innovative and highly heterarchical medium-sized company in the German fire engineering industry are investigated. In a pragmatic mixed methods approach media resonance, company documents, and workspace architecture are analyzed, in addition to qualitative interviews with the CEO and employees of the case company, as well as a quantitative survey aiming to characterize the company along five scaled dimensions of a heterarchy spectrum. The analysis reveals some similarities and striking differences to approaches suggested by classic innovation management. The studied heterarchy has no predefined innovation strategy guiding new product and service development. Instead, strategic direction is provided by the CEO, described as visionary and creative. Procedures for innovation are hardly formalized, with new product ideas being evaluated on the basis of gut feeling and flexible, rather general criteria. Employees still being hesitant to take responsibility and make decisions, hierarchical influence is still prominent. Described as open-minded and collaborative, culture and leadership were found largely congruent with definitions of innovation culture. Overall, innovation efforts at the case company tend to be coordinated more through cultural than through formal organizational mechanisms. To better enable innovation in mainstream organizations, responsible practitioners are recommended not to limit changes to reducing the central elements of the bureaucratic organization, formalization, and centralization. The freedoms this entails need to be sustained through cultural coordination mechanisms, with personal initiative and responsibility by employees as well as common innovation-supportive norms and values. These allow to integrate diverse competencies, opinions, and activities and, thus, to guide innovation efforts.

Keywords: bureaucracy, heterarchy, innovation management, values

Procedia PDF Downloads 187

Authors: Lin Gong, Holger Göbel

Abstract:

In the present study, we have investigated the influence of UV/ozone treatment on pentacene-based organic field effect transistors (OFETs) with a bilayer gate dielectric. The OFETs for this study were fabricated on heavily n-doped Si substrates with a thermally deposited SiO2 dielectric layer (300nm). On the SiO2 dielectric a very thin (≈ 15nm) buffer layer of polystyrene (PS) was first spin-coated and then treated by UV/ozone to modify the surface prior to the deposition of pentacene. We found out that by extending the UV/ozone treatment time the threshold voltage of the OFETs was monotonically shifted towards positive values, whereas the field effect mobility first decreased but eventually reached a stable value after a treatment time of approximately thirty seconds. Since the field effect mobility of the UV/ozone treated bilayer OFETs was found to be higher than the value of a comparable transistor with a single layer dielectric, we propose that the bilayer (SiO2/PS) structure can be used to shift the threshold voltage to a desired value without sacrificing field effect mobility.

Keywords: buffer layer, organic field effect transistors, threshold voltage, UV/ozone treatment

Procedia PDF Downloads 337