Search results for: integrator circuits

Authors: Nahla Elazab, Mohamed Aboudina, Ghada Ibrahim, Hossam Fahmy, Ahmed Khalil

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This paper presents the developed memristor based demodulators for eight circular Quadrature Amplitude Modulation (QAM) and Binary Frequency Shift Keying (BFSK) operating at relatively high frequency. In our implementations, the experimental-based ‘nonlinear’ dopant drift model is adopted along with the proposed circuits providing incorporation of all known non-idealities of practically realized memristor and gaining high operation frequency. The suggested designs leverage the distinctive characteristics of the memristor device, definitely, its changeable average memristance versus the frequency, phase and amplitude of the periodic excitation input. The proposed demodulators feature small integration area, low power consumption, and easy implementation. Moreover, the proposed QAM demodulator precludes the requirement for the carrier recovery circuits. In doing so, the designs were validated by transient simulations using the nonlinear dopant drift memristor model. The simulations results show high agreement with the theory presented.

Keywords: BFSK, demodulator, high frequency memristor applications, memristor based analog circuits, nonlinear dopant drift model, QAM

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Authors: Suleiman Babani, Jazuli Sanusi Kazaure

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In this paper, two coupled-line couplers are designed and simulated using stripline technology. The coupled-line couplers (A and B) are designed with different values of coupling coefficient 6dB and 10dB respectively. Both of circuits have a coupled output port, a through output port and an isolated output port. Moreover, both circuits are tuned to function around 2.45 GHz. The design results are presented by simulation results obtained using ADS 2012.08 (Advanced Design System) software.

Keywords: ADS, coupled-line coupler, directional coupler, stripline

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Authors: Patikineti Sreenivasulu, K. srinivasa Rao, A. Vinaya Babu

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The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits.

Keywords: power consumption, ultra-low power, leakage, sub threshold, MTCMOS

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Authors: Eszter Hamza

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The competitiveness of economic operators is based on interoperability, which is relatively low in Hungary. The development of co-operation is high priority in Common Agricultural Policy 2014-2020. The aim of the paper to assess co-operations in Hungarian agriculture, estimate the economic outputs and benefits of co-operations, based on statistical data processing and literature. Further objective is to explore the potential of agricultural co-operation with the help of interviews and questionnaire survey. The research seeks to answer questions as to what fundamental factors play role in the development of co-operation, and what are the motivations of the actors and the key success factors and pitfalls. The results were analysed using econometric methods. In Hungarian agriculture we can find several forms of co-operation: cooperatives, producer groups (PG) and producer organizations (PO), machinery cooperatives, integrator companies, product boards and interbranch organisations. Despite the several appearance of the agricultural co-operation, their economic weight is significantly lower in Hungary than in western European countries. Considering the agricultural importance, the integrator companies represent the most weight among the co-operations forms. Hungarian farmers linked to co-operations or organizations mostly in relation to procurement and sales. Less than 30 percent of surveyed farmers are members of a producer organization or cooperative. The trust level is low among farmers. The main obstacle to the development of formalized co-operation, is producers' risk aversion and the black economy in agriculture. Producers often prefer informal co-operation instead of long-term contractual relationships. The Hungarian agricultural co-operations are characterized by non-dynamic development, but slow qualitative change. For the future, one breakout point could be the association of producer groups and organizations, which in addition to the benefits of market concentration, in the dissemination of knowledge, advisory network operation and innovation can act more effectively.

Keywords: agriculture, co-operation, producer organisation, trust level

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Authors: Jun-Geol Park, Kyoung-Il Do, Min-Ju Kwon, Kyung-Hyun Park, Yong-Seo Koo

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This paper analyzed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuits with the turn-on time characteristics. The structures are the LVTSCR (Low Voltage Triggered SCR), the ZTSCR (Zener Triggered SCR) and the PTSCR (P-Substrate Triggered SCR). The three structures are for the 5V power clamp. In general, the structures with the low trigger voltage structure can have the fast turn-on characteristics than other structures. All the ESD protection circuits have the low trigger voltage by using the N+ bridge region of LVTSCR, by using the zener diode structure of ZTSCR, by increasing the trigger current of PTSCR. The simulation for the comparison with the turn-on time was conducted by the Synopsys TCAD simulator. As the simulation results, the LVTSCR has the turn-on time of 2.8 ns, ZTSCR of 2.1 ns and the PTSCR of 2.4 ns. The HBM simulation results, however, show that the PTSCR is the more robust structure of 430K in HBM 8kV standard than 450K of LVTSCR and 495K of ZTSCR. Therefore the PTSCR is the most effective ESD protection circuit for the 5V power clamp.

Keywords: ESD, SCR, turn-on time, trigger voltage, power clamp

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Authors: Sangguk Ahn, Youngyu Kim, Jaheon Gu, Gyoutae Park

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In this paper, we developed a dual gas leak instrument to detect Hydrocarbon (HC) and Monoxide (CO) gases. To two kinds of gases, it is necessary to design compact structure for sensors. And then it is important to draw sensing circuits such as measuring, amplifying and filtering. After that, it should be well programmed with robust, systematic and module coding methods. In center of them, improvement of accuracy and initial response time are a matter of vital importance. To manufacture distinguished gas leak detector, we applied intrinsically safe explosion-proof structure to lithium ion battery, main circuits, a pump with motor, color LCD interfaces and sensing circuits. On software, to enhance measuring accuracy we used numerical analysis such as Lagrange and Neville interpolation. Performance test result is conducted by using standard Methane with seven different concentrations with three other products. We want raise risk prevention and efficiency of gas safe management through distributing to the field of gas safety. Acknowledgment: This study was supported by Small and Medium Business Administration under the research theme of ‘Commercialized Development of a portable intrinsically safe explosion-proof type dual gas leak detector’, (task number S2456036).

Keywords: gas leak, dual gas detector, intrinsically safe, explosion proof

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Authors: Biswarup Mukherjee, Aniruddha Ghosal

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In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub components. The explored method of implementation achieves a low power design for the full adder. Simulated results using state-of-art Tanner tool indicates the superior performance of the proposed technique over conventional CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: low power full adder, 2-T GDI MUX, ASIC (application specific integrated circuit), 12-T FA, CMOS (complementary metal oxide semiconductor)

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Authors: Fawzia Al-Sakeer, Hassan Aldeeb

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Development in the communications field is proceeding at an amazing speed, which has led researchers to improve and develop electronic circuits by increasing their efficiency and reducing their size to reduce the weight of electronic devices. One of the most important of these circuits is the band-pass filter, which is what made us carry out this research, which aims to use an alternate technology to design a dual band-pass filter by using a stepped impedance microstrip transmission line. We designed a filter that works at two center frequency bands by designing with the ADS program, and the results were excellent, as we obtained the two design frequencies, which are 1 and 3GHz, and the values of insertion loss S11, which was more than 21dB with a small area.

Keywords: band pass filter, dual band band-pass filter, ADS, microstrip filter, stepped impedance

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Authors: Mohamed Mahmoud

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This paper has developed an effect-cause analysis technique for fault diagnosis in digital circuits. The main algorithm of our technique is based on the Enhanced Deduction Algorithm, which processes the real response of the CUT to the applied test T to deduce the values of the internal lines. An experimental version of the algorithm has been implemented in C++. The code takes about 7592 lines. The internal values are determined based on the logic values under the permanent stuck-fault model. Using a backtracking strategy guarantees that the actual values are covered by at least one solution, or no solution is found.

Keywords: enhanced deduction algorithm, backtracking strategy, automatic test equipment, verfication

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Authors: K. Shaji Mon, P. R. John Sreenidhi

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In deep-submicrometer CMOS processes, time-domain resolution of a digital signal is becoming higher than voltage resolution of analog signals. This claim is nowadays pushing toward a new circuit design paradigm in which the traditional analog signal processing is expected to be progressively substituted by the processing of times in the digital domain. Within this novel paradigm, digitally controlled delay lines (DCDL) should play the role of digital-to-analog converters in traditional, analog-intensive, circuits. Digital delay locked loops are highly prevalent in integrated systems.The proposed paper addresses the glitches present in delay circuits along with area,power dissipation and signal integrity.The digitally controlled delay lines(DCDL) under study have been designed in a 90 nm CMOS technology 6 layer metal Copper Strained SiGe Low K Dielectric. Simulation and synthesis results show that the novel circuits exhibit no glitches for dual output coarse DCDL with less power dissipation and consumes less area compared to the glitch free NAND based DCDL.

Keywords: glitch free, NAND-based DCDL, CMOS, deep-submicrometer

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Authors: Jerome G. Chandraseelan, Samuel M. D. Oliveira, Antti Häkkinen, Sofia Startceva, Andre S. Ribeiro

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We used live E. coli containing synthetic genetic oscillators to study how the degree of synchrony between the genetic circuits of sister cells changes with temperature. We found that both the mean and the variability of the degree of synchrony between the fluorescence signals from sister cells are affected by temperature. Also, while most pairs of sister cells were found to be highly synchronous in each condition, the number of asynchronous pairs increased with increasing temperature, which was found to be due to disruptions in the oscillations. Finally we provide evidence that these disruptions tend to affect multiple generations as opposed to individual cells. These findings provide insight in how to design more robust synthetic circuits and in how cell division can affect their dynamics.

Keywords: repressilator, robustness, synchrony, synthetic biology

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Authors: Abdeljalil Metioui

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The purpose of this article is to present the results of two-stage qualitative research. The first involved the identification of the alternative conceptions of 80 elementary pre-service teachers from Quebec in Canada about the operation of simple electrical circuits. To do this, they completed a two-choice questionnaire (true or false) with justification. Data analysis identifies many conceptual difficulties. For example, for their majority, whatever the electrical device that composes an electrical circuit, the current source (power supply), and the generated electrical power is constant. The second step was to develop a double multiple-choice questionnaire based on the identified designs. It allows teachers to quickly diagnose their students' conceptions and take them into account in their teaching.

Keywords: development, electrical circuits, two-tier diagnostic test, secondary and high school

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Authors: Chin-Yun Chen

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Numerical integration is an essential tool for deriving different physical quantities in engineering and science. The effectiveness of a numerical integrator depends on different factors, where the crucial one is the error estimation. This work presents an error estimator that combines a derivative free method to improve the performance of verified numerical quadrature.

Keywords: numerical quadrature, error estimation, derivative free method, interval computation

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Authors: Biswarup Mukherjee, Aniruddha Ghoshal

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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

Keywords: high speed low power full adder, 2-T MUX, 3-T XOR, 8-T FA, pass transistor logic, CMOS (complementary metal oxide semiconductor)

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Authors: M. A. Grigoryev, A. N. Shishkov, D. A. Sychev

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The article defines the necessity of choosing the optimal power circuits scheme of the electric drive with field regulated reluctance machine. The specific weighting factors are calculation, the linear regression dependence of specific losses in semiconductor frequency converters are presented depending on the values of the rated current. It is revealed that with increase of the carrier frequency PWM improves the output current waveform, but increases the loss, so you will need depending on the task in a certain way to choose from the carrier frequency. For task of optimization by criterion of the minimum electrical losses regression dependence of the electrical losses in the frequency converter circuit at a frequency of a PWM signal of 0 Hz. The surface optimization criterion is presented depending on the rated output torque of the motor and number of phases. In electric drives with field regulated reluctance machine with at low output power optimization criterion appears to be the worst for multiphase circuits. With increasing output power this trend hold true, but becomes insignificantly different optimal solutions for three-phase and multiphase circuits. This is explained to the linearity of the dependence of the electrical losses from the current.

Keywords: field regulated reluctance machine, the electrical losses, multiphase power circuit, the surface optimization criterion

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Authors: Kwan-Ho Kim, Jin-Hong Park

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The multi-valued logic (MVL) circuits, which can handle more than two logic states, are one of the promising solutions to overcome the bit density limitations of conventional binary logic systems. Recently, tunneling devices such as Esaki diode and resonant tunneling diode (RTD) have been extensively explored to construct the MVL circuits. These tunneling devices present a negative differential resistance (NDR) phenomenon in which a current decreases as a voltage increases in a specific applied voltage region. Due to this non-monotonic current behavior, the tunneling devices have more than two threshold voltages, consequently enabling construction of MVL circuits. Recently, the emergence of two dimensional (2D) van der Waals (vdW) crystals has opened up the possibility to fabricate such tunneling devices easily. Owing to the defect-free surface of the 2D crystals, a very abrupt junction interface could be formed through a simple stacking process, which subsequently allowed the implementation of a high-performance tunneling device. Here, we report a vdW heterostructure based tunneling device with multiple threshold voltages, which was fabricated with black phosphorus (BP) and hafnium diselenide (HfSe₂). First, we exfoliated BP on the SiO₂ substrate and then transferred HfSe₂ on BP using dry transfer method. The BP and HfSe₂ form type-Ⅲ heterojunction so that the highly doped n+/p+ interface can be easily implemented without additional electrical or chemical doping process. Owing to high natural doping at the junction, record high peak to valley ratio (PVCR) of 16 was observed to the best our knowledge in 2D materials based NDR device. Furthermore, based on this, we first demonstrate the feasibility of the ternary latch by connecting two multi-threshold voltage devices in series.

Keywords: two dimensional van der Waals crystal, multi-valued logic, negative differential resistnace, tunneling device

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Authors: Iman Farasat, Howard M. Salis

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Engineered genetic circuits reprogram cellular behavior to act as living computers with applications in detecting cancer, creating self-controlling artificial tissues, and dynamically regulating metabolic pathways. Phenemenological models are often used to simulate and design genetic circuit behavior towards a desired behavior. While such models assume that each circuit component’s function is modular and independent, even small changes in a circuit (e.g. a new promoter, a change in transcription factor expression level, or even a new media) can have significant effects on the circuit’s function. Here, we use statistical thermodynamics to account for the several factors that control transcriptional regulation in bacteria, and experimentally demonstrate the model’s accuracy across 825 measurements in several genetic contexts and hosts. We then employ our first principles model to design, experimentally construct, and characterize a family of signal amplifying genetic circuits (genetic OpAmps) that expand the dynamic range of cell sensors. To develop these models, we needed a new approach to measuring the in vivo binding free energies of transcription factors (TFs), a key ingredient of statistical thermodynamic models of gene regulation. We developed a new high-throughput assay to measure RNA polymerase and TF binding free energies, requiring the construction and characterization of only a few constructs and data analysis (Figure 1A). We experimentally verified the assay on 6 TetR-homolog repressors and a CRISPR/dCas9 guide RNA. We found that our binding free energy measurements quantitatively explains why changing TF expression levels alters circuit function. Altogether, by combining these measurements with our biophysical model of translation (the RBS Calculator) as well as other measurements (Figure 1B), our model can account for changes in TF binding sites, TF expression levels, circuit copy number, host genome size, and host growth rate (Figure 1C). Model predictions correctly accounted for how these 8 factors control a promoter’s transcription rate (Figure 1D). Using the model, we developed a design framework for engineering multi-promoter genetic circuits that greatly reduces the number of degrees of freedom (8 factors per promoter) to a single dimensionless unit. We propose the Ptashne (Pt) number to encapsulate the 8 co-dependent factors that control transcriptional regulation into a single number. Therefore, a single number controls a promoter’s output rather than these 8 co-dependent factors, and designing a genetic circuit with N promoters requires specification of only N Pt numbers. We demonstrate how to design genetic circuits in Pt number space by constructing and characterizing 15 2-repressor OpAmp circuits that act as signal amplifiers when within an optimal Pt region. We experimentally show that OpAmp circuits using different TFs and TF expression levels will only amplify the dynamic range of input signals when their corresponding Pt numbers are within the optimal region. Thus, the use of the Pt number greatly simplifies the genetic circuit design, particularly important as circuits employ more TFs to perform increasingly complex functions.

Keywords: transcription factor, synthetic biology, genetic circuit, biophysical model, binding energy measurement

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Authors: Jelena Slugan, Ivica Ružić

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We are witnessing the rapid development of technologies that change the world around us. However, curriculums and teaching processes are often slow to adapt to the change; it takes time, money and expertise to implement technology in the classroom. Therefore, the University of Split, Croatia, partnered with local school Marko Marulić High School and created the project "Modern competence in modern high schools" as part of which five different curriculums for STEM areas were developed. One of the curriculums involves combining information technology with physics. The main idea was to teach students how to use different circuits and microcomputers to explore nature and physical phenomena. As a result, using electrical circuits, students are able to recreate in the classroom the phenomena that they observe every day in their environment. So far, high school students had very little opportunity to perform experiments independently, and especially, those physics experiment did not involve ICT. Therefore, this project has a great importance, because the students will finally get a chance to develop themselves in accordance to modern technologies. This paper presents some new methods of teaching physics that will help students to develop experimental skills through the study of deterministic nature of physical laws. Students will learn how to formulate hypotheses, model physical problems using the electronic circuits and evaluate their results. While doing that, they will also acquire useful problem solving skills.

Keywords: ICT in physics, curriculum, laboratory activities, STEM (science, technology, engineering, mathematics)

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Authors: Vishal Pareek, Shubham Gupta, Sushil Chandra Jain

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With increasing high-speed computation demand the power consumption, heat dissipation and chip size issues are posing challenges for logic design with conventional technologies. Recovery of bit loss and bit errors is other issues that require reversibility and fault tolerance in the computation. The reversible computing is emerging as an alternative to conventional technologies to overcome the above problems and helpful in a diverse area such as low-power design, nanotechnology, quantum computing. Bit loss issue can be solved through unique input-output mapping which require reversibility and bit error issue require the capability of fault tolerance in design. In order to incorporate reversibility a number of combinational reversible logic based circuits have been developed. However, very few sequential reversible circuits have been reported in the literature. To make the circuit fault tolerant, a number of fault model and test approaches have been proposed for reversible logic. In this paper, we have attempted to incorporate fault tolerance in sequential reversible building blocks such as D flip-flop, T flip-flop, JK flip-flop, R-S flip-flop, Master-Slave D flip-flop, and double edge triggered D flip-flop by making them parity preserving. The importance of this proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault and single bit fault. In our opinion our design of reversible building blocks is superior to existing designs in term of quantum cost, hardware complexity, constant input, garbage output, number of gates and design of online testable D flip-flop have been proposed for the first time. We hope our work can be extended for building complex reversible sequential circuits.

Keywords: parity preserving gate, quantum computing, fault tolerance, flip-flop, sequential reversible logic

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Authors: Zahra Khalid, Gul Muhammad Khan, Arbab Masood Ahmad

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Cartesian Genetic Programming (CGP) is explored to design an optimal circuit capable of early stage breast cancer detection. CGP is used to evolve simple multiplexer circuits for detection of malignancy in the Fine Needle Aspiration (FNA) samples of breast. The data set used is extracted from Wisconsins Breast Cancer Database (WBCD). A range of experiments were performed, each with different set of network parameters. The best evolved network detected malignancy with an accuracy of 99.14%, which is higher than that produced with most of the contemporary non-linear techniques that are computational expensive than the proposed system. The evolved network comprises of simple multiplexers and can be implemented easily in hardware without any further complications or inaccuracy, being the digital circuit.

Keywords: breast cancer detection, cartesian genetic programming, evolvable hardware, fine needle aspiration

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Authors: Kala Bharathan, R. Seshasayanan

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In this paper, a 1-bit Embedded Logic Full Adder (EFA) circuit in transistor level is proposed, which reduces logic complexity, gives low power and high speed. The design is further extended till 64 bits. To evaluate the performance of EFA, a 16, 32, 64-bit both Linear and Square root Carry Select Adder/Subtractor (CSLAS) Structure is also proposed. Realistic testing of proposed circuits is done on 8 X 8 Modified Booth multiplier and comparison in terms of power and delay is done. The EFA is implemented for different multiplier architectures for performance parameter comparison. Overall delay for CSLAS is reduced to 78% when compared to conventional one. The circuit implementations are done on TSMC 28nm CMOS technology using Cadence Virtuoso tool. The EFA has power savings of up to 14% when compared to the conventional adder. The present implementation was found to offer significant improvement in terms of power and speed in comparison to other full adder circuits.

Keywords: embedded logic, full adder, pdp, xor gate

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Authors: Mohamed Sanad, Noha Hassan

Abstract:

A broadband resonant terminal antenna has been developed. It can be used in different MIMO arrangements such as 2x2, 4x4, 8x8, or even 12x12 MIMO configurations. The antenna covers the whole LTE and WiFi bands besides the existing 2G/3G bands (700-5800 MHz), without using any matching/tuning circuits. Matching circuits significantly reduce the efficiency of any antenna and reduce the battery life. They also reduce the bandwidth because they are frequency dependent. The antenna can be implemented in smartphone handsets, tablets, laptops, notebooks or any other terminal. It is also suitable for different IoT and vehicle applications. The antenna is manufactured from a flexible material and can be bent or folded and shaped in any form to fit any available space in any terminal. It is self-contained and does not need to use the ground plane, the chassis or any other component of the terminal. Hence, it can be mounted on any terminal at different positions and configurations. Its performance does not get affected by the terminal, regardless of its type, shape or size. Moreover, its performance does not get affected by the human body of the terminal’s users. Because of all these unique features of the antenna, multiples of them can be simultaneously used for MIMO diversity coverage in any terminal device with a high isolation and a low correlation factor between them.

Keywords: IOT, LTE, MIMO, terminal antenna, WiFi

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Authors: K. Yahia, M. Sahraoui, A. Guettaf

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This paper deals with the problem of stator faults diagnosis in induction motors. Using the discrete wavelet transform (DWT) for the current Park’s vector modulus (CPVM) analysis, the inter-turn short-circuit faults diagnosis can be achieved. This method is based on the decomposition of the CPVM signal, where wavelet approximation and detail coefficients of this signal have been extracted. The energy evaluation of a known bandwidth detail permits to define a fault severity factor (FSF). This method has been tested through the simulation of an induction motor using a mathematical model based on the winding-function approach. Simulation, as well as experimental results, show the effectiveness of the used method.

Keywords: induction motors (IMs), inter-turn short-circuits diagnosis, discrete wavelet transform (DWT), Current Park’s Vector Modulus (CPVM)

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Authors: F. Fekak, A. Gravouil, M. Brun, B. Depale

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During an earthquake, a bridge crane may be subjected to multiple impacts between crane wheels and rail. In order to model such phenomena, a time-history dynamic analysis with a multi-scale approach is performed. The high frequency aspect of the impacts between wheels and rails is taken into account by a Lagrange explicit event-capturing algorithm based on a velocity-impulse formulation to resolve contacts and impacts. An implicit temporal scheme is used for the rest of the structure. The numerical coupling between the implicit and the explicit schemes is achieved with a heterogeneous asynchronous time-integrator.

Keywords: bridge crane, earthquake, dynamic analysis, explicit, implicit, impact

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Authors: P. Pistelok

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The article presents the concept of an electromagnetic circuit generator with permanent magnets mounted on the surface rotor core designed for single phase work. Computation field-circuit model was shown. The spectrum of time course of voltages in the idle work was presented. The cross section with graphically presentation of magnetic induction in particular parts of electromagnetic circuits was presented. Distribution of magnetic induction at the rated load point for each phase were shown. The time course of voltages and currents for each phases for rated power were displayed. An analysis of laboratory results and measurement of load characteristics of the generator was discussed. The work deals with three electromagnetic circuits of generators with permanent magnet where output voltage characteristics versus rated power were expressed.

Keywords: permanent magnet generator, permanent magnets, vibration, course of torque, single phase work, asymmetrical three phase work

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Authors: Tokuei Sako

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Light-induced ultrafast charge transfer in low-dimensional nanostructure has been studied by a model of a few electrons confined in a 1D electrostatic potential coupled to electrodes at both ends and subjected to an ultrashort pulsed laser field. The time-propagation of the one- and two-electron wave packets has been calculated by integrating the time-dependent Schrödinger equation by the symplectic integrator method with uniform Fourier grid. The temporal behavior of the resultant light-induced current in the studied systems has been discussed with respect to the central frequency and pulse width of the applied laser fields.

Keywords: pulsed laser field, nanowire, wave packet, quantum dots, conductivity

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Authors: Liqin Zhang, Liang Yan

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This paper addresses the speed synchronization control problem for a network-based multi-motor system from the perspective of cluster consensus theory. Each motor is considered as a single agent connected through fixed and undirected network. This paper presents an improved control protocol from three aspects. First, for the purpose of improving both tracking and synchronization performance, this paper presents a distributed leader-following method. The improved control protocol takes the importance of each motor’s speed into consideration, and all motors are divided into different groups according to speed weights. Specifically, by using control parameters optimization, the synchronization error and tracking error can be regulated and decoupled to some extent. The simulation results demonstrate the effectiveness and superiority of the proposed strategy. In practical engineering, the simplified models are unrealistic, such as single-integrator and double-integrator. And previous algorithms require the acceleration information of the leader available to all followers if the leader has a varying velocity, which is also difficult to realize. Therefore, the method focuses on an observer-based variable structure algorithm for consensus tracking, which gets rid of the leader acceleration. The presented scheme optimizes synchronization performance, as well as provides satisfactory robustness. What’s more, the existing algorithms can obtain a stable synchronous system; however, the obtained stable system may encounter some disturbances that may destroy the synchronization. Focus on this challenging technological problem, a state-dependent-switching approach is introduced. In the presence of unmeasured angular speed and unknown failures, this paper investigates a distributed fault-tolerant consensus tracking algorithm for a group non-identical motors. The failures are modeled by nonlinear functions, and the sliding mode observer is designed to estimate the angular speed and nonlinear failures. The convergence and stability of the given multi-motor system are proved. Simulation results have shown that all followers asymptotically converge to a consistent state when one follower fails to follow the virtual leader during a large enough disturbance, which illustrates the good performance of synchronization control accuracy.

Keywords: consensus control, distributed follow, fault-tolerant control, multi-motor system, speed synchronization

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Authors: Lina Pan

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In non-Gaussian clutter of a spherically invariant random vector, in the cases that a certain estimated covariance matrix could become singular, the adaptive target detection of high-range-resolution radar is addressed. Firstly, the restricted maximum likelihood (RML) estimates of unknown covariance matrix and scatterer amplitudes are derived for non-Gaussian clutter. And then the RML estimate of texture is obtained. Finally, a novel detector is devised. It is showed that, without secondary data, the proposed detector outperforms the existing Kelly binary integrator.

Keywords: non-Gaussian clutter, covariance matrix estimation, target detection, maximum likelihood

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

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As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: scan chain, single event transient, soft error, 8051 processor

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Authors: K. Yahia, A. Ghoggal, A. Titaouine, S. E. Zouzou, F. Benchabane

Abstract:

This paper deals with the problem of stator faults diagnosis in induction motors. Using the discrete wavelet transform (DWT) for the current Park’s vector modulus (CPVM) analysis, the inter-turn short-circuit faults diagnosis can be achieved. This method is based on the decomposition of the CPVM signal, where wavelet approximation and detail coefficients of this signal have been extracted. The energy evaluation of a known bandwidth detail permits to define a fault severity factor (FSF). This method has been tested through the simulation of an induction motor using a mathematical model based on the winding-function approach. Simulation, as well as experimental, results show the effectiveness of the used method.

Keywords: Induction Motors (IMs), Inter-turn Short-Circuits Diagnosis, Discrete Wavelet Transform (DWT), Current Park’s Vector Modulus (CPVM)

Procedia PDF Downloads 563