Search results for: field-effect transistors

Authors: Rajesh Kumar Ulaganathan, Yi-Ying Lu, Chia-Jung Kuo, Srinivasa Reddy Tamalampudi, Raman Sankar, Fang Cheng Chou, Yit-Tsong Chen

Abstract:

In this paper, we report the optoelectronic properties of multi-layered GeS nanosheets (~28 nm thick)-based field-effect transistors (called GeS-FETs). The multi-layered GeS-FETs exhibit remarkably high photoresponsivity of Rλ ~ 206 AW-1 under illumination of 1.5 µW/cm2 at  = 633 nm, Vg = 0 V, and Vds = 10 V. The obtained Rλ ~ 206 AW-1 is excellent as compared with a GeS nanoribbon-based and the other family members of group IV-VI-based photodetectors in the two-dimensional (2D) realm, such as GeSe and SnS2. The gate-dependent photoresponsivity of GeS-FETs was further measured to be able to reach Rλ ~ 655 AW-1 operated at Vg = -80 V. Moreover, the multi-layered GeS photodetector holds high external quantum efficiency (EQE ~ 4.0 × 104 %) and specific detectivity (D* ~ 2.35 × 1013 Jones). The measured D* is comparable to those of the advanced commercial Si- and InGaAs-based photodiodes. The GeS photodetector also shows an excellent long-term photoswitching stability with a response time of ~7 ms over a long period of operation (>1 h). These extraordinary properties of high photocurrent generation, broad spectral range, fast response, and long-term stability make the GeS-FET photodetector a highly qualified candidate for future optoelectronic applications.

Keywords: germanium sulfide, photodetector, photoresponsivity, external quantum efficiency, specific detectivity

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Authors: Evln Ranga Charyulu, S. P. Venu Madhavarao, S. Udaya kumar, S. V. S. S. N. V. G. Krishna Murthy

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With the advent of new nanometer process technologies, it is possible to integrate billion transistors on a single substrate. When more and more functionality included there is the possibility of multi-million transistors switching simultaneously consuming more power and dissipating more power along with more leakage of current into the substrate of porous silicon or germanium material. These results in substrate heating and thermal noise generation coupled to signals of interest. The heating process is represented by coupled nonlinear partial differential equations in porous silicon and germanium. By identifying heat sources and heat fluxes may results in designing of ultra-low power circuits. The PDEs are solved by finite difference scheme assuming that boundary layer equations in porous silicon and germanium. Local heat fluxes along the vertical isothermal surface immersed in porous SI/Ge are considered. The parameters considered for optimization are thermal diffusivity, thermal expansion coefficient, thermal diffusion ratio, permeability, specific heat at constant temperatures, Rayleigh number, amplitude of wavy surface, mass expansion coefficient. The diffusion of heat was caused by the concentration gradient. Thermal physical properties are homogeneous and isotropic. By using L8, TAGUCHI method the parameters are optimized.

Keywords: heat transfer, pde, taguchi optimization, SI/Ge

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Authors: C. S Lee, W. C. Hsu, H. Y. Liu, C. J. Lin, S. C. Yao, Y. T. Shen, Y. C. Lin

Abstract:

In₀.₁₈Al₀.₈₂N/AlN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) having Al₂O₃ gate-dielectric and backside metal-trench structure are investigated. The Al₂O₃ gate oxide was formed by using a cost-effective non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. In order to enhance the heat dissipation efficiency, metal trenches were etched 3-µm deep and evaporated with a 150-nm thick Ni film on the backside of the Si substrate. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET (Schottky-gate HFET) has demonstrated improved maximum drain-source current density (IDS, max) of 1.08 (0.86) A/mm at VDS = 8 V, gate-voltage swing (GVS) of 4 (2) V, on/off-current ratio (Ion/Ioff) of 8.9 × 10⁸ (7.4 × 10⁴), subthreshold swing (SS) of 140 (244) mV/dec, two-terminal off-state gate-drain breakdown voltage (BVGD) of -191.1 (-173.8) V, turn-on voltage (Von) of 4.2 (1.2) V, and three-terminal on-state drain-source breakdown voltage (BVDS) of 155.9 (98.5) V. Enhanced power performances, including saturated output power (Pout) of 27.9 (21.5) dBm, power gain (Gₐ) of 20.3 (15.5) dB, and power-added efficiency (PAE) of 44.3% (34.8%), are obtained. Superior breakdown and RF power performances are achieved. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET design with backside metal-trench is advantageous for high-power circuit applications.

Keywords: backside metal-trench, InAlN/AlN/GaN, MOS-HFET, non-vacuum ultrasonic spray pyrolysis deposition

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Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO₂ interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center

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Authors: Clara Oliver, Oibar Martinez

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This paper is intended to reveal the severity of electrostatic discharge (ESD) effects in electronic and optoelectronic devices by performing sensitivity tests based on Human Body Model (HBM) standard. We explain here the HBM standard in detail together with the typical failure modes associated with electrostatic discharges. In addition, a prototype of electrostatic charge generator has been designed, fabricated, and verified to stress electronic devices, which features a compact high voltage source. This prototype is inexpensive and enables one to do a battery of pre-compliance tests aimed at detecting unexpected weaknesses to static discharges at the component level. Some tests with different devices were performed to illustrate the behavior of the proposed generator. A set of discharges was applied according to the HBM standard to commercially available bipolar transistors, complementary metal-oxide-semiconductor transistors and light emitting diodes. It is observed that high current and voltage ratings in electronic devices not necessarily provide a guarantee that the device will withstand high levels of electrostatic discharges. We have also compared the result obtained by performing the sensitivity tests based on HBM with a real discharge generated by a human. For this purpose, the charge accumulated in the person is monitored, and a direct discharge against the devices is generated by touching them. Every test has been performed under controlled relative humidity conditions. It is believed that this paper can be of interest for research teams involved in the development of electronic and optoelectronic devices which need to verify the reliability of their devices in terms of robustness to electrostatic discharges.

Keywords: human body model, electrostatic discharge, sensitivity tests, static charge monitoring

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Authors: Ameni Mahmoudi, Manel Troudi, Paolo Bondavalli, Nabil Sghaier

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In this study, the charge storage on thin-film SWCNT transistors was investigated, and C-V hysteresis tests showed that interface charge trapping effects predominate the memory window. Two electrode materials were utilized to demonstrate that selecting the appropriate metal electrode clearly improves the conductivity and, consequently, the SWCNT thin-film’s memory effect. Because their work function is similar to that of thin-film carbon nanotubes, Ti contacts produce higher charge confinement and show greater charge storage than Pd contacts. For Pd-contact CNTFETs and CNTFETs with Ti electrodes, a sizable clockwise hysteresis window was seen in the dual sweep circle with a threshold voltage shift of V11.52V and V9.7V, respectively. The SWCNT thin-film based transistor is expected to have significant trapping and detrapping charges because of the large C-V hysteresis. We have found that the predicted stored charge density for CNTFETs with Ti contacts is approximately 4.01×10-2C.m-2, which is nearly twice as high as the charge density of the device with Pd contacts. We have shown that the amount of trapped charges can be changed by sweeping the range or Vgs rate. We also looked into the variation in the flat band voltage (V FB) vs. time in order to determine the carrier retention period in CNTFETs with Ti and Pd electrodes. The outcome shows that memorizing trapped charges is about 300 seconds, which is a crucial finding for memory function mimicking.

Keywords: charge storage, thin-film SWCNT based transistors, C-V hysteresis, memory effect, trapping and detrapping charges, stored charge density, the carrier retention time

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Authors: Nissar Mohammad Karim, Norhayati Soin

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To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, Sol-Gel, precursor aging, aging

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Authors: Nissar Mohammad Karim, Norhayati Soin

Abstract:

To ensure fast switching in high-K incorporated Complementary Metal Oxide Semiconductor (CMOS) transistors, the results on the basis of d (NBTI) by incorporating SiO2 dielectric with aged samples of CuO sol-gels have been reported. Precursor ageing has been carried out for 4 days. The minimum obtained refractive index is 1.0099 which was found after 3 hours of adhesive UV curing. Obtaining a low refractive index exhibits a low dielectric constant and hence a faster system.

Keywords: refractive index, sol-gel, precursor ageing, metallurgical and materials engineering

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Authors: Wei-Chou Hsu, Ching-Sung Lee, Han-Yin Liu

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This work uses H2O2 oxidation technique to improve the pH sensitivity of the AlGaN/GaN-based ion-sensitive field-effect transistors (ISFETs). 10-nm-thick Al2O3 was grown on the surface of the AlGaN. It was found that the pH sensitivity was improved from 41.6 mV/pH to 55.2 mV/pH. Since the H2O2-grown Al2O3 was served as a passivation layer and the problem of Fermi-level pinning was suppressed for the ISFET with the H2O2 oxidation process. Hysteresis effect in the ISFET with the H2O2 treatment also became insignificant. The hysteresis effect was observed by dipping the ISFETs into different pH value solutions and comparing the voltage difference between the initial and final conditions. The hysteresis voltage (Vhys) of the ISFET with the H2O2 oxidation process was improved from 8.7 mV to 4.8 mV. The hysteresis effect is related to the buried binding sites which are related to the material defects like threading dislocations in the AlGaN/GaN heterostructure which was grown by the hetero-epitaxy technique. The H2O2-grown Al2O3 passivate these material defects and the Al2O3 has less material defects. The long-term stability of the ISFET is estimated by the drift effect measurement. The drift measurement was conducted by dipping the ISFETs into a specific pH value solution for 12 hours and the ISFETs were operating at a specific quiescent point. The drift rate is estimated by the drift voltage divided by the total measuring time. It was found that the drift rate of the ISFET was improved from 10.1 mV/hour to 1.91 mV/hour in the pH 7 solution, from 14.06 mV/hour to 6.38 mV/pH in the pH 2 solution, and from 12.8 mV/hour to 5.48 mV/hour in the pH 12 solution. The drift effect results from the capacitance variation in the electric double layer. The H2O2-grown Al2O3 provides an additional capacitance connection in series with the electric double layer. Therefore, the capacitance variation of the electric double layer became insignificant. Generally, the H2O2 oxidation process is a simple, fast, and cost-effective method for the AlGaN/GaN-based ISFET. Furthermore, the performance of the AlGaN/GaN ISFET was improved effectively and the non-ideal effects were suppressed.

Keywords: AlGaN/GaN, Al2O3, hysteresis effect, drift effect, reliability, passivation, pH sensors

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Authors: A. Douara, N. Kermas, B. Djellouli

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In this study, we report calculations of gate capacitance of AlGaN/GaN HEMTs with nextnano device simulation software. We have used a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. These simulations explore various device structures with different values of barrier thickness and channel thickness. A detailed understanding of the impact of gate capacitance in HEMTs will allow us to determine their role in future 10 nm physical gate length node.

Keywords: gate capacitance, AlGaN/GaN, HEMTs, quantum capacitance, centroid capacitance

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Authors: Karandeep Kaur

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This paper presents the design of power amplifier (PA) for mmWave communication systems. The designed amplifier uses GlobalFoundries 22 FDX technology and works at an operational frequency of 140 GHz in the D-Band. With a supply voltage of 0.8V for the super low threshold voltage transistors, the amplifier is biased in class AB and has a total current consumption of 50 mA. The measured saturated output power from the power amplifier is 5.6 dBm with an output-referred 1dB-compression point of 1.6dBm. The measured gain of PA is 19 dB with 3 dB-bandwidth ranging from 120 GHz to 140 GHz. The chip occupies an area of 795µm × 410µm.

Keywords: mmWave communication system, power amplifiers, 22FDX, D-Band, cross-coupled capacitive neutralization

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Authors: Anwar H. Jarndal, Ahmed S. Elwakil

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In this paper, a fraction-order model for pad parasitic effect of GaN HEMT on Si substrate is developed and validated. Open de-embedding structure is used to characterize and de-embed substrate loading parasitic effects. Unbiased device measurements are implemented to extract parasitic inductances and resistances. The model shows very good simulation for S-parameter measurements under different bias conditions. It has been found that this approach can improve the simulation of intrinsic part of the transistor, which is very important for small- and large-signal modeling process.

Keywords: fractional-order modeling, GaNHEMT, si-substrate, open de-embedding structure

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Authors: Hasan Çiçekli, Ahmet Gökçen, Uğur Çam

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In this paper, a comparative performance analysis of mostly used four nonlinearity cancellation techniques used to realize the passive resistor by MOS transistors is presented. The comparison is done by using an integrator circuit which is employing sequentially Op-amp, OTRA and ICCII as active element. All of the circuits are implemented by MOS-C realization and simulated by PSPICE program using 0.35 µm process TSMC MOSIS model parameters. With MOS-C realization, the circuits became electronically tunable and fully integrable which is very important in IC design. The output waveforms, frequency responses, THD analysis results and features of the nonlinearity cancellation techniques are also given.

Keywords: integrator circuits, MOS-C realization, nonlinearity cancellation, tuneable resistors

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Authors: Ata Khorami, Mohammad Sharifkhani

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In the dynamic comparators, the pre-amplifier amplifies the input differential voltage and when the output Vcm of the pre-amplifier becomes larger than Vth of the latch input transistors, the latch is activated and finalizes the comparison. As a result, the pre-amplification delay is fixed to a value and cannot be set at the minimum required delay, thus, significant power and delay are imposed. In this paper, a novel structure is proposed through which the pre-amplification delay can be set at any low value saving power and time. Simulations show that using the proposed structure, by setting the pre-amplification delay at the minimum required value the power and comparison delay can be reduced by 55% and 100ps respectively.

Keywords: dynamic comparator, low power comparator, analog to digital converter, pre-amplification delay

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Authors: Zakarya Kourdi, Mohammed Khaouani, Benyounes Bouazza, Ahlam Guen-Bouazza, Amine Boursali

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In this paper, we have evaluated the thermal effect for high electron mobility transistors (HEMTs) heterostructure InAlN/GaN with a gate length 30nm high-performance. It also shows the analysis and simulated these devices, and how can be used in different application. The simulator Tcad-Silvaco software has used for predictive results good for the DC, AC and RF characteristic, Devices offered max drain current 0.67A; transconductance is 720 mS/mm the unilateral power gain of 180 dB. A cutoff frequency of 385 GHz, and max frequency 810 GHz These results confirm the feasibility of using HEMTs with InAlN/GaN in high power amplifiers, as well as thermal places.

Keywords: HEMT, Thermal Effect, Silvaco, InAlN/GaN

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Authors: Parisa Khoshvaght, Mehdi Hosseinzadeh

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During the past few years, the Residue Number System (RNS) has been receiving considerable interest due to its parallel and fault-tolerant properties. This system is a useful tool for Digital Signal Processing (DSP) since it can support parallel, carry-free, high-speed and low power arithmetic. One of the drawbacks of Residue Number System is the fractional numbers, that is, the corresponding circuit is very hard to realize in conventional CMOS technology. In this paper, we propose a method in which the numbers of transistors are significantly reduced. The related delay is extremely diminished, in the first glance we use this method to solve concerning problem of one decimal functional number some how this proposition can be extended to generalize the idea. Another advantage of this method is the independency on the kind of moduli.

Keywords: computer arithmetic, residue number system, number system, one-Hot, VLSI

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Authors: Tae Kyu An

Abstract:

We demonstrate repurposing linear micropatterns on the CD as a master mold to fabricate TIPS-PEN microwires. From the micropatterns on CDs, we replicated polyurethane acrylate (PUA) templates which are robust and flexible until submicrometer scale patterns. Subsequently, 1.5 μm TIPS-PEN microwires separated by 1.5 μm were grown. Using crystal analysis tools with polarized optical microscopy and X-ray diffraction measurement, it was revealed that each TIPS-PEN microwires are highly crystalline and uniform compared to spin-coated films. It is attributed to the template-guided growth of TIPS-PEN crystals along the linear template, thus the OFETs comprised of TIPS-PEN microwires displayed the high field-effect mobility.

Keywords: compact disk, macro patterning, OFET, soft lithography

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

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This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: digital electronics, integrated circuits, full adder, 32nm CMOS tehnology, double pass transistor technology, fault toleance, self-checking

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Authors: Madina Hamiane

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Modelling and simulation of an analogy function generator is presented based on a polynomial expansion model. The proposed function generator model is based on a 10th order polynomial approximation of any of the required functions. The polynomial approximations of these functions can then be implemented using basic CMOS circuit blocks. In this paper, a circuit model is proposed that can simultaneously generate many different mathematical functions. The circuit model is designed and simulated with HSPICE and its performance is demonstrated through the simulation of a number of non-linear functions.

Keywords: modelling and simulation, analog function generator, polynomial approximation, CMOS transistors

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Authors: V. Swarnalatha, A. V. Narasimha Rao, P. Pal

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The present research reports the investigation of fast etching of silicon for the fabrication of microelectromechanical systems (MEMS) structures using silicon wet bulk micromachining. Low concentration tetramethyl-ammonium hydroxide (TMAH) and hydroxylamine (NH₂OH) are used as main etchant and additive, respectively. The concentration of NH₂OH is varied to optimize the composition to achieve best etching characteristics such as high etch rate, significantly high undercutting at convex corner for the fast release of the microstructures from the substrate, and improved etched surface morphology. These etching characteristics are studied on Si{100} and Si{110} wafers as they are most widely used in the fabrication of MEMS structures as wells diode, transistors and integrated circuits.

Keywords: KOH, MEMS, micromachining, silicon, TMAH, wet anisotropic etching

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Authors: Adriana-Gabriela Plaiasu, Catalin Marian Ducu

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The interest in the unique properties associated with materials having structures on a nanometer scale has been increasing at an exponential rate in last decade. Among the functional mineral compounds such as perovskite (CaTiO3), rutile (TiO2), CaF2, spinel (MgAl2O4), wurtzite (ZnS), zincite (ZnO) and the cupric oxide (CuO) has been used in numerous applications such as catalysis, semiconductors, batteries, gas sensors, biosensors, field transistors and medicine. The Solar Physical Vapor Deposition (SPVD) presented in the paper as elaboration method is an original process to prepare nanopowders working under concentrated sunlight in 2kW solar furnaces. The influence of the synthesis parameters on the chemical and microstructural characteristics of zinc and manganese oxides synthesized nanophases has been systematically studied using XRD, TEM and SEM.

Keywords: characterization, morphological, nano-oxides, structural

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Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

Abstract:

This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, voltage transition, node stabilization, biasing circuits

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Authors: Abdelghafour Galadi

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In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.

Keywords: power MOSFET, drift layer, quasi-saturation effect, SPICE model

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Authors: Anwar Jarndal

Abstract:

In this paper, a genetic-neural-network (GNN) based large-signal model for GaN HEMTs is presented along with its parameters extraction procedure. The model is easy to construct and implement in CAD software and requires only DC and S-parameter measurements. An improved decomposition technique is used to model self-heating effect. Two GNN models are constructed to simulate isothermal drain current and power dissipation, respectively. The two model are then composed to simulate the drain current. The modeling procedure was applied to a packaged GaN-on-Si HEMT and the developed model is validated by comparing its large-signal simulation with measured data. A very good agreement between the simulation and measurement is obtained.

Keywords: GaN HEMT, computer-aided design and modeling, neural networks, genetic optimization

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Authors: Mojtaba Ghodsi, Hamidreza Ziaifar, Morteza Mohammadzaheri, Payam Soltani

Abstract:

In this paper, the performance of a medium power (25 kW/25 kHz) hybrid inverter with a reactive transformer is investigated. To analyze the sensitivity of the inverster, the RSM technique is employed to manifest the effective factors in the inverter to minimize current passing through the Insulated Bipolar Gate Transistors (IGBTs) (current stress). It is revealed that the ratio of the axillary inductor to the effective inductance of resonant inverter (N), is the most effective parameter to minimize the current stress in this type of inverter. In practice, proper selection of N mitigates the current stress over IGBTs by five times. This reduction is very helpful to keep the IGBTs at normal temperatures.

Keywords: analytical analysis, hybrid resonant inverter, reactive transformer, response surface method

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Authors: A. boursali, A. Guen Bouazza, M. Khaouani, Z. Kourdi, B. Bouazza

Abstract:

This paper presents the design, development and characterization of the devices simulation for X-Band Radar applications. The effect of an InAlN/GaN structure on the RF performance High Electron Mobility Transistor (HEMT) device. Systematic investigations on the small signal as well as power performance as functions of the drain biases are presented. Were improved for X-band applications. The Power Added Efficiency (PAE) was achieved over 23% for X-band. The developed devices combine two InAlN/GaN HEMTs of 30nm gate periphery and exhibited the output power of over 50W. An InAlN/GaN HEMT with 30nm gate periphery was developed and exhibited the output power of over 120W.

Keywords: InAlN/GaN, HEMT, RF analyses, PAE, X-Band, radar

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Authors: Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn

Abstract:

This paper discusses the undesirable charge transfer through the parasitic capacitances of the input transistors in a multi-inputs voltage sense amplifier. Its intrinsic rail-to-rail voltage transitions at the output nodes inevitably disturb the input sides through the capacitive coupling between the outputs and inputs. Then, it can possible degrade the stabilities of the reference voltage levels. Moreover, it becomes more serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the overall systems. In order to alleviate the internal node voltage transition, the internal node stabilization techniques are proposed. It achieves 45% and 40% improvements for node stabilization and input referred disturbance, respectively.

Keywords: voltage sense amplifier, multi-inputs, voltage transition, node stabilization, biasing circuits

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Authors: Kuan Yu Lin, Shih Chih Chen

Abstract:

This study focuses on the Al/HfO₂/Si/Al structure to explore the electrical properties of the structure. This experiment uses a radio frequency magnetron sputtering system to deposit high dielectric materials on p-type silicon substrates of 1~10 Ω-cm (100). Consider the hafnium dioxide film as a dielectric layer. Post-deposition annealing at 750°C in nitrogen atmosphere. Electron beam evaporation of metallic aluminum is then used to complete the top/bottom electrodes. The metal is post-annealed at 450°C for 20 minutes in a nitrogen environment to complete the MOS component. Its dielectric constant, equivalent oxide layer thickness, oxide layer defects, and leakage current mechanism are discussed. At PDA 750°C-5s, the maximum k value was found to be 21.2, and the EOT was 3.68nm.

Keywords: high-k gate dielectrics, HfO₂, post deposition annealing, RF magnetic

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Authors: Suruchi Saini, Hitender Kumar Tyagi

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With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively.

Keywords: current on-off ratio, FinFET, short-channel effects, transconductance

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

Abstract:

This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ~72% PAE and output power of > 39 dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5 GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The load- and source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: power amplifier (PA), high power, class-J and class-E, high efficiency

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