Search results for: FPGA tool

Authors: Tayab D. Memon, Shahji Farooque, Marvi Deshi, Imtiaz Hussain Kalwar, B. S. Chowdhry

Abstract:

Recently single-bit ternary FIR-like filter (SBTFF) hardware synthesize in FPGA is reported and compared with multi-bit FIR filter on similar spectral characteristics. Results shows that SBTFF dominates upon multi-bit filter overall. In this paper, an optimized adder module for ternary quantized sigma-delta modulated signal is presented. The adder is simulated using ModelSim for functional verification the area-performance of the proposed adder were obtained through synthesis in Xilinx and compared to conventional adder trees. The synthesis results show that the proposed adder tree achieves higher clock rates and lower chip area at higher inputs to the adder block; whereas conventional adder tree achieves better performance and lower chip area at lower number of inputs to the same adder block. These results enhance the usefulness of existing short word length DSP algorithms for fast and efficient mobile communication.

Keywords: short word length (SWL), DSP algorithms, FPGA, SBTFF, VHDL

Procedia PDF Downloads 319

Authors: Hussain K. Chaiel

Abstract:

The development in the field of the digital signal processing (DSP) and the microelectronics technology reduces the complexity of the iterative algorithms that need large number of arithmetic operations. Virtex-Field Programmable Gate Arrays (FPGAs) are programmable silicon foundations which offer an important solution for addressing the needs of high performance DSP designer. In this work, Virtex-7 FPGA technology is used to implement an iterative algorithm to estimate the earthquake location. Simulation results show that an implementation based on block RAMB36E1 and DSP48E1 slices of Virtex-7 type reduces the number of cycles of the clock frequency. This enables the algorithm to be used for earthquake prediction.

Keywords: DSP, earthquake, FPGA, iterative algorithm

Procedia PDF Downloads 359

Authors: Hanan Mikhael Dawood, Afaneen Anwer Abood Al-Khazraji

Abstract:

The paper presents an investigation of field oriented control strategy of Permanent Magnet Synchronous Motor (PMSM) based on hardware in the loop simulation (HIL) over a wide speed range. A sensorless rotor position estimation using sliding mode observer for permanent magnet synchronous motor is illustrated considering the effects of magnetic saturation between the d and q axes. The cross saturation between d and q axes has been calculated by finite-element analysis. Therefore, the inductance measurement regards the saturation and cross saturation which are used to obtain the suitable id-characteristics in base and flux weakening regions. Real time matrix multiplication in Field Programmable Gate Array (FPGA) using floating point number system is used utilizing Quartus-II environment to develop FPGA designs and then download these designs files into development kit. dSPACE DS1103 is utilized for Pulse Width Modulation (PWM) switching and the controller. The hardware in the loop results conducted to that from the Matlab simulation. Various dynamic conditions have been investigated.

Keywords: magnetic saturation, rotor position estimation, sliding mode observer, hardware in the loop (HIL)

Procedia PDF Downloads 502

Authors: H. Bentarzi, A. Zitouni

Abstract:

The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.

Keywords: amplifier class D, field-programmable gate array (FPGA), protective relay, tester

Procedia PDF Downloads 189

Authors: Hung-Yuan Chang, Wen-Lung Chiang, Kuo-Liang Wu, Chen-Tsung Lin

Abstract:

National Space Organization (NSPO) has completed in 2014 the development of a space-borne GPS receiver, including design, manufacture, comprehensive functional test, environmental qualification test and so on. The main performance of this receiver include 8-meter positioning accuracy, 0.05 m/sec speed-accuracy, the longest 90 seconds of cold start time, and up to 15g high dynamic scenario. The receiver will be integrated in the autonomous FORMOSAT-7 NSPO-Built satellite scheduled to be launched in 2019 to execute pre-defined scientific missions. The flight model of this receiver manufactured in early 2015 will pass comprehensive functional tests and environmental acceptance tests, etc., which are expected to be completed by the end of 2015. The space-borne GPS receiver is a pure software design in which all GPS baseband signal processing are executed by a digital signal processor (DSP), currently only 50% of its throughput being used. In response to the booming global navigation satellite systems, NSPO will gradually expand this receiver to become a multi-mode, multi-band, high-precision navigation receiver, and even a science payload, such as the reflectometry receiver of a global navigation satellite system. The fundamental purpose of this extension study is to port some software algorithms such as signal acquisition and correlation, reused code and large amount of computation load to the FPGA whose processor is responsible for operational control, navigation solution, and orbit propagation and so on. Due to the development and evolution of the FPGA is pretty fast, the new system architecture upgraded via an FPGA should be able to achieve the goal of being a multi-mode, multi-band high-precision navigation receiver, or scientific receiver. Finally, the results of tests show that the new system architecture not only retains the original overall performance, but also sets aside more resources available for future expansion possibility. This paper will explain the detailed DSP/FPGA architecture, development, test results, and the goals of next development stage of this receiver.

Keywords: space-borne, GPS receiver, DSP, FPGA, multi-mode multi-band

Procedia PDF Downloads 347

Authors: Ankit Shai

Abstract:

CRC or Cyclic Redundancy Check is one of the most common, and one of the most powerful error-detecting codes implemented on modern computers. Most of the modern communication protocols use some error detection algorithms in digital networks and storage devices to detect accidental changes to raw data between transmission and reception. Cyclic Redundancy Check, or CRC, is the most popular one among these error detection codes. CRC properties are defined by the generator polynomial length and coefficients. The aim of this project is to implement an efficient FPGA based CRC-8 that accepts a 32 bit input, taking into consideration optimal chip area and high performance, using VHDL. The proposed architecture is implemented on Xilinx ISE Simulator. It is designed while keeping in mind the hardware design, complexity and cost factor.

Keywords: cyclic redundancy checker, CRC-8, 32-bit input, FPGA, VHDL, ModelSim, Xilinx

Procedia PDF Downloads 270

Authors: Nan Hu, Chao Wang, Xi Li, Xuehai Zhou

Abstract:

The field-programmable gate array (FPGA) has been widely adopted in the high-performance computing domain. In recent years, the embedded system-on-a-chip (SoC) contains coarse granularity multi-core CPU (central processing unit) and mobile GPU (graphics processing unit) that can be used as general-purpose accelerators. The motivation is that algorithms of various parallel characteristics can be efficiently mapped to the heterogeneous architecture coupled with these three processors. The CPU and GPU offload partial computationally intensive tasks from the FPGA to reduce the resource consumption and lower the overall cost of the system. However, in present common scenarios, the applications always utilize only one type of accelerator because the development approach supporting the collaboration of the heterogeneous processors faces challenges. Therefore, a systematic approach takes advantage of write-once-run-anywhere portability, high execution performance of the modules mapped to various architectures and facilitates the exploration of design space. In this paper, A servant-execution-flow model is proposed for the abstraction of the cooperation of the heterogeneous processors, which supports task partition, communication and synchronization. At its first run, the intermediate language represented by the data flow diagram can generate the executable code of the target processor or can be converted into high-level programming languages. The instantiation parameters efficiently control the relationship between the modules and computational units, including two hierarchical processing units mapping and adjustment of data-level parallelism. An embedded system of a three-dimensional waveform oscilloscope is selected as a case study. The performance of algorithms such as contrast stretching, etc., are analyzed with implementations on various combinations of these processors. The experimental results show that the heterogeneous computing system with less than 35% resources achieves similar performance to the pure FPGA and approximate energy efficiency.

Keywords: FPGA-CPU-GPU collaboration, design space exploration, heterogeneous computing, intermediate language, parameterized instantiation

Procedia PDF Downloads 84

Authors: Long Kim Vu

Abstract:

The central processing unit in Electro-Optical devices is a Field-programmable gate array (FPGA) chip package allowing flexible, reconfigurable computing but energy consumption. Because chip package is placed in isolated devices based on IP67 waterproof standard, there is no air circulation and the heat dissipation is a challenge. In this paper, the author successfully modeled a chip package which various interposer materials such as silicon, glass and organics. Computational fluid dynamics (CFD) was utilized to analyze the thermal performance of chip package in the case of considering comprehensive heat transfer modes: conduction, convection and radiation, which proposes equivalent heat dissipation. The logic chip temperature varying with time is compared between the simulation and experiment results showing the excellent correlation, proving the reasonable chip modeling and simulation method.

Keywords: CFD, FPGA, heat transfer, thermal analysis

Procedia PDF Downloads 164

Authors: Anil Kumar Pandey

Abstract:

Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.

Keywords: power integrity, power-aware signal integrity analysis, electromagnetic simulation, channel simulation

Procedia PDF Downloads 413

Authors: B. Kirubakaran, C. Rajasekaran

Abstract:

Reconfigurable techniques are used in many engineering and industrial applications for the efficient data transmissions through the wireless sensor networks. Nowadays most of the industrial applications are work for try to minimize the size and cost. During runtime the reconfigurable technique avoid the unwanted hang and delay in the system performance. In recent world Field Programmable Gate Array (FPGA) as one of the most efficient reconfigurable device and widely used for most of the hardware and software reconfiguration applications. In this paper, the work deals with whatever going to make changes in the hardware and software during runtime it’s should not affect the current running process that’s the main objective of the paper our changes be done in a parallel manner at the same time concentrating the cost and power transmission problems during data trans-receiving. Analog sensor (Temperature) as an input for the controller (PIC) through that control the FPGA digital sensors in generalized manner.

Keywords: field programmable gate array, peripheral interrupt controller, runtime reconfigurable techniques, wireless sensor networks

Procedia PDF Downloads 384

Authors: S. Mohamed Rabeek, Mi Kyoung Park, M. Annamalai Arasu

Abstract:

This paper presents a design of a wireless read out system for tracking the frequency shift of the polymer coated piezoelectric micro electromechanical resonator due to gas absorption. The measure of this frequency shift indicates the percentage of a particular gas the sensor is exposed to. It is measured using an oscillator and an FPGA based frequency counter by employing the resonator as a frequency determining element in the oscillator. This system consists of a Gas Sensing Wireless Readout (GSWR) and an USB Wireless Transceiver (UWT). GSWR consists of an oscillator based on a trans-impedance sustaining amplifier, an FPGA based frequency readout, a sub 1GHz wireless transceiver and a micro controller. UWT can be plugged into the computer via USB port and function as a wireless module to transfer gas sensor data from GSWR to the computer through its USB port. GUI program running on the computer periodically polls for sensor data through UWT - GSWR wireless link, the response from GSWR is logged in a file for post processing as well as displayed on screen.

Keywords: gas sensor, GSWR, micromechanical system, UWT, volatile emissions

Procedia PDF Downloads 461

Authors: Shiuh-Jer Huang, Yun-Han Yeh

Abstract:

A four-wheel drive electric vehicle was built with hub DC motors and FPGA embedded control structure. A 40 steps manual adjusting motorcycle shock absorber was refitted with DC motor driving mechanism to construct as a semi-active suspension system. Accelerometer and potentiometer sensors are installed to measure the sprung mass acceleration and suspension system compression or rebound states for control purpose. An intelligent fuzzy logic controller was proposed to real-time search appropriate damping ratio based on vehicle running condition. Then, a robust fuzzy sliding mode controller (FSMC) is employed to regulate the target damping ratio of each wheel axis semi-active suspension system. Finally, different road surface conditions are chosen to evaluate the control performance of this semi-active suspension and compare with that of passive system based on wheel axis acceleration signal.

Keywords: acceleration, FPGA, Fuzzy sliding mode control, semi-active suspension

Procedia PDF Downloads 389

Authors: Arminder Singh Walia, Vineet Srivastava, Vivek Jain

Abstract:

In Electrical Discharge Machining (EDM) operations, the workpiece confers to the shape of the tool. Further, the cost of the tool contributes the maximum effect on total operation cost. Therefore, the shape and profile of the tool become highly significant. Thus, in this work, an attempt has been made to study the effect of process parameters on the shape of the tool. Copper has been used as the tool material for the machining of AISI 52100 die steel. The shape of the tool has been evaluated by determining the difference in out of roundness of tool before and after machining. Statistical model has been developed and significant process parameters have been identified which affect the shape of the tool. Optimum process parameters have been identified which minimizes the shape distortion.

Keywords: discharge current, flushing pressure, pulse-on time, pulse-off time, out of roundness, electrical discharge machining

Procedia PDF Downloads 261

Authors: Anand Prakash Dwivedi, Sounak Kumar Choudhury

Abstract:

Electric Discharge Machining (EDM) is a well-established and one of the most primitive unconventional manufacturing processes, that is used world-wide for the machining of geometrically complex or hard and electrically conductive materials which are extremely difficult to cut by any other conventional machining process. One of the major flaws, over all its advantages, is its very slow Material Removal Rate (MRR). In order to eradicate this slow machining rate, various researchers have proposed various methods like; providing rotational motion to the tool or work-piece or to both, mixing of conducting additives (such as SiC, Cr, Al, graphite etc) powders in the dielectric, providing vibrations to the tool or work-piece or to both etc. Present work is a comparative study of Rotational and Stationary Tool EDM, which deals with providing rotational motion to the copper tool for the machining of AISI D3 Tool Steel and the results have been compared with stationary tool EDM. It has been found that the tool rotation substantially increases the MRR up to 28%. The average surface finish increases around 9-10% by using the rotational tool EDM. The average tool wear increment is observed to be around 19% due to the tool rotation. Apart from this, the present work also focusses on the recast layer analysis, which are being re-deposited on the work-piece surface during the operation. The recast layer thickness is less in case of Rotational EDM and more for Stationary Tool EDM. Moreover, the cracking on the re-casted surface is also more for stationary tool EDM as compared with the rotational EDM.

Keywords: EDM, MRR, Ra, TWR

Procedia PDF Downloads 294

Authors: Shih-Ming Wang, Chun-Kai Yeh, Ming-Hwang Shie, Tai-Wei Lin, Chieh-Fu Chang

Abstract:

This paper introduces a FPGA-based baseband signals generator (BSG) of X-band transmitter developed by National Space Organization (NSPO), Taiwan, for earth observation. In order to gain more flexibility for various applications, a number of modulation schemes, QPSK, DeQPSK and 8PSK 4D-TCM are included. For micro satellite scenario, the maximum symbol rate is up to 150Mbsps, and the EVM is as low as 1.9%. For CubeSat scenario, the maximum symbol rate is up to 60Mbsps, and the EVM is less than 1.7%. The maximum data rates are 412.5Mbps and 165Mbps, respectively. Besides, triple modular redundancy (TMR) scheme is implemented in order to reduce single event effect (SEE) induced by radiation. Finally, the theoretical error performance is provided based on comprehensive analysis, especially when BER is lower and much lower than 10⁻⁶ due to low error bit requirement of modern high-resolution earth remote-sensing instruments.

Keywords: X-band transmitter, FPGA (Field-Programmable Gate Array), CubeSat, micro satellite

Procedia PDF Downloads 274

Authors: Hao Cheng, Zhiwu Wang, Guozheng Yan, Pingping Jiang, Shijia Qin, Shuai Kuang

Abstract:

Autofluorescence Imaging (AFI) is a technology for detecting early carcinogenesis of the gastrointestinal tract in recent years. Compared with traditional white light endoscopy (WLE), this technology greatly improves the detection accuracy of early carcinogenesis, because the colors of normal tissues are different from cancerous tissues. Thus, edge detection can distinguish them in grayscale images. In this paper, based on the traditional Sobel edge detection method, optimization has been performed on this method which considers the environment of the gastrointestinal, including adaptive threshold and morphological processing. All of the processes are implemented on our self-designed system based on the image sensor OV6930 and Field Programmable Gate Array (FPGA), The system can capture the gastrointestinal image taken by the lens in real time and detect edges. The final experiments verified the feasibility of our system and the effectiveness and accuracy of the edge detection algorithm.

Keywords: AFI, edge detection, adaptive threshold, morphological processing, OV6930, FPGA

Procedia PDF Downloads 204

Authors: S. J. Arif

Abstract:

In the presented technique, a simple method is given for accurate measurement and control of power frequency deviation. The sinusoidal signal for which the frequency deviation measurement is required is transformed to a low voltage level and passed through a zero crossing detector to convert it into a pulse train. Another stable square wave signal of 10 KHz is obtained using a crystal oscillator and decade dividing assemblies (DDA). These signals are combined digitally and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded to make them equally suitable for both control applications and display units. The developed circuit using discrete components has a resolution of 0.5 Hz and completes measurement within 20 ms. The realized circuit is simulated and synthesized using Verilog HDL and subsequently implemented on FPGA. The results of measurement on FPGA are observed on a very high resolution logic analyzer. These results accurately match the simulation results as well as the results of same circuit implemented with discrete components. The proposed system is suitable for accurate measurement and control of power frequency deviation.

Keywords: digital encoder for frequency measurement, frequency deviation measurement, measurement and control systems, power systems

Procedia PDF Downloads 351

Authors: Si Mon Kueh, Tom J. Kazmierski

Abstract:

There are about 1% of the world population suffering from the hidden disability known as epilepsy and major developing countries are not fully equipped to counter this problem. In order to reduce the inconvenience and danger of epilepsy, different methods have been researched by using a artificial neural network (ANN) classification to distinguish epileptic waveforms from normal brain waveforms. This paper outlines the aim of achieving massive ANN parallelization through a dedicated hardware using bit-serial processing. The design of this bit-serial Neural Processing Element (NPE) is presented which implements the functionality of a complete neuron using variable accuracy. The proposed design has been tested taking into consideration non-idealities of a hardware ANN. The NPE consists of a bit-serial multiplier which uses only 16 logic elements on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a look-up table. Arrays of NPEs can be driven by a single controller which executes the neural processing algorithm. In conclusion, the proposed compact NPE design allows the construction of complex hardware ANNs that can be implemented in a portable equipment that suits the needs of a single epileptic patient in his or her daily activities to predict the occurrences of impending tonic conic seizures.

Keywords: Artificial Neural Networks (ANN), bit-serial neural processor, FPGA, Neural Processing Element (NPE)

Procedia PDF Downloads 295

Authors: S. Ghorbani, N. I. Polushin

Abstract:

Vibration during machining process is crucial since it affects cutting tool, machine, and workpiece leading to a tool wear, tool breakage, and an unacceptable surface roughness. This paper applies a nonparametric statistical method, single decision tree (SDT), to identify factors affecting on vibration in machining process. Workpiece material (AISI 1045 Steel, AA2024 Aluminum alloy, A48-class30 Gray Cast Iron), cutting tool (conventional, cutting tool with holes in toolholder, cutting tool filled up with epoxy-granite), tool overhang (41-65 mm), spindle speed (630-1000 rpm), feed rate (0.05-0.075 mm/rev) and depth of cut (0.05-0.15 mm) were used as input variables, while vibration was the output parameter. It is concluded that workpiece material is the most important parameters for natural frequency followed by cutting tool and overhang.

Keywords: cutting condition, vibration, natural frequency, decision tree, CART algorithm

Procedia PDF Downloads 310

Authors: K. K. Soundra Pandian, Bhupendra Gupta

Abstract:

In the modern era, as the application data’s are massive and complex, it needs to be secured from the adversary attack. In this context, a non-recursive key based integrated spritz stream cipher with the circulant hash function using delayed feedback with carry shift register (d-FCSR) is proposed in this paper. The novelty of this proposed stream cipher algorithm is to engender the improved keystream using d-FCSR. The proposed algorithm is coded using Verilog HDL to produce dynamic binary key stream and implemented on commercially available FPGA device Virtex 5 xc5vlx110t-2ff1136. The implementation of stream cipher using d-FCSR on the FPGA device operates at a maximum frequency of 60.62 MHz. It achieved the data throughput of 492 Mbps and improved in terms of efficiency (throughput/area) compared to existing techniques. This paper also briefs the cryptanalysis of proposed circulant hash value based spritz stream cipher using d-FCSR is against the adversary attack on a hardware platform for the hardware based cryptography applications.

Keywords: cryptography, circulant function, field programmable gated array, hash value, spritz stream cipher

Procedia PDF Downloads 229

Authors: Tomyslav Sledevič, Artūras Serackis, Gintautas Tamulevičius, Dalius Navakauskas

Abstract:

This paper presents a comparative evaluation of features extraction algorithm for a real-time isolated word recognition system based on FPGA. The Mel-frequency cepstral, linear frequency cepstral, linear predictive and their cepstral coefficients were implemented in hardware/software design. The proposed system was investigated in the speaker-dependent mode for 100 different Lithuanian words. The robustness of features extraction algorithms was tested recognizing the speech records at different signals to noise rates. The experiments on clean records show highest accuracy for Mel-frequency cepstral and linear frequency cepstral coefficients. For records with 15 dB signal to noise rate the linear predictive cepstral coefficients give best result. The hard and soft part of the system is clocked on 50 MHz and 100 MHz accordingly. For the classification purpose, the pipelined dynamic time warping core was implemented. The proposed word recognition system satisfies the real-time requirements and is suitable for applications in embedded systems.

Keywords: isolated word recognition, features extraction, MFCC, LFCC, LPCC, LPC, FPGA, DTW

Procedia PDF Downloads 471

Authors: Y. Bai, M. Bodlak, V. Frolov, S. Huber, V. Jary, I. Konorov, D. Levit, J. Novy, D. Steffen, O. Subrt, M. Virius

Abstract:

Modern experiments in high energy physics impose great demands on the reliability, the efficiency, and the data rate of Data Acquisition Systems (DAQ). This contribution focuses on the development and deployment of the new communication library DIALOG for the intelligent, FPGA-based Data Acquisition System (iFDAQ) of the COMPASS experiment at CERN. The iFDAQ utilizing a hardware event builder is designed to be able to readout data at the maximum rate of the experiment. The DIALOG library is a communication system both for distributed and mixed environments, it provides a network transparent inter-process communication layer. Using the high-performance and modern C++ framework Qt and its Qt Network API, the DIALOG library presents an alternative to the previously used DIM library. The DIALOG library was fully incorporated to all processes in the iFDAQ during the run 2016. From the software point of view, it might be considered as a significant improvement of iFDAQ in comparison with the previous run. To extend the possibilities of debugging, the online monitoring of communication among processes via DIALOG GUI is a desirable feature. In the paper, we present the DIALOG library from several insights and discuss it in a detailed way. Moreover, the efficiency measurement and comparison with the DIM library with respect to the iFDAQ requirements is provided.

Keywords: data acquisition system, DIALOG library, DIM library, FPGA, Qt framework, TCP/IP

Procedia PDF Downloads 294

Authors: Noemia Gomes de Mattos de Mesquita, José Eduardo Ferreira de Oliveira, Arimatea Quaresma Ferraz

Abstract:

Stops to exchange cutting tool, to set up again the tool in a turning operation with CNC or to measure the workpiece dimensions have a direct influence on production. The premature removal of the cutting tool results in high cost of machining since the parcel relating to the cost of the cutting tool increases. On the other hand, the late exchange of cutting tool also increases the cost of production because getting parts out of the preset tolerances may require rework for its use when it does not cause bigger problems such as breaking of cutting tools or the loss of the part. Therefore, the right time to exchange the tool should be well defined when wanted to minimize production costs. When the flank wear is the limiting tool life, the time predetermination that a cutting tool must be used for the machining occurs within the limits of tolerance can be done without difficulty. This paper aims to show how the life of the cutting tool can be calculated taking into account the cutting parameters (cutting speed, feed and depth of cut), workpiece material, power of the machine, the dimensional tolerance of the part, the finishing surface, the geometry of the cutting tool and operating conditions of the machine tool, once known the parameters of Taylor algebraic structure. These parameters were raised for the ABNT 1038 steel machined with cutting tools of hard metal.

Keywords: machining, productions, cutting condition, design, manufacturing, measurement

Procedia PDF Downloads 614

Authors: Jun Wang, Tingcun Wei

Abstract:

The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.

Keywords: DPWM, digitally-controlled DC-DC switching converter, FPGA, PLL megafunction, time resolution

Procedia PDF Downloads 448

Authors: Chris M. Taylor, Ian Cook, Raul Alegre, Pedro Arrazola, Phil Spiers

Abstract:

Noteworthy results have been obtained in the turning and drilling of hardened high-strength steels using tungsten carbide based cutting tools. In a finish turning process, it was seen that surface roughness and tool flank wear followed very different trends against cutting time. The suggested explanation for this behaviour is that the profile cut into the workpiece surface is determined by the tool’s cutting edge profile. It is shown that the profile appearing on the cut surface changes rapidly over time, so the profile of the tool cutting edge should also be changing rapidly. Workpiece material adhered onto the cutting tool, which is also known as a built-up edge, is a phenomenon which could explain the observations made. In terms of tool damage modes, workpiece material adhesion is believed to have contributed to tool wear in examples provided from finish turning, thread turning and drilling. Additionally, evidence of tool fracture and tool abrasion were recorded.

Keywords: turning, drilling, adhesion, wear, hard steels

Procedia PDF Downloads 313

Authors: Jui-Pui Hung, Yu-Sheng Lai, Tzuo-Liang Luo, Kung-Da Wu, Yun-Ji Zhan

Abstract:

This study presented the investigation of the influence of the tool holder interface stiffness on the dynamic characteristics of a spindle tool system. The interface stiffness was produced by drawbar force on the tool holder, which tends to affect the spindle dynamics. In order to assess the influence of interface stiffness on the vibration characteristic of spindle unit, we first created a three dimensional finite element model of a high speed spindle system integrated with tool holder. The key point for the creation of FEM model is the modeling of the rolling interface within the angular contact bearings and the tool holder interface. The former can be simulated by a introducing a series of spring elements between inner and outer rings. The contact stiffness was calculated according to Hertz contact theory and the preload applied on the bearings. The interface stiffness of the tool holder was identified through the experimental measurement and finite element modal analysis. Current results show that the dynamic stiffness was greatly influenced by the tool holder system. In addition, variations of modal damping, static stiffness and dynamic stiffness of the spindle tool system were greatly determined by the interface stiffness of the tool holder which was in turn dependent on the draw bar force applied on the tool holder. Overall, this study demonstrates that identification of the interface characteristics of spindle tool holder is of very importance for the refinement of the spindle tooling system to achieve the optimum machining performance.

Keywords: dynamic stiffness, spindle-tool holder, interface stiffness, drawbar force

Procedia PDF Downloads 369

Authors: Adam Janásek, Marek Pagáč

Abstract:

The article is looking for an experimental determination of tool life tests for ceramic cutting inserts. Mentioned experimental determination should provide an added information about cutting process. The mechanism of tool wear, cutting temperature in machining, quality machined surface and machining process itself is the information, which are important for whole manufacturing process. Mainly, the roughness plays very important role in determining how a real object will interact with its environment. The main aim was to determine the number of machined inserts, tool life and micro-geometry, as well. On the basis of previous tests the tool-wear was measured at constant cutting parameter which is more typical for high volume manufacturing processes.

Keywords: ceramic, insert, machining, surface roughness, tool-life, tool-wear

Procedia PDF Downloads 466

Authors: S. Chockalingam, U. Natarajan, D. M. Santhoshsarang

Abstract:

Particle damping is a promising vibration attenuating technique in boring tool than other type of damping with minimal effect on the strength, rigidity and stiffness ratio of the machine tool structure. Due to the cantilever nature of boring tool holder in operations, it suffers chatter when the slenderness ratio of the tool gets increased. In this study, Copper-Stainless steel (SS) particles were packed inside the boring tool which acts as a damper. Damper suppresses chatter generated during machining and also improves the machining efficiency of the tool with better slenderness ratio. In the first approach of particle damping, combined Cu-SS particles were packed inside the vibrating tool, whereas Copper and Stainless steel particles were selected separately and packed inside another tool and their effectiveness was analysed in this simulation. This study reveals that the efficiency of finite element simulation of the boring tools when equipped with particles such as copper, stainless steel and a combination of both. In this study, the newly modified boring tool holder with particle damping was simulated using ANSYS12.0 with and without particles. The aim of this study is to enhance the structural rigidity through particle damping thus avoiding the occurrence of resonance in the boring tool during machining.

Keywords: boring bar, copper-stainless steel, chatter, particle damping

Procedia PDF Downloads 435

Authors: Amir Ngah, Masita Abdul Jalil, Zailani Abdullah

Abstract:

The aim of software maintenance is to maintain the software system in accordance with advancement in software and hardware technology. One of the early works on software maintenance is to extract information at higher level of abstraction. In this paper, we present the process of how to design an information extraction tool for software maintenance. The tool can extract the basic information from old program such as about variables, based classes, derived classes, objects of classes, and functions. The tool have two main part; the lexical analyzer module that can read the input file character by character, and the searching module which is user can get the basic information from existing program. We implemented this tool for a patterned sub-C++ language as an input file.

Keywords: extraction tool, software maintenance, reverse engineering, C++

Procedia PDF Downloads 463

Authors: Omar M. Elmabrouk

Abstract:

The cutting tool, in the high-speed machining process, is consistently dealing with high localized stress at the tool tip, tip temperature exceeds 800°C and the chip slides along the rake face. These conditions are affecting the tool wear, the cutting tool performances, the quality of the produced parts and the tool life. Therefore, a thin film coating on the cutting tool should be considered to improve the tool surface properties while maintaining its bulks properties. One of the general coating processes in applying thin film for hard coating purpose is PVD magnetron sputtering. In this paper, the prediction of the effects of PVD magnetron sputtering coating process parameters, sputter power in the range of (4.81-7.19 kW), bias voltage in the range of (50.00-300.00 Volts) and substrate temperature in the range of (281.08-600.00 °C), were studied using artificial neural network (ANN). The results were compared with previously published results using RSM model. It was found that the ANN is more accurate in prediction of tool hardness, and hence, it will not only improve the tool life of the tool but also significantly enhances the efficiency of the machining processes.

Keywords: artificial neural network, hardness, prediction, titanium aluminium nitrate coating

Procedia PDF Downloads 529