Search results for: memory acquisition
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 751

Search results for: memory acquisition

691 Dual-Network Memory Model for Temporal Sequences

Authors: Motonobu Hattori, Rina Suzuki

Abstract:

In neural networks, when new patters are learned by a network, they radically interfere with previously stored patterns. This drawback is called catastrophic forgetting. We have already proposed a biologically inspired dual-network memory model which can much reduce this forgetting for static patterns. In this model, information is first stored in the hippocampal network, and thereafter, it is transferred to the neocortical network using pseudopatterns. Because temporal sequence learning is more important than static pattern learning in the real world, in this study, we improve our conventional  dual-network memory model so that it can deal with temporal sequences without catastrophic forgetting. The computer simulation results show the effectiveness of the proposed dual-network memory model.  

Keywords: Catastrophic forgetting, dual-network, temporal sequences.

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690 Review and Experiments on SDMSCue

Authors: Ashraf Anwar

Abstract:

In this work, I present a review on Sparse Distributed Memory for Small Cues (SDMSCue), a variant of Sparse Distributed Memory (SDM) that is capable of handling small cues. I then conduct and show some cognitive experiments on SDMSCue to test its cognitive soundness compared to SDM. Small cues refer to input cues that are presented to memory for reading associations; but have many missing parts or fields from them. The original SDM failed to handle such a problem. SDMSCue handles and overcomes this pitfall. The main idea in SDMSCue; is the repeated projection of the semantic space on smaller subspaces; that are selected based on the input cue length and pattern. This process allows for Read/Write operations using an input cue that is missing a large portion. SDMSCue is augmented with the use of genetic algorithms for memory allocation and initialization. I claim that SDM functionality is a subset of SDMSCue functionality.

Keywords: Artificial intelligence, recall, recognition, SDM, SDMSCue.

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689 Parallel-computing Approach for FFT Implementation on Digital Signal Processor (DSP)

Authors: Yi-Pin Hsu, Shin-Yu Lin

Abstract:

An efficient parallel form in digital signal processor can improve the algorithm performance. The butterfly structure is an important role in fast Fourier transform (FFT), because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even though recent research which call as novel memory reference reduction methods (NMRRM) for FFT focus on reduce memory reference in twiddle factor, the data-dependent property still exists. In this paper, we propose a parallel-computing approach for FFT implementation on digital signal processor (DSP) which is based on data-independent property and still hold the property of low-memory reference. The proposed method combines final two steps in NMRRM FFT to perform a novel data-independent structure, besides it is very suitable for multi-operation-unit digital signal processor and dual-core system. We have applied the proposed method of radix-2 FFT algorithm in low memory reference on TI TMSC320C64x DSP. Experimental results show the method can reduce 33.8% clock cycles comparing with the NMRRM FFT implementation and keep the low-memory reference property.

Keywords: Parallel-computing, FFT, low-memory reference, TIDSP.

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688 Developing OMS in IHL

Authors: Suzana Basaruddin, Haryani Haron, Siti Arpah Noodin

Abstract:

Managing knowledge of research is one way to ensure just in time information and knowledge to support research strategist and activities. Unfortunately researcher found the vital research knowledge in IHL (Institutions of Higher Learning) are scattered, unstructured and unorganized. Aiming on lay aside conceptual foundations for understanding and developing OMS (Organizational Memory System) to facilitate research in IHL, this research revealed ten factors contributed to the needs of research in the IHL and seven internal challenges of IHL in promoting research to their academic members. This study then suggested a comprehensive support of managing research knowledge using Organizational Memory System (OMS). Eight OMS characteristics to support research were identified. Finally the initial work in designing OMS was projected using knowledge taxonomy. All analysis is derived from pertinent research paper related to research in IHL and OMS. Further study can be conducted to validate and verify results presented.

Keywords: corporate memory, Institutions of Higher Learning, organizational memory system, research

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687 3D Network-on-Chip with on-Chip DRAM: An Empirical Analysis for Future Chip Multiprocessor

Authors: Thomas Canhao Xu, Bo Yang, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

Abstract:

With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.

Keywords: 3D integration, network-on-chip, memory-on-chip, DRAM, chip multiprocessor.

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686 VLSI Design of 2-D Discrete Wavelet Transform for Area-Efficient and High-Speed Image Computing

Authors: Mountassar Maamoun, Mehdi Neggazi, Abdelhamid Meraghni, Daoud Berkani

Abstract:

This paper presents a VLSI design approach of a highspeed and real-time 2-D Discrete Wavelet Transform computing. The proposed architecture, based on new and fast convolution approach, reduces the hardware complexity in addition to reduce the critical path to the multiplier delay. Furthermore, an advanced twodimensional (2-D) discrete wavelet transform (DWT) implementation, with an efficient memory area, is designed to produce one output in every clock cycle. As a result, a very highspeed is attained. The system is verified, using JPEG2000 coefficients filters, on Xilinx Virtex-II Field Programmable Gate Array (FPGA) device without accessing any external memory. The resulting computing rate is up to 270 M samples/s and the (9,7) 2-D wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out memory) with 256×256 image size. In this way, the developed design requests reduced memory and provide very high-speed processing as well as high PSNR quality.

Keywords: Discrete Wavelet Transform (DWT), Fast Convolution, FPGA, VLSI.

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685 An Optimized Multi-block Method for Turbulent Flows

Authors: M. Goodarzi, P. Lashgari

Abstract:

A major part of the flow field involves no complicated turbulent behavior in many turbulent flows. In this research work, in order to reduce required memory and CPU time, the flow field was decomposed into several blocks, each block including its special turbulence. A two dimensional backward facing step was considered here. Four combinations of the Prandtl mixing length and standard k- E models were implemented as well. Computer memory and CPU time consumption in addition to numerical convergence and accuracy of the obtained results were mainly investigated. Observations showed that, a suitable combination of turbulence models in different blocks led to the results with the same accuracy as the high order turbulence model for all of the blocks, in addition to the reductions in memory and CPU time consumption.

Keywords: Computer memory, CPU time, Multi-block method, Turbulence modeling.

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684 Effectiveness of Working Memory Training on Cognitive Flexibility

Authors: Leila Maleki, Ezatollah Ahmadi

Abstract:

The aim of this study was to investigate the effectiveness of memory training exercise on cognitive flexibility. The method of this study was experimental. The statistical population selected 40 students 14 years old, samples were chosen by available sampling method and then they were replaced in experimental (training program) group and control group randomly and answered to Wisconsin Card Sorting Test; covariance test results indicated that there were a significant in post-test scores of experimental group (p<0.005).

Keywords: Cognitive flexibility, working memory exercises, problem solving, reaction time.

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683 Spatial Abilities, Memory and Intellect of Drivers with Different Level of Professional Experience

Authors: N. Khon, A. Kim, T. Mukhitdinova

Abstract:

The aim of this research was to reveal the link between mental variables, such as spatial abilities, memory, intellect and professional experience of drivers. Participants were allocated to four groups: no experience, inexperienced, skilled and professionals (total 85 participants). The level of ability for spatial navigation and indicator of nonverbal memory grow along the process of accumulation of driving experience. At high levels of driving experience, this tendency is especially noticeable. The professionals having personal achievements in driving (racing) differ from skilled drivers in better feeling of direction, which is specific for them not just in a short-term situation of an experimental task, but also in life-size perspective. The level of ability of mental rotation does not grow with the growth of driving experience, which confirms the multiple intelligence theory according to which spatial abilities represent specific, other than logical intelligence type of intellect. The link between spatial abilities, memory, intellect and professional experience of drivers seems to be different relating spatial navigation or mental rotation as different kinds of spatial abilities.

Keywords: Memory, spatial abilities, intellect, drivers.

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682 Tests and Measurements of Image Acquisition Characteristics for Image Sensors

Authors: Seongsoo Lee, Jong-Bae Lee, Wookkang Lee, Duyen Hai Pham

Abstract:

In the image sensors, the acquired image often differs from the real image in luminance or chrominance due to fabrication defects or nonlinear characteristics, which often lead to pixel defects or sensor failure. Therefore, the image acquisition characteristics of image sensors should be measured and tested before they are mounted on the target product. In this paper, the standardized test and measurement methods of image sensors are introduced. It applies standard light source to the image sensor under test, and the characteristics of the acquired image is compared with ideal values.

Keywords: Image Sensor, Image Acquisition Characteristics, Defect, Failure, Standard, Test, Measurement.

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681 Performance Evaluation of Neural Network Prediction for Data Prefetching in Embedded Applications

Authors: Sofien Chtourou, Mohamed Chtourou, Omar Hammami

Abstract:

Embedded systems need to respect stringent real time constraints. Various hardware components included in such systems such as cache memories exhibit variability and therefore affect execution time. Indeed, a cache memory access from an embedded microprocessor might result in a cache hit where the data is available or a cache miss and the data need to be fetched with an additional delay from an external memory. It is therefore highly desirable to predict future memory accesses during execution in order to appropriately prefetch data without incurring delays. In this paper, we evaluate the potential of several artificial neural networks for the prediction of instruction memory addresses. Neural network have the potential to tackle the nonlinear behavior observed in memory accesses during program execution and their demonstrated numerous hardware implementation emphasize this choice over traditional forecasting techniques for their inclusion in embedded systems. However, embedded applications execute millions of instructions and therefore millions of addresses to be predicted. This very challenging problem of neural network based prediction of large time series is approached in this paper by evaluating various neural network architectures based on the recurrent neural network paradigm with pre-processing based on the Self Organizing Map (SOM) classification technique.

Keywords: Address, data set, memory, prediction, recurrentneural network.

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680 Consistency Model and Synchronization Primitives in SDSMS

Authors: Dalvinder Singh Dhaliwal, Parvinder S. Sandhu, S. N. Panda

Abstract:

This paper is on the general discussion of memory consistency model like Strict Consistency, Sequential Consistency, Processor Consistency, Weak Consistency etc. Then the techniques for implementing distributed shared memory Systems and Synchronization Primitives in Software Distributed Shared Memory Systems are discussed. The analysis involves the performance measurement of the protocol concerned that is Multiple Writer Protocol. Each protocol has pros and cons. So, the problems that are associated with each protocol is discussed and other related things are explored.

Keywords: Distributed System, Single owner protocol, Multiple owner protocol

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679 A Parallel Architecture for the Real Time Correction of Stereoscopic Images

Authors: Zohir Irki, Michel Devy

Abstract:

In this paper, we will present an architecture for the implementation of a real time stereoscopic images correction's approach. This architecture is parallel and makes use of several memory blocs in which are memorized pre calculated data relating to the cameras used for the acquisition of images. The use of reduced images proves to be essential in the proposed approach; the suggested architecture must so be able to carry out the real time reduction of original images.

Keywords: Image reduction, Real-time correction, Parallel architecture, Parallel treatment.

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678 The Investigation of the Possible Connections between Acculturation and the Acquisition of a Second Language on Libyan Teenage Students

Authors: Hamza M. A. Muftah

Abstract:

The study investigates the possible connections between acculturation and the acquisition of a second language on Libyan teenage students in Australia. Specifically, the study examined how various socio-psychological variables influenced English oral proficiency (oral communicative competence and native-like pronunciation) of the participants. In addition, it looked at whether or not SLA affects acculturation towards the target language group. This is achieved by analysing data obtained from semi-structured interviews and oral proficiency interviews. The present study found a definite link between the students’ acculturation process and their oral communicative competence but not native-like pronunciation. The results also provided evidence that SLL process has an impact on integration into the host society as well as the acquisition of a second language culture. Yet, it did not draw a clear conclusion with respect to how such a process affects these aspects.

Keywords: Acculturation, Native-like pronunciation, Oral communicative competence, Second language acquisition, Second language learners.

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677 Enhanced Disk-Based Databases Towards Improved Hybrid In-Memory Systems

Authors: Samuel Kaspi, Sitalakshmi Venkatraman

Abstract:

In-memory database systems are becoming popular due to the availability and affordability of sufficiently large RAM and processors in modern high-end servers with the capacity to manage large in-memory database transactions. While fast and reliable inmemory systems are still being developed to overcome cache misses, CPU/IO bottlenecks and distributed transaction costs, disk-based data stores still serve as the primary persistence. In addition, with the recent growth in multi-tenancy cloud applications and associated security concerns, many organisations consider the trade-offs and continue to require fast and reliable transaction processing of diskbased database systems as an available choice. For these organizations, the only way of increasing throughput is by improving the performance of disk-based concurrency control. This warrants a hybrid database system with the ability to selectively apply an enhanced disk-based data management within the context of inmemory systems that would help improve overall throughput. The general view is that in-memory systems substantially outperform disk-based systems. We question this assumption and examine how a modified variation of access invariance that we call enhanced memory access, (EMA) can be used to allow very high levels of concurrency in the pre-fetching of data in disk-based systems. We demonstrate how this prefetching in disk-based systems can yield close to in-memory performance, which paves the way for improved hybrid database systems. This paper proposes a novel EMA technique and presents a comparative study between disk-based EMA systems and in-memory systems running on hardware configurations of equivalent power in terms of the number of processors and their speeds. The results of the experiments conducted clearly substantiate that when used in conjunction with all concurrency control mechanisms, EMA can increase the throughput of disk-based systems to levels quite close to those achieved by in-memory system. The promising results of this work show that enhanced disk-based systems facilitate in improving hybrid data management within the broader context of in-memory systems.

Keywords: Concurrency control, disk-based databases, inmemory systems, enhanced memory access (EMA).

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676 Concurrent Approach to Data Parallel Model using Java

Authors: Bala Dhandayuthapani Veerasamy

Abstract:

Parallel programming models exist as an abstraction of hardware and memory architectures. There are several parallel programming models in commonly use; they are shared memory model, thread model, message passing model, data parallel model, hybrid model, Flynn-s models, embarrassingly parallel computations model, pipelined computations model. These models are not specific to a particular type of machine or memory architecture. This paper expresses the model program for concurrent approach to data parallel model through java programming.

Keywords: Concurrent, Data Parallel, JDK, Parallel, Thread

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675 In vivo Histomorphometric and Corrosion Analysis of Ti-Ni-Cr Shape Memory Alloys in Rabbits

Authors: T. Ahmed, Z. Butt, M. Ali, S. Attiq, M. Ali

Abstract:

A series of Ti based shape memory alloys with composition of Ti50Ni49Cr1, Ti50Ni47Cr3 and Ti50Ni45Cr5 were developed by vacuum arc-melting under a purified argon atmosphere. The histometric and corrosion evaluation of Ti-Ni-Cr shape memory alloys have been considered in this research work. The alloys were developed by vacuum arc melting and implanted subcutaneously in rabbits for 4, 8 and 12 weeks. Metallic implants were embedded in order to determine the outcome of implantation on histometric and corrosion evaluation of Ti-Ni-Cr metallic strips. Encapsulating membrane formation around the alloys was minimal in the case of all materials. After histomorphometric analyses it was possible to demonstrate that there were no statistically significant differences between the materials. Corrosion rate was also determined in this study which is within acceptable range. The results showed the Ti- Ni-Cr alloy was neither cytotoxic, nor have any systemic reaction on living system in any of the test performed. Implantation shows good compatibility and a potential of being used directly in vivo system.

Keywords: Shape memory alloy, Ti-Ni-Fe, histomorphometric, corrosion.

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674 Analysis of Performance of 3T1D Dynamic Random-Access Memory Cell

Authors: Nawang Chhunid, Gagnesh Kumar

Abstract:

On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore’s law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated diode (D1) acts as a storage device and also as an amplifier, which leads to fast read access. Due to its high tolerance to process variation, high density, and low cost of memory as compared to 6T SRAM cell, it is universally used by the advanced microprocessor for on chip data and program memory. In the present paper, it has been shown that 3T1D DRAM cell can perform better in terms of fast read access as compared to 6T, 4T, 3T SRAM cells, respectively.

Keywords: DRAM cell, read access time, tanner EDA tool write access time and retention time, average power dissipation.

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673 A Tabu Search Heuristic for Scratch-Pad Memory Management

Authors: Maha Idrissi Aouad, Rene Schott, Olivier Zendra

Abstract:

Reducing energy consumption of embedded systems requires careful memory management. It has been shown that Scratch- Pad Memories (SPMs) are low size, low cost, efficient (i.e. energy saving) data structures directly managed at the software level. In this paper, the focus is on heuristic methods for SPMs management. A method is efficient if the number of accesses to SPM is as large as possible and if all available space (i.e. bits) is used. A Tabu Search (TS) approach for memory management is proposed which is, to the best of our knowledge, a new original alternative to the best known existing heuristic (BEH). In fact, experimentations performed on benchmarks show that the Tabu Search method is as efficient as BEH (in terms of energy consumption) but BEH requires a sorting which can be computationally expensive for a large amount of data. TS is easy to implement and since no sorting is necessary, unlike BEH, the corresponding sorting time is saved. In addition to that, in a dynamic perspective where the maximum capacity of the SPM is not known in advance, the TS heuristic will perform better than BEH.

Keywords: Energy consumption, memory allocation management, optimization, tabu search heuristic.

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672 Performance Analysis of an Adaptive Threshold Hybrid Double-Dwell System with Antenna Diversity for Acquisition in DS-CDMA Systems

Authors: H. Krouma, M. Barkat, K. Kemih, M. Benslama, Y. Yacine

Abstract:

In this paper, we consider the analysis of the acquisition process for a hybrid double-dwell system with antenna diversity for DS-CDMA (direct sequence-code division multiple access) using an adaptive threshold. Acquisition systems with a fixed threshold value are unable to adapt to fast varying mobile communications environments and may result in a high false alarm rate, and/or low detection probability. Therefore, we propose an adaptively varying threshold scheme through the use of a cellaveraging constant false alarm rate (CA-CFAR) algorithm, which is well known in the field of radar detection. We derive exact expressions for the probabilities of detection and false alarm in Rayleigh fading channels. The mean acquisition time of the system under consideration is also derived. The performance of the system is analyzed and compared to that of a hybrid single dwell system.

Keywords: Adaptive threshold, hybrid double-dwell system, CA-CFAR algorithm, DS-CDMA.

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671 Benchmarking: Performance on ALPS and Formosa Clusters

Authors: Chih-Wei Hsieh, Chau-Yi Chou, Sheng-HsiuKuo, Tsung-Che Tsai, I-Chen Wu

Abstract:

This paper presents the benchmarking results and performance evaluation of differentclustersbuilt atthe National Center for High-Performance Computingin Taiwan. Performance of processor, memory subsystem andinterconnect is a critical factor in the overall performance of high performance computing platforms. The evaluation compares different system architecture and software platforms. Most supercomputer used HPL to benchmark their system performance, in accordance with the requirement of the TOP500 List. In this paper we consider system memory access factors that affect benchmark performance, such as processor and memory performance.We hope these works will provide useful information for future development and construct cluster system.

Keywords: Performance Evaluation, Benchmarking and High-Performance Computing

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670 Association of Sensory Processing and Cognitive Deficits in Children with Autism Spectrum Disorders – Pioneer Study in Saudi Arabia

Authors: Rana M. Zeina, Laila AL-Ayadhi, Shahid Bashir

Abstract:

The association between sensory problems and cognitive abilities has been studied in individuals with Autism Spectrum Disorders (ASDs). In this study, we used a Neuropsychological Test to evaluate memory and attention in ASDs children with sensory problems compared to the ASDs children without sensory problems. Four visual memory tests of Cambridge Neuropsychological Test Automated Battery (CANTAB) including Big/little circle (BLC), Simple Reaction Time (SRT) Intra /Extra dimensional set shift (IED), Spatial recognition memory (SRM), were administered to 14 ASDs children with sensory problems compared to 13 ASDs without sensory problems aged 3 to 12 with IQ of above 70. ASDs individuals with sensory problems performed worse than the ASDs group without sensory problems on comprehension, learning, reversal and simple reaction time tasks, and no significant difference between the two groups was recorded in terms of the visual memory and visual comprehension tasks. The findings of this study suggest that ASDs children with sensory problems are facing deficits in learning, comprehension, reversal, and speed of response to a stimulus.

Keywords: Visual memory, Attention, Autism Spectrum Disorders (ASDs).

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669 A Probabilistic View of the Spatial Pooler in Hierarchical Temporal Memory

Authors: Mackenzie Leake, Liyu Xia, Kamil Rocki, Wayne Imaino

Abstract:

In the Hierarchical Temporal Memory (HTM) paradigm the effect of overlap between inputs on the activation of columns in the spatial pooler is studied. Numerical results suggest that similar inputs are represented by similar sets of columns and dissimilar inputs are represented by dissimilar sets of columns. It is shown that the spatial pooler produces these results under certain conditions for the connectivity and proximal thresholds. Following the discussion of the initialization of parameters for the thresholds, corresponding qualitative arguments about the learning dynamics of the spatial pooler are discussed.

Keywords: Hierarchical Temporal Memory, HTM, Learning Algorithms, Machine Learning, Spatial Pooler.

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668 English Classroom for SLA of Students and Small and Medium Entrepreneurs in Thailand

Authors: S. Yordchim, G. Anugkakul, T. Gibbs

Abstract:

The English competence of Thai people was examined in the context of knowledge of English in everyday life for Small and Medium Entrepreneurs (SMEs), and also integrated with Second language acquisition (SLA) students’ classroom. Second language acquisition was applied to the results of the questionnaires and interview forms. Levels of the need on English used for SME entrepreneurs in Thailand, satisfaction on joining the street classroom project were shown to be significantly high for some certain language functions and satisfaction. Finding suggests that the language functions on etiquette for professional use is essential and useful because lesson learned can be used in the real situation for their career. Implications for the climate of the street classroom are discussed.

Keywords: English classroom, second language acquisition, Small and Medium Entrepreneurs, Thai students.

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667 Accurate Position Electromagnetic Sensor Using Data Acquisition System

Authors: Z. Ezzouine, A. Nakheli

Abstract:

This paper presents a high position electromagnetic sensor system (HPESS) that is applicable for moving object detection. The authors have developed a high-performance position sensor prototype dedicated to students’ laboratory. The challenge was to obtain a highly accurate and real-time sensor that is able to calculate position, length or displacement. An electromagnetic solution based on a two coil induction principal was adopted. The HPESS converts mechanical motion to electric energy with direct contact. The output signal can then be fed to an electronic circuit. The voltage output change from the sensor is captured by data acquisition system using LabVIEW software. The displacement of the moving object is determined. The measured data are transmitted to a PC in real-time via a DAQ (NI USB -6281). This paper also describes the data acquisition analysis and the conditioning card developed specially for sensor signal monitoring. The data is then recorded and viewed using a user interface written using National Instrument LabVIEW software. On-line displays of time and voltage of the sensor signal provide a user-friendly data acquisition interface. The sensor provides an uncomplicated, accurate, reliable, inexpensive transducer for highly sophisticated control systems.

Keywords: Electromagnetic sensor, data acquisition, accurately, position measurement.

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666 The Relationship between Citizenship Acquisition and Ethnic Identity of Immigrant Women in Taiwan

Authors: Yuan-Yu Chiang, Yu-Han Tseng, Chin-Chen Wen

Abstract:

In the last few decades, many southeast-Asia women migrate to Taiwan by marriage, and it usually takes several years for them to acquire Taiwanese citizenship. This study investigates the relationship between their citizenship acquisition and whether they develop Taiwanese identities, and how does it affect their ethnical identity towards their original ethnics. Furthermore, the present study also explores that whether citizenship acquisition help the immigrant women to explore the host society further and make commitment to it, or the identification towards mainstream Taiwanese society is only symbolic and superficial? One hundred and ninety-two immigrant women were measured using Multigroup Ethnic Identity Measure-Revised and a global 10-point ethnic identity question. Correlation tests, t-test, and hierarchical regression were performed to answer the above questions. The results revealed that citizenship acquisition does help immigrant women to identify with Taiwanese society, but it does not affect how they identify with their own ethnics. Furthermore, the results also indicated that acquiring citizenship would not help these immigrant women become involved in deeper cultural exploration of Taiwan nor would it encourage them to make commitments to the host society.

Keywords: Immigrants, international marriage, ethnic identity, Taiwan.

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665 Switching Behaviors of TiN/HfOx/Pt Based RRAM

Authors: B. B. Weng, Z. Fang, Z. X. Chen, X. P. Wang, G. Q. Lo, D. L. Kwong

Abstract:

Resistive Random Access Memory (RRAM) had received great amount of attention from various research efforts in recent years, owing to its promising performance as a next generation memory device. In this paper, samples based on TiN/HfOx/Pt stack were prepared and its electrical switching behaviors were characterized and discussed in brief.

Keywords: HfOx, resistive switching, RRAM.

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664 Rural Women’s Skill Acquisition in the Processing of Locust Bean in Ipokia Local Government Area of Ogun State, Nigeria

Authors: A. A. Adekunle, A. M. Omoare, W. O. Oyediran

Abstract:

This study was carried out to assess rural women’s skill acquisition in the processing of locust bean in Ipokia Local Government Area of Ogun State, Nigeria. Simple random sampling technique was used to select 90 women locust bean processors for this study. Data were analyzed with descriptive statistics and Pearson Product Moment Correlation. The result showed that the mean age of respondents was 40.72 years. Most (70.00%) of the respondents were married. The mean processing experience was 8.63 years. 93.30% of the respondents relied on information from fellow locust beans processors and friends. All (100%) the respondents did not acquire improved processing skill through trainings and workshops. It can be concluded that the rural women’s skill acquisition on modernized processing techniques was generally low. It is hereby recommend that the rural women processors should be trained by extension service providers through series of workshops and seminars on improved processing techniques.

Keywords: Locust bean, processing, skill acquisition, rural women.

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663 Crossover Memories and Code-Switching in the Narratives of Arabic-Hebrew and Hebrew-English Bilingual Adults in Israel

Authors: Amani Jaber-Awida

Abstract:

This study examines two bilingual phenomena in the narratives of Arabic Hebrew and Hebrew-English bilingual adults in Israel: CO memories and code-switching (CS). The study examined these phenomena in the context of autobiographical memory, using a cue word technique. Student experimenters held two sessions in the homes of the participants. In separate language sessions, the participant was asked to look first at each of 16 cue words and then to state a concrete memory. After stating the memory, participants reported whether their memories were in the same language of the experiment session or different. Memories were classified as ‘Crossovers’ (CO) or ‘Same Language’ (SL) according to participants' self-reports. Participants were also required to elaborate about the setting, interlocutors and other languages involved in the specific memory. Beyond replicating the procedure of cuing technique, one memory from a specific lifespan period was chosen per participant, and the participant was required to provide further details about it. For the more detailed memories, CS count was conducted. Both bilingual groups confirmed the Reminiscence Bump phenomenon, retrieving more memories in the 10-30 age period. CO memories prevailed in second language sessions (L2). Same language memories were more abundant in first language sessions (L1). Higher CS frequency was found in L2 sessions. Finally, as predicted, 'individual' CS was prevalent in L2 sessions, but 'community-based' CS was not higher in L1 sessions. The two bilingual measures in this study, crossovers, and CS came from different research traditions, the former from an experimental paradigm in the psychology of autobiographical memory based on self-reported judgments, the latter a behavioral measure from linguistics. This merger of approaches offers new insight into the field of bilingual autobiographical memory. In addition, the study attempted to shed light on the investigation of motivations for CS, beginning with Walters’ SPPL Model and concluding with a distinction between ‘community-based’ and individual motivations.

Keywords: Autobiographical memory, code-switching, crossover memories, reminiscence bump.

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662 Analysis of Multilayer Neural Network Modeling and Long Short-Term Memory

Authors: Danilo López, Nelson Vera, Luis Pedraza

Abstract:

This paper analyzes fundamental ideas and concepts related to neural networks, which provide the reader a theoretical explanation of Long Short-Term Memory (LSTM) networks operation classified as Deep Learning Systems, and to explicitly present the mathematical development of Backward Pass equations of the LSTM network model. This mathematical modeling associated with software development will provide the necessary tools to develop an intelligent system capable of predicting the behavior of licensed users in wireless cognitive radio networks.

Keywords: Neural networks, multilayer perceptron, long short-term memory, recurrent neuronal network, mathematical analysis.

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