Search results for: voltage output

Authors: Sanguk Nam, Van Ha Nguyen, Hanjung Song

Abstract:

For low-power applications such as adapters for portable devices and USB chargers, the primary side regulation (PSR) fly-back converter is widely used in lieu of the conventional fly-back converter using opto-coupler because of its simpler structure and lower cost. In the literature, there has been studies focusing on the design of PSR circuit; however, the conventional sensing method in PSR circuit using RC delay has a lower accuracy as compared to the conventional fly-back converter using opto-coupler. In this paper, we propose a novel PWM/PFM controller using new sensing technique for the PSR fly-back converter which can control an accurate output voltage. The conventional PSR circuit can sense the output voltage information from the auxiliary winding to regulate the duty cycle of the clock that control the output voltage. In the sensing signal waveform, there has two transient points at time the voltage equals to Vout+VD and Vout, respectively. In other to sense the output voltage, the PSR circuit must detect the time at which the current of the diode at the output equals to zero. In the conventional PSR flyback-converter, the sensing signal at this time has a non-sharp-negative slope that might cause a difficulty in detecting the output voltage information since a delay of sensing signal or switching clock may exist which brings out an unstable operation of PSR fly-back converter. In this paper instead of detecting output voltage at a non-sharp-negative slope, a sharp-positive slope is used to sense the proper information of the output voltage. The proposed PRS circuit consists of a saw-tooth generator, a summing circuit, a sample and hold circuit and a peak detector. Besides, there is also the start-up circuit which protects the chip from high surge current when the converter is turned on. Additionally, to reduce the standby power loss, a second mode which operates in a low frequency is designed beside the main mode at high frequency. In general, the operation of the proposed PSR circuit can be summarized as following: At the time the output information is sensed from the auxiliary winding, a saw-tooth signal from the saw-tooth generator is generated. Then, both of these signals are summed using a summing circuit. After this process, the slope of the peak of the sensing signal at the time diode current is zero becomes positive and sharp that make the peak easy to detect. The output of the summing circuit then is fed into a peak detector and the sample and hold circuit; hence, the output voltage can be properly sensed. By this way, we can sense more accurate output voltage information and extend margin even circuit is delayed or even there is the existence of noise by using only a simple circuit structure as compared with conventional circuits while the performance can be sufficiently enhanced. Circuit verification was carried out using 0.35μm 700V Magnachip process. The simulation result of sensing signal shows a maximum error of 5mV under various load and line conditions which means the operation of the converter is stable. As compared to the conventional circuit, we achieved very small error only used analog circuits compare with conventional circuits. In this paper, a PWM/PFM controller using a simple and effective sensing method for PSR fly-back converter has been presented in this paper. The circuit structure is simple as compared with the conventional designs. The gained results from simulation confirmed the idea of the design

Keywords: primary side regulation, PSR, sensing technique, peak detector, PWM/PFM control, fly-back converter

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Authors: Spyridon Nikolaidis

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A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, inverter modeling, transistor current mode, timing model

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Authors: I Made Ginarsa, Agung Budi Muljono, I Made Ari Nrartha

Abstract:

Transient voltage response appears in power system operation when an additional loading is forced to load bus of power systems. In this research, improvement of transient voltage response is done by using power system stabilizer-static var compensator (PSS-SVC) based on adaptive neuro-fuzzy inference system (ANFIS)-algorithm. The main function of the PSS is to add damping component to damp rotor oscillation through automatic voltage regulator (AVR) and excitation system. Learning process of the ANFIS is done by using off-line method where data learning that is used to train the ANFIS model are obtained by simulating the PSS-SVC conventional. The ANFIS model uses 7 Gaussian membership functions at two inputs and 49 rules at an output. Then, the ANFIS-PSS and ANFIS-SVC models are applied to power systems. Simulation result shows that the response of transient voltage is improved with settling time at the time of 4.25 s.

Keywords: improvement, transient voltage, PSS-SVC, ANFIS, settling time

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Authors: Dhivya Balakrishnan, Dhamodharan Shanmugam

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Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity requiring a great number of power devices and passive components, and a rather complex control circuitry. This paper proposes a single-phase seven-level inverter for grid connected PV systems, With a novel pulse width-modulated (PWM) control scheme. Three reference signals that are identical to each other with an offset that is equivalent to the amplitude of the triangular carrier signal were used to generate the PWM signals. The inverter is capable of producing seven levels of output-voltage levels from the dc supply voltage. This paper proposes a new multilevel inverter topology using an H-bridge output stage with two bidirectional auxiliary switches. The new topology produces a significant reduction in the number of power devices and capacitors required to implement a multilevel output using the asymmetric cascade configuration.

Keywords: asymmetric cascade configuration, H-Bridge, multilevel inverter, Pulse Width Modulation (PWM)

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Authors: Maryam Ebrahimpour, Amir Ebrahimi

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This paper presents the steady-state amplitude analysis of MOS Colpitts oscillator with short channel device. The proposed method is based on a large signal analysis and the nonlinear differential equations that govern the oscillator circuit behaviour. Also, the short channel effects are considered in the proposed analysis and analytical equations for finding the steady-state oscillation amplitude are derived. The output voltage calculated from this analysis is in excellent agreement with simulations for a wide range of circuit parameters.

Keywords: colpitts oscillator, CMOS, electronics, circuits

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Authors: Monika Rawat, Rahul Kumar

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Input output Buffer Information Specification (IBIS) models are used for describing the analog behavior of the Input Output (I/O) buffers of a digital device. They are widely used to perform signal integrity analysis. Advantages of using IBIS models include simple structure, IP protection and fast simulation time with reasonable accuracy. As design complexity of driver and receiver increases, capturing exact behavior from transistor level model into IBIS model becomes an essential task to achieve better accuracy. In this paper, an improvement in existing methodology of generating IBIS model for complex I/O interfaces such as Inter-Integrated Circuit (I2C) and Low Voltage Differential Signaling (LVDS) is proposed. Furthermore, the accuracy and computational performance of standard method and proposed approach with respect to SPICE are presented. The investigations will be useful to further improve the accuracy of IBIS models and to enhance their wider acceptance.

Keywords: IBIS, signal integrity, open-drain buffer, low voltage differential signaling, behavior modelling, transient simulation

Procedia PDF Downloads 163

Authors: Bo Bae Song, Byung Seok Lee, Hyun young Kim, Chung Kwang Lee, Yong Seo Koo

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This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3, and D4).

Keywords: ESD, SCR, holding voltage, latch-up

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Authors: Atabak Faramarzpour, Mohsen Mohammadian

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In this article, we introduce the stability of power system voltage and state DG power plants placement and its effect on improving voltage security margin in radial distribution networks. For this purpose, first, important definitions in voltage stability area such as small and big voltage disturbances, instability, and voltage collapse, and voltage security definitions are stated. Then, according to voltage collapse time, voltage stability is classified and each one's characteristics are stated.

Keywords: DG power plants, evaluation, voltage security, radial distribution networks

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Authors: Milad Kaboli

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A new CMOS low voltage current-mode four-quadrant analog multiplier based on the squarer circuit with voltage output is presented. The proposed circuit is composed of a pair of current subtractors, a pair differential-input V-I converters and a pair of voltage squarers. The circuit was simulated using HSPICE simulator in standard 0.18 μm CMOS level 49 MOSIS (BSIM3 V3.2 SPICE-based). Simulation results show the performance of the proposed circuit and experimental results are given to confirm the operation. This topology of multiplier results in a high-frequency capability with low power consumption. The multiplier operates for a power supply ±1.2V. The simulation results of analog multiplier demonstrate a THD of 0.65% in 10MHz, a −3dB bandwidth of 1.39GHz, and a maximum power consumption of 7.1mW.

Keywords: analog processing circuit, WTA, LTA, low voltage

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Authors: Mansa Radhakrishnan, Anwar Ali, Muhammad Rizwan Mughal

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Many universities around the world are working on modular and low budget architecture of small spacecraft to reduce the development cost of the overall system. This paper focuses on the design of a modular solar power harvesting system for a hexagonal-shaped small satellite. The designed solar power harvesting systems are composed of solar panels and power converter subsystems. The solar panel is composed of solar cells mounted on the external face of the printed circuit board (PCB), while the electronic components of power conversion are mounted on the interior side of the same PCB. The solar panel with dimensions 16.5cm × 99cm is composed of 36 solar cells (each solar cell is 4cm × 7cm) divided into four parallel banks where each bank consists of 9 solar cells. The output voltage of a single solar cell is 2.14V, and the combined output voltage of 9 series connected solar cells is around 19.3V. The output voltage of the solar panel is boosted to the satellite power distribution bus voltage level (28V) by a boost converter working on a constant voltage maximum power point tracking (MPPT) technique. The solar panel module is an eight-layer PCB having embedded coil in 4 internal layers. This coil is used to control the attitude of the spacecraft, which consumes power to generate a magnetic field and rotate the spacecraft. As power converter and distribution subsystem components are mounted on the PCB internal layer, therefore it is mandatory to do thermal analysis in order to ensure that the overall module temperature is within thermal safety limits. The main focus of the overall design is on compactness, miniaturization, and efficiency enhancement.

Keywords: small satellites, power subsystem, efficiency, MPPT

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Authors: Manel Hammami, Gabriele Grandi

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In recent years, multilevel inverters have become more attractive for single-phase photovoltaic (PV) systems, due to their known advantages over conventional H-bridge pulse width-modulated (PWM) inverters. They offer improved output waveforms, smaller filter size, lower total harmonic distortion (THD), higher output voltages and others. The most common multilevel converter topologies, presented in literature, are the neutral-point-clamped (NPC), flying capacitor (FC) and Cascaded H-Bridge (CHB) converters. In both NPC and FC configurations, the number of components drastically increases with the number of levels what leads to complexity of the control strategy, high volume, and cost. Whereas, increasing the number of levels in case of the cascaded H-bridge configuration is a flexible solution. However, it needs isolated power sources for each stage, and it can be applied to PV systems only in case of PV sub-fields. In order to improve the ratio between the number of output voltage levels and the number of components, several hybrids and asymmetric topologies of multilevel inverters have been proposed in the literature such as the FC asymmetric H-bridge (FCAH) and the NPC asymmetric H-bridge (NPCAH) topologies. Another asymmetric multilevel inverter configuration that could have interesting applications is the cascaded asymmetric H-bridge (CAH), which is based on a modular half-bridge (two switches and one capacitor, also called level doubling network, LDN) cascaded to a full H-bridge in order to double the output voltage level. This solution has the same number of switches as the above mentioned AH configurations (i.e., six), and just one capacitor (as the FCAH). CAH is becoming popular, due to its simple, modular and reliable structure, and it can be considered as a retrofit which can be added in series to an existing H-Bridge configuration in order to double the output voltage levels. In this paper, an original and effective method for the analysis of the DC-link voltage ripple is given for single-phase asymmetric H-bridge multilevel inverters based on level doubling network (LDN). Different possible configurations of the asymmetric H-Bridge multilevel inverters have been considered and the analysis of input voltage and current are analytically determined and numerically verified by Matlab/Simulink for the case of cascaded asymmetric H-bridge multilevel inverters. A comparison between FCAH and the CAH configurations is done on the basis of the analysis of the DC and voltage ripple for the DC source (i.e., the PV system). The peak-to-peak DC and voltage ripple amplitudes are analytically calculated over the fundamental period as a function of the modulation index. On the basis of the maximum peak-to-peak values of low frequency and switching ripple voltage components, the DC capacitors can be designed. Reference is made to unity output power factor, as in case of most of the grid-connected PV generation systems. Simulation results will be presented in the full paper in order to prove the effectiveness of the proposed developments in all the operating conditions.

Keywords: asymmetric inverters, dc-link voltage, level doubling network, single-phase multilevel inverter

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Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

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In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: M. Shadmand, T. Enayaty Ahangar, S. Kazemi

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Insulation system of electrical machineries is the most critical point for their durability. Depending on generator nominal voltage, its insulation system is designed. In this research, a new stator insulation system is designed by new type of mica tapes which will consequently enables us to decrease the nominal ground-wall insulation thickness for the same voltage level. By keeping constant the slot area, it will be possible to increase the copper value in stator bars which will consequently able us to increase the nominal output current of turbo-generator. This will affect the cooling capability of machinery to some extent. But by considering the thermal conductivity of new insulating system which is improved, it is possible to increase the output power of generator up to 6% more. This research is done practically on a 200 MVA and 15.75 kV turbo-generators which its insulating system is Resin Rich (RR).

Keywords: insulation system, resin rich, VPI, upgrading

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Authors: Xinke Huang, Huan Wang, Lidong Guo, Changbin Ju, Runbiao Liu, Guoen Cao, Yibo Wang, Honghua Xu

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Grid connected photovoltaic (PV) power system is to be developed in the direction of large-scale, clustering. Large-scale PV generation systems connected to HVDC grid have many advantages compared to its counterpart of AC grid, and DC connection is the tendency. DC/DC converter as the most important device in the system, has become one of the hot spots recently. The paper proposes a Quasi Z-Source(QZS) based Boost Full Bridge Isolated DC/DC Converter(BFBIC) topology as a basis power module and combination through input parallel output series(IPOS) method to improve power capacity and output voltage to match with the HVDC grid. The topology has both traditional voltage source and current source advantages, it permit the H-bridge short through and open circuit, which adopt utility duty cycle control and achieved input current and output voltage balancing through input current sharing control strategy. A ±10kV/200kW system model is built in MATLAB/SIMULINK to verify the proposed topology and control strategy.

Keywords: PV Generation System, Cascaded DC/DC converter, HVDC, Quasi Z Source Converter

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Authors: Voodi Kalandhar, Veera Reddy, Yuva Tejasree

Abstract:

Researchers have become interested in multilevel inverters (MLI) because of their potential for medium- and high-power applications. MLIs are becoming more popular as a result of their ability to generate higher voltage levels, minimal power losses, small size, and low price. These inverters used in high voltage and high-power applications because the stress on the switch is low. Even though many traditional topologies, such as the cascaded H-bridge MLI, the flying capacitor MLI, and the diode clamped MLI, exist, they all have some drawbacks. A complicated control system is needed for the flying capacitor MLI to balance the voltage across the capacitor and diode clamped MLI requires more no of diodes when no of levels increases. Even though the cascaded H-Bridge MLI is popular in terms of modularity and simple control, it requires more no of isolated DC source. Therefore, a topology with fewer devices has always been necessary for greater efficiency and reliability. A new single-phase MLI topology has been introduced to minimize the required switch count in the circuit and increase output levels. With 3 dc voltage sources, 8 switches, and 13 levels at the output, this new single- phase MLI topology was developed. To demonstrate the proposed converter's superiority over the other MLI topologies currently in use, a thorough analysis of the proposed topology will be conducted.

Keywords: DC-AC converter, multi-level inverter (MLI), diodes, H-bridge inverter, switches

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Authors: Yakup Sahin, Naim Suleyman Ting, Ismail Aksoy

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In this paper, a single phase soft switched Zero Voltage Transition and Zero Current Transition (ZVT-ZCT) Power Factor Correction (PFC) boost converter is proposed. In the proposed PFC converter, the main switch turns on with ZVT and turns off with ZCT without any additional voltage or current stresses. Auxiliary switch turns on and off with zero current switching (ZCS). Also, the main diode turns on with zero voltage switching (ZVS) and turns off with ZCS. The proposed converter has features like low cost, simple control and structure. The output current and voltage are controlled by the proposed PFC converter in wide line and load range. The theoretical analysis of converter is clarified and the operating steps are given in detail. The simulation results of converter are obtained for 500 W and 100 kHz. It is observed that the semiconductor devices operate with soft switching (SS) perfectly. So, the switching power losses are minimum. Also, the proposed converter has 0.99 power factor with sinusoidal current shape.

Keywords: power factor correction, zero-voltage transition, zero-current transition, soft switching

Procedia PDF Downloads 768

Authors: Hyun Young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon Cho, Yong Seo Koo

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In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp

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Authors: Maninder Kaur Gill, Alpana Agarwal

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It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values.

Keywords: Device Under Test (DUT), open loop voltage gain, operational amplifier, test circuit

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Authors: Ling Ai Wong, Hussain Shareef, Azah Mohamed, Ahmad Asrul Ibrahim

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The installation of photovoltaic based distributed generation (PVDG) in active distribution system can lead to voltage fluctuation due to the intermittent and unpredictable PVDG output power. This paper presented a method in mitigating the voltage rise by optimally locating and sizing the battery energy storage system (BESS) in PVDG integrated distribution network. The improved firefly algorithm is used to perform optimal placement and sizing. Three objective functions are presented considering the voltage deviation and BESS off-time with state of charge as the constraint. The performance of the proposed method is compared with another optimization method such as the original firefly algorithm and gravitational search algorithm. Simulation results show that the proposed optimum BESS location and size improve the voltage stability.

Keywords: BESS, firefly algorithm, PVDG, voltage fluctuation

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Authors: Yasunori Kobori, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi

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In this paper, we study a Pulse-WidthModulation (PWM) controlled Zero-Voltage-Switching (ZVS) for single-inductor dual-output (SIDO) converters. This method can meet the industry demands for high efficiency due to ZVS and small size and low cost, thanks to single-inductor per multiple voltages. We show the single inductor single-output (SISO) ZVS buck converter with its operation and simulation and then the experimental results. Next proposed ZVS-PWM controlled SIDO converters are explained in the simulation. Finally we have proposed EMI reduction method with spread spectrum.

Keywords: DC-DC switching converter, zero-oltage switching control, single-inductor dual-output converter, EMI reduction, spread spectrum

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Authors: L. Hassaine, A. Mraoui, M. R. Bengourina

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In photovoltaic system, connected to the grid, the main goal is to control the power that the inverter injects into the grid from the energy provided by the photovoltaic generator. This paper proposes a control technique for a photovoltaic system connected to the grid based on the digital pulse-width modulation (DSPWM) which can synchronise a sinusoidal current output with a grid voltage and generate power at unity power factor. This control is based on H-Bridge inverter controlled by bipolar PWM Switching. The electrical scheme of the system is presented. Simulations results of output voltage and current validate the impact of this method to determinate the appropriate control of the system. A digital design of a generator PWM using VHDL is proposed and implemented on a Xilinx FPGA.

Keywords: grid connected photovoltaic system, H-Bridge inverter, control, bipolar PWM

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Authors: Mengesha Mamo Wogari

Abstract:

In this paper, low voltage multiphase brushless DC motor with square wave air-gap flux distribution for electric vehicle application is proposed. Ten-phase, 5 kW motor, has been designed and simulated by finite element methods demonstrating the desired high torque capability at low speed and flux weakening operation for high-speed operations. The motor torque is proportional to number of phases for a constant phase current and air-gap flux. The concept of vector control and simple space vector modulation technique is used on MATLAB to control the motor demonstrating simple switching pattern for selected number of phases. The low voltage DC and inverter output AC are desired characteristics to avoid any electric shock in the vehicle, accidentally and during abnormal conditions. The switching devices for inverter are of low-voltage rating and cost effective though their number is equal to twice the number of phases.

Keywords: brushless DC motors, electric Vehicle, finite element methods, Low-voltage inverter, multiphase

Procedia PDF Downloads 117

Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

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This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

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Authors: Vahid Rashtchi, Ashkan Pirooz

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This paper applies the Imperialist Competitive Algorithm (ICA) to find the optimal place and size of Static Compensator (STATCOM) in power systems. The output of the algorithm is a two dimensional array which indicates the best bus number and STATCOM's optimal size that minimizes all bus voltage deviations from their nominal value. Simulations are performed on IEEE 5, 14, and 30 bus test systems. Also some comparisons have been done between ICA and the famous Particle Swarm Optimization (PSO) algorithm. Results show that how this method can be considered as one of the most precise evolutionary methods for the use of optimum compensator placement in electrical grids.

Keywords: evolutionary computation, imperialist competitive algorithm, power systems compensation, static compensators, voltage profile

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Authors: Magdy B. Eteiba, Wael Ismael Wahba, Shimaa Barakat

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This paper presents a fault identification, classification and fault location estimation method based on Discrete Wavelet Transform and Adaptive Network Fuzzy Inference System (ANFIS) for medium voltage cable in the distribution system. Different faults and locations are simulated by ATP/EMTP, and then certain selected features of the wavelet transformed signals are used as an input for a training process on the ANFIS. Then an accurate fault classifier and locator algorithm was designed, trained and tested using current samples only. The results obtained from ANFIS output were compared with the real output. From the results, it was found that the percentage error between ANFIS output and real output is less than three percent. Hence, it can be concluded that the proposed technique is able to offer high accuracy in both of the fault classification and fault location.

Keywords: ANFIS, fault location, underground cable, wavelet transform

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Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

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In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

Procedia PDF Downloads 369

Authors: H. H. Goh, Q. S. Chua, S. W. Lee, B. C. Kok, K. C. Goh, K. T. K. Teo

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At present, the evaluation of voltage stability assessment experiences sizeable anxiety in the safe operation of power systems. This is due to the complications of a strain power system. With the snowballing of power demand by the consumers and also the restricted amount of power sources, therefore, the system has to perform at its maximum proficiency. Consequently, the noteworthy to discover the maximum ability boundary prior to voltage collapse should be undertaken. A preliminary warning can be perceived to evade the interruption of power system’s capacity. The effectiveness of line voltage stability indices (LVSI) is differentiated in this paper. The main purpose of the indices is used to predict the proximity of voltage instability of the electric power system. On the other hand, the indices are also able to decide the weakest load buses which are close to voltage collapse in the power system. The line stability indices are assessed using the IEEE 14 bus test system to validate its practicability. Results demonstrated that the implemented indices are practically relevant in predicting the manifestation of voltage collapse in the system. Therefore, essential actions can be taken to dodge the incident from arising.

Keywords: critical line, line outage, line voltage stability indices (LVSI), maximum loadability, voltage collapse, voltage instability, voltage stability analysis

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Authors: K. A. Chinmaya, M. Udaya Bhaskar

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Multiphase motor drives are now a day considered for numerous applications due to the advantages that they offer when compared to their three-phase counterparts. Proper modeling of inverters and motors are important in devising an appropriate control algorithm. This paper develops a complete modeling of a five-phase inverter and five-phase space vector modulation schemes which can be used for five-phase motor drives. A novel modified algorithm is introduced which enables the sinusoidal output voltages up to certain voltage value. The waveforms of phase to neutral voltage are compared with the different modulation techniques and also different modulation indexes in terms of Low-order Harmonic (LH) voltage of 3rd and 7th present. A detailed performance evolution of existing and newly modified schemes is done in terms of Total Harmonic Distortion (THD).

Keywords: multi-phase drives, space vector modulation, voltage source inverter, low order harmonic voltages, total harmonic distortion

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Authors: Yakup Sahin, Naim Suleyman Ting, Ismail Aksoy

Abstract:

A 1 kW power factor correction boost converter with an active snubber cell is presented in this paper. In the converter, the main switch turns on under zero voltage transition (ZVT) and turns off under zero current transition (ZCT) without any additional voltage or current stress. The auxiliary switch turns on and off under zero current switching (ZCS). Besides, the main diode turns on under ZVS and turns off under ZCS. The output current and voltage are controlled by the PFC converter in wide line and load range. The simulation results of converter are obtained for 1 kW and 100 kHz. One of the most important feature of the given converter is that it has direct power transfer as well as excellent soft switching techniques. Also, the converter has 0.99 power factor with the sinusoidal input current shape.

Keywords: power factor correction, direct power transfer, zero-voltage transition, zero-current transition, soft switching

Procedia PDF Downloads 930

Authors: Saif Alomari

Abstract:

The paper aims at giving physical and mathematical descriptions of how the structural parameters of a resonant tunnelling diode (RTD) affect its output characteristics. Specifically, the value of the peak voltage, peak current, peak to valley current ratio (PVCR), and the difference between peak and valley voltages and currents ΔV and ΔI. A simulation-based approach using the Non-Equilibrium Green Function (NEGF) formalism based on the Silvaco ATLAS simulator is employed to conduct a series of designed experiments. These experiments show how the doping concentration in the emitter and collector layers, their thicknesses, and the width of the barriers and the quantum well influence the above-mentioned output characteristics. Each of these parameters was systematically changed while holding others fixed in each set of experiments. Factorial experiments are outside the scope of this work and will be investigated in future. The physics involved in the operation of the device is thoroughly explained and mathematical models based on curve fitting and underlaying physical principles are deduced. The models can be used to design devices with predictable output characteristics. These models were found absent in the literature that the author acanned. Results show that the doping concentration in each region has an effect on the value of the peak voltage. It is found that increasing the carrier concentration in the collector region shifts the peak to lower values, whereas increasing it in the emitter shifts the peak to higher values. In the collector’s case, the shift is either controlled by the built-in potential resulting from the concentration gradient or the conductivity enhancement in the collector. The shift to higher voltages is found to be also related to the location of the Fermi-level. The thicknesses of these layers play a role in the location of the peak as well. It was found that increasing the thickness of each region shifts the peak to higher values until a specific characteristic length, afterwards the peak becomes independent of the thickness. Finally, it is shown that the thickness of the barriers can be optimized for a particular well width to produce the highest PVCR or the highest ΔV and ΔI. The location of the peak voltage is important in optoelectronic applications of RTDs where the operating point of the device is usually the peak voltage point. Furthermore, the PVCR, ΔV, and ΔI are of great importance for building RTD-based oscillators as they affect the frequency response and output power of the oscillator.

Keywords: peak to valley ratio, peak voltage shift, resonant tunneling diodes, structural parameters

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